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This paper presents a 14-bit hybrid column-parallel compact analog-to-digital converter (ADC) for the application of digital infrared focal plane arrays (IRFPAs) with compromised power and speed performance. The proposed hybrid ADC works in two phases: in the first phase, a 7-bit successive approximation register (SAR) ADC performs coarse quantization; in the second phase, a 7-bit single-slope (SS) ADC performs fine quantization to complete the residue voltage conversion. In this work, the number of unit capacitors is reduced to 1/128th of that of a conventional 14-bit SAR ADC, which is beneficial for the application of small pixel-pitch IRFPAs. In this work, a tradeoff segmented thermometer-coded digital-to-analog converter (DAC) is adopted in the first 7-bit coarse quantization process: the lower 3-bit is binary coded, and the upper 4-bit is thermometer coded. A thermometer-coded DAC can improve the linearity of ADC. Capacitor array matching can be incredibly relaxed compared with a binary-weight 14-bit SAR ADC, resulting in a noncalibration feature. Moreover, by sharing DAC and comparator analog circuits between the SAR ADC and the SS ADC, the power consumption and layout area are consequently reduced. The proposed hybrid ADC was fabricated using a 180 nm CMOS process. The measurement results show that the proposed ADC has a differential nonlinearity of −0.61/+0.84 LSB and a sampling rate of 120 kS/s. The developed ADC achieves a temporal noise of 1.7 LSBrms at a temperature of 77 K. In addition, the SNDR is 72.9 dB, and the ENOB is 11.82 bit, respectively. Total power consumption is 71 μW from supply voltages of 3.3 V (analog) and 1.8 V (digital). [ABSTRACT FROM AUTHOR]

This letter presents a low‐power single‐slope analog‐to‐digital converter (ADC) for column‐parallel architectures. A simple and effective design technique is proposed to solve the input‐dependent power consumption problem of the conventional single‐slope ADCs. A decision‐feedback loop is implemented in the second stage of the comparator. Based on the negative‐feedback path, which is activated after the signal decision of the comparator, the input‐dependent dynamic current path in the amplifier is disabled. Furthermore, an additional low‐power design technique is proposed to save the power consumption of the ADC by optimizing the offset cancelling auto‐zero period. With the combination of the proposed techniques, the power consumption of the single‐slope ADC can be effectively saved while suppressing the dynamic current. [ABSTRACT FROM AUTHOR]

This paper presents a novel dynamic bias latch‐type comparator combined with a voltage‐controlled delay line (VCDL), designed specifically for low‐power and low‐noise applications in high‐speed analog‐to‐digital converters (ADCs). The incorporation of the VCDL precedes the dynamic bias amplifier in the proposed comparator, thereby achieving a balance between energy efficiency and high‐speed operation. This innovative design enhances the input common voltage of the dynamic bias amplifier through the utilization of the VCDL, surpassing that of a conventional dynamic bias comparator. Furthermore, it demonstrates increased adaptability in technology scaling and efficient operation at lower supply voltages, leveraging inverters and other simple cells. The proposed comparator in 28 nm process technology achieves a 309.7 µV input‐referred noise while consuming approximately 145.8 fJ and completing comparisons in 125 ps with a 0.9 V supply and a 0.45 V input common‐mode voltage. [ABSTRACT FROM AUTHOR]

An 11-bit, power efficiency, two-stage SAR-voltage-controlled oscillator (VCO) hybrid ADC is proposed in this work. Taking full advantage of the voltage-to-phase and voltage-to-frequency characteristics, the reused ring-VCO circuit acts as not only a time-domain comparator with the phase detector assistance for low power consumption in the first SAR stage but also a fine quantizer in the second stage. More importantly, the gain nonlinearity of the VCO can be effectively suppressed due to the small residue voltage after the coarse quantization. In addition, the VCO-based ADC (except for the ring-VCO circuit) only works in the quantization phase instead of the whole conversion period. As a result, the power consumption and area of the comparator in the previous SAR-VCO ∆Σ ADC can be thoroughly avoided. Besides, compared to an 11-bit SAR ADC, the capacitor mismatch can be relaxed theoretically by 2 × in the identical capacitor array area. Post-simulation results demonstrate that the proposed ADC in a 0.18 μm CMOS process exhibits a signal-to-noise and distortion ratio (SNDR) of 63.8 dB, and it dissipates 2.1 μW power from a 0.6 V supply with a sampling rate of 50 kS/s and a Nyquist input rate. To the author's knowledge, the hybrid ADC can achieve the best Walden figure of merit (FoMw) of 33.3 fJ/conversion-step compared with the previous SAR-VCO hybrid ADC, and its active area is only 0.109 mm2. [ABSTRACT FROM AUTHOR]

This paper presents the realization of binary and floating-point comparators on FPGA. The implementation is done by exploiting the primitive instantiation of FPGA resources which has enabled a significant improvement in resource utilization in terms of Look-Up Table (LUT) usage and overall combinational path delay when compared to the conventional inference approach. The comparator architectures are implemented using Vivado 2020.1 and ISE Design Suite 14.7 environment on multiple Xilinx FPGA platforms and are compared with the existing designs. The results indicate an improvement of 33.33% and 45.45% in LUT utilization, 14.41% and 30.73% in delay for 32-bit and 64-bit binary comparators respectively, compared to the existing architectures. The proposed floating-point comparator requires 88.57% and 285.29% lesser LUTs for single precision and double precision representation respectively, compared to the existing design. [ABSTRACT FROM AUTHOR]

Analog–digital converters (ADCs) are electronic circuits that convert continuous time signals into digital signals (binary data) for analyzing, estimation, and transmission. Transceivers use ADC in the baseband stage of receiver to convert the analog signals to digital form for further signal processing. At high-frequency applications, like millimeter wave applications, the ADC consumes more power due to the high sampling rate with respect to the increased bandwidth. In this article, a novel dynamic comparator is presented with delay and power analysis for the design. The expression is derived for all operational regions of the transistor. The new design is proposed for low-power consumption and reduced delay of the circuit. The novel design overcomes the drawbacks of the less operating frequency range, high latency, and more power dissipation of existing comparator designs. The proposed low-power dynamic comparator is simulated with 45 nm CMOS technology that provides total power dissipation of 33.92 µW, delay of 19.71 ps, and energy per conversion of 0.19 fJ/conv. with a supply voltage of 1 V. [ABSTRACT FROM AUTHOR]

Digital Circuits applications are expanding rapidly in modern times because they generate correct signals without errors or interferences. These digital circuits play important roles in data storage operation, as well as the implementation of image processing applications on hardware where the power, speed, and area of an electronic device play a significant role, particularly in the field of modern VLSI technology. The digital comparator with more number of bits plays an important role in image processing applications. In the proposed research paper, an attempt is made to design a speed and area efficient 32-bit comparator. To improve the speed of the comparator a modified priority encoder technique is used. It shows that the area of proposed 32-bit digital comparator consumes 573.73 units which are 20% better than when compared with the conventional comparators and the speed improved by 50% when compared with the Conventional Comparators. The proposed implementation is simulated on the 'Encounter(R) RTL Compiler RC14.28'. [ABSTRACT FROM AUTHOR]

Research on artificial neural network computing based on conventional integrated circuit chips has made significant progress, but it faces technical bottlenecks such as reduced energy consumption, computing speed, and efficiency. So, it is seeking integrated chips based on optical interconnections to solve the current dilemma. Fortunately, the small size and very localized graphene surface plasmon waves offer the possibility of optical integrated chips. In this paper, we propose a graphene-based one-bit optical numerical comparator. The comparator is located on the top of a 0.4-μm2 rectangular dielectric layer, mainly consisting of Y-shaped graphene nanoribbons. The on/off effect of the graphene nanoribbons is achieved by applying an external voltage to change the chemical potential energy of the graphene switching bands. The proposed optical numerical comparator with 9.55-μm TM mode light achieves a minimum extinction ratio of 31.12 dB and amplitude modulation of 0.77 dB, as shown by the finite-difference time-domain (FDTD) method. Compared with the current optical numerical comparators, it has the advantages of a high extinction ratio, small size, low loss, and high stability. In addition, the effect of process deviation of graphene nanoribbons on the reliability of the designed optical numerical comparator is analyzed by simulation. It is beneficial to developing integrated photonic devices and has some significance for developing ultra-high-frequency and integrating artificial neural network computing. [ABSTRACT FROM AUTHOR]

In this research, a new architecture of dynamic latch comparator is presented, which is able to provide high-speed, consumes low-power and low offset voltage. The proposed comparator has been verified in a design, a 12-Bit SAR ADC(Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter). The comparator consists of two stage pre-amplifier and a StrongLatch. The pre-amplifier adopts an inverter-based input pair and a pair of capacitances in output stage to reduce noise. It is shown by simulation and analysis that the offset voltage is significantly reduced compared to a conventional dynamic latched comparator. The proposed circuit is designed and simulated in 28 nm CMOS technology. The results show that, for the proposed comparator, the speed is 2.37 ns and consumes only 426.6 μ W power, at 1.8 V supply voltage and 330 MHz clock frequency. This article presents two kinds of FoM(Figure of Merit) to prove that the comparator has excellent performance. • Analysis of offset source of differential pairs. • Optimize comparator design. • Validate the comparator design. [ABSTRACT FROM AUTHOR]

Summary: This paper presents an energy‐efficient fully differential switching scheme for successive approximation register (SAR) analog‐to‐digital converters (ADCs). During the sampling phase, the top and bottom plates of all capacitors except most significant bit (MSB) capacitors are grounded in digital‐to‐analog converter (DAC) arrays. The input signals are bottom plate sampled on MSB capacitors. This technique can reduce the settling time by more than 87.5% in comparison with the conventional switching scheme. Furthermore, a novel reset‐free regenerative comparator is unveiled in this paper. The proposed comparator is armed to amplify its inputs both during the reset and evaluation phases. In comparison with a conventional single‐ended comparator, the proposed comparator can reduce power consumption above 90% for the almost same input‐referred offset voltage. The proposed scheme is designed with a resolution of 8‐bit and a sampling rate of 90 MS/s in a standard 65‐nm CMOS technology. The simulation results certify that the ADC dissipates 363‐μW power with a 1.2‐V supply voltage and achieves a 7.13 effective number of bits (ENOBs), yielding a 28.8 fJ/conversion step Nyquist rate Walden FOM. [ABSTRACT FROM AUTHOR]

The power optimization is one of the biggest challenging issues for designing of VLSI circuits within the advanced technology. The reversible logic is one among the best approaches for low power application. This logic has wide applications in the communication, nanotechnology, digital signal processing, computer graphics, optical computing, etc. In this paper, some proposed reversible magnitude comparator has been designed using the prevailing reversible gates and implemented using gate diffusion input (GDI) technique. The design methodologies are also proposed for the designing of N-bit comparator. The main objective of this paper is to design and implementation of reversible magnitude comparator using some proposed methods and compares them with the existing circuits in terms of constant input, garbage output, number of reversible gates, and quantum cost. The transistor implementations of the proposed comparators are done by the combination of CMOS and GDI technique in EDA Tanner tools. After the design and analysis of proposed comparators it has been found that the proposed-2 logic based 4-bit comparator has lowest quantum cost which is equal to 38 and the proposed-3 logic based 4-bit comparator has lowest constant input and garbage output which is equal to 8 and 13. [ABSTRACT FROM AUTHOR]

This letter presents an 11 b 200 MS/s 28 nm CMOS 2b/cycle successive-approximation register (SAR) analogue-to-digital converter (ADC). The offset calibration technique is proposed to reduce the comparator offset mismatch that degrades the linearity of the high-resolution 2b/cycle SAR ADC. The offset mismatch is reduced to within 0.25 least significant bit (LSB) by generating a compensation voltage from capacitor-resistor (C-R) hybrid digital-to-analogue converters (DACs). The prototype ADC implemented in a 28-nm CMOS process demonstrates measured differential and integral non-linearities within 0.6 LSB and 1.73 LSB at 11 b resolution, respectively. The measured signal-to-noise-and-distortion ratio (SNDR) and spuriousfree dynamic range (SFDR) are 50.9 dB and 66.2 dB at Nyquist, respectively. The prototype ADC occupies an active die area of 0.115 mm² and consumes 3.98 mW at a 1.1-V supply voltage. [ABSTRACT FROM AUTHOR]

Localized data conversions for sensors placed under harsh environmental conditions often require Analog to Digital Converters (ADC) capable of working under wide operating temperature range. Even though the fastest analog to digital converter, flash ADC is omitted from the high temperature regime due to the requirements of reference voltage source, reference voltage divider and a comparator array capable of providing stable operation under wide operating temperatures. A CMOS Schmitt inverter-based internal reference comparator array for flash ADC which is efficient in terms of area and power consumption, capable of working under wide temperature range is presented in this paper. The proposed idea replaces the reference voltage source, resistive reference voltage divider and differential comparator array of a conventional flash ADC by an array of suitably sized Schmitt inverters. The circuit was simulated for static and dynamic characteristics with gpdk 180 nm library using cadence virtuoso simulation suite. The voltage transfer characteristic curve (VTC) of the proposed comparator array was found invariable when a temperature sweep in the range of −40 to 170 degree Celsius was performed. Each of the comparator in the proposed array consumes a silicon area of 40.68 u m 2 and the average dynamic power consumption per cycle is estimated as 103.1 uW. [ABSTRACT FROM AUTHOR]

This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications. [ABSTRACT FROM AUTHOR]

In this paper, a modified successive-approximation-register analog-to-digital converter (SAR ADC) with a novel low power dynamic comparator at 0.2 V supply voltage is presented. The power consumption of SAR ADC has been reduced by 70% with design of proposed low-power comparator and using power reduction techniques such as power gating and reducing the supply voltage. Also, by custom design for unit capacitor in the SAR ADC, the area has been reduced by 46% compared to the conventional structure. The proposed ADC with a sampling frequency of 1 kS/s and power consumption of only 1.21 nW for biomedical applications has been designed and simulated in a TSMC 65 nm CMOS technology and occupies an area of 0.013 m m 2. The proposed biomedical ADC is verified using analog electroencephalogram (EEG) and electrocardiogram (ECG) inputs which demonstrate it is proper to quantize these biosignals. The figure-of-merit (FOM) of the proposed converter is 3.2 fJ/conversion-step. • Designing a modified ADC with an ultra low supply voltage (0.2 V) for biosignals acquisition. • Designing a novel 0.2 V, ultra low power dynamic comparator. • The power consumption of SAR ADC has been reduced by 70% with design of proposed low-power comparator and using power reduction techniques such as power gating and reducing the supply voltage. • 46% reduction of occupied area using custom capacitor design. [ABSTRACT FROM AUTHOR]

This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks—an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it. [ABSTRACT FROM AUTHOR]

This paper presents a 16-bit 1-Msps successive-approximation-register analog-to-digital converter (ADC) with a split-ADC digital calibration scheme based on dynamic element matching. A multi-segment capacitor array with redundant bits is utilised for ensuring that missing-level errors are calibrated in the digital domain, reducing the area and power consumption. The key circuit modules are optimised, such as the low-power dual-mode cascade comparator and dynamic element matching control logic. The prototype is fabricated by a 0.18-μm CMOS technology, and it exhibits 170.47 dB figure of merit Schreier (FoMs), 15.04 bits effective number of bits (ENOB) and 119.50 dB spurs free dynamic range (SFDR). The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.422/0.536 LSB and −0.721/0.758 LSB, respectively. • A 16-bit 1 Msps SAR ADC is manufactured in 0.18 μm CMOS process with 170.47 dB FoMs. • A split-ADC digital calibration scheme based on dynamic element matching can improve the SFDR effectively. • A segmented capacitor array of 4 sub-capacitor arrays decreases the total capacitance of the high-resolution SAR ADC. • A dual-mode automatic zero comparator is utilised to reduce power consumption. [ABSTRACT FROM AUTHOR]

In this letter, a new rail‐to‐rail two‐stage regenerative comparator for low supply voltage applications is presented. A rail‐to‐rail operation is achieved by utilizing an inverse inverter pre‐amplifier. The proposed comparator is post‐layout simulated within a standard 180‐nm CMOS technology. In the worst‐case scenario, the energy efficiency and the delay of the comparator are improved by more than 80% compared to the conventional single‐stage comparator. [ABSTRACT FROM AUTHOR]

A new 1-bit digital comparator named 14T-SR-GDI is presented with gate-diffusion-input (GDI) and single-swing-restoration (SR) techniques to attain internal gates with high driving capability. The comparator has 14 transistors which produce full-swing outputs with low power consumption. In the 14T-SR-GDI, boosted inner signals are used to activate the output gates which result in a high-speed circuit with effective scalability and the enhanced driving capability for multi-bit structures. The comparator has a low power delay product (PDP) due to the small numbers of internal nodes and capacitances and efficient power-ground-free gates. The 14T-SR-GDI comparator, fully SR-GDI-based AND, and OR gates, construct a new tree structure for multi-bit magnitude comparators including 2-bit, 4-bit, 8-bit, and 16-bit comparators. The proposed 1-bit comparator is used in image processing for difference detection, and its efficiency is proved by image quality parameters. The post-layout simulations are performed for the 1-bit to 16-bit structures under TSMC 90 nm technology. The extracted results express a PDP with an average difference of 9.59% between the regular and post-layout modes. Also, the proposed 16-bit comparator is embedded in a pad with a total area of 4331.25 μm2. The designed magnitude comparators are key components in digital signal processors (DSPs). [ABSTRACT FROM AUTHOR]

We present a highly robust 12-bit, 100 kS/s Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) that excels in mitigating the effects of mismatch, temperature variations and process corners. A modified hybrid switching method is developed in design of the Capacitive Digital-to-Analog Converter (C-DAC) that saves 17 % of the DAC power consumption. Furthermore, we utilize a switched local feedback loop in the pre-amplifier circuit of the comparator that significantly minimizes the offset. Using this technique, the 3-sigma offset is reduced from 11.33 mV to 0.37 mV. Moreover, a high performance latched-based Bit Slice Unit (BSU) is proposed to preserve the successive codes during each conversion. Designed in 65 nm CMOS technology, the ADC operates in −55 °C to +125 °C temperature range, consuming only 1.55 μW with a 0.7V supply voltage and occupying a 0.6 mm2 area. [ABSTRACT FROM AUTHOR]

A dynamic comparator is the core element in high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. The majority of the dynamic comparators can only operate at high speeds when the input difference voltage is large enough. Due to the limited pre-amplifier gain, the comparators' performance deteriorates at lower input difference voltages, which is not suitable for high-speed, high-resolution ADCs. A double-tail dynamic comparator with a pair of auxiliary inverters is proposed to alleviate this problem. With the proposed comparator, the pre-amplifier's differential gain is increased, and the latch regeneration time is reduced by the auxiliary inverter pair resulting in faster comparison operations. The proposed comparator is designed, simulated, and compared with the latest topologies in 65 nm CMOS technology. The performance metrics such as delay, kickback noise, energy consumption per bit, rms noise, and power delay product are evaluated and compared with the state-of-the-art architectures. The proposed technique can be applied to any dynamic comparator that has differential signals at the output of the pre-amplifier stage. Simulations show that the auxiliary inverter pair improves the comparator's speed by more than 10%. [ABSTRACT FROM AUTHOR]

This paper presents a low voltage energy-efficient 10-bit SAR ADC. A double-merge and split (DMAS) switching scheme is proposed to reduce the CDAC switching energy by 92.2 % compared with conventional one without extra reference voltage (V CM ). Gain tunable voltage-controlled delay unit (GT-VCDU) is proposed for offset calibration of time-domain comparator (TD-CMP). The residual offset is reduced by proposed stage-by-stage calibration. 1 sigma of TD-CMP offset is reduced to 0.8 mV. The SAR ADC is fabricated in the 55 nm CMOS process occupied a core area of 0.038 m m 2. With a supply voltage of 0.5 V and a Nyquist rate input, the prototype consumes 164 nW at 100kS/s. The ENOB is 8.86-bit, resulting a FoM of 3.53 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

In this paper, a low-power, small-area SAR-VCO ADC is proposed using a highly linear and single-path differential VCO-based quantizer. Compared to conventional digital solution or analog design, proposed digital synthesizable dynamic voltage comparator (DVC) employs a two-stage structure, which reduces the comparator delay and offset and saves chip area. Furthermore, improved differential voltage-to-current (V–I) converter enables the realization of a single-path differential VCO-based quantizer. Trimming circuits enhance the robustness of VCO, compensating for variations induced by process variations. Additionally, a novel frequency-to-digital converter (FDC) is used as the fine quantization to directly measure the frequency. Finally, a SAR-VCO ADC is realized in 65 nm CMOS process. The simulation results show that the signal-to-noise distortion ratio (SNDR) is 70.16 dB under sampling rate of 7.8 MHz at oversampling rate (OSR) of 8. The proposed ADC has a supply voltage of 1.2V and a power consumption of 405 μW. It occupies an area of 0.16 mm2, and achieves an area figure of merit (FoM A) of 25.12 fJ*mm2/conversion-step. [ABSTRACT FROM AUTHOR]

Purpose: There are many types of the ADCs implemented in the mobile and wireless devices. Most of these devices are battery operated and operational at low input voltage. SAR ADC is popular for its low power operations and simple architecture. Scientists are still working to make its working faster under the same low power area. There are many SAR-ADC implemented in the past two decades, but still, there is a big room for dual SAR-ADC. Design/methodology/approach: The authors are presenting a dual SAR-ADC with a smaller number of components and blocks. The proposed ultra-low-power circuit of the SAR-ADC consists of four major blocks, which include Bee-bootstrap, Spider-Latch dual comparator, dual SAR-logic and dual digital to analog converter. The authors have used the 90-nm CMOS library for the construction of the design. Findings: The power breaks down of the comparator are dramatically improved from 0.006 to 0.003 uW. The ultimate design has 5 MHz operating frequency with 25 KS/s sampling frequency. The supply voltage is 1.2 V with 35.724 uW power consumption. Signal-to-noise and distortion ratio and spurious-free dynamic range are 65 and 84 dB, respectively. The Walden's figure of merits calculated 7.08 fj/step. Originality/value: The authors are proposing two-in-one circuit for SAR-ADC named as "dual SAR-ADC", which obeys the basic equation of duality, derived and proved under the heading of proposed solution. It shows a clear difference between the performance of two circuit-based ADC and one dual circuit ADC. The number of components is reduced by sharing the work load of some key components. [ABSTRACT FROM AUTHOR]

In the field of low power VLSI, the charge recovery property of adiabatic logic has been liked by the VLSI researchers. And this stimulates the research of various charge recovery techniques for low power computation. The applications of adiabatic logic in digital circuits are well understood, whereas mixed signals and analog circuits are yet to be explored. In this work, the author presents a wave shaping diode-based adiabatic logic (WSDAL) driven strong ARM comparator. The proposed ARM comparator consumes a power of 0.46 µW as compared to 14.41 µW and 8.77 µW as that of traditional strong ARM and adiabatic driven strong ARM, respectively. The reduction in power dissipation is achieved by three ways, (1) the proposed design consists of WSDAL based invertor for SR latch inputs that reduces the power dissipation up to a great extent by charge recycling through PCb (power clock bar). (2) The magnitude of PCb is half as that of PC (power clock), which reduces the node voltage difference and ultimately reduces the power dissipation, (3) the leakage and short circuit components of current get reduced utilizing PC as a sinusoidal supply. The proposed design also shows better thermal stability with varying temperature conditions. [ABSTRACT FROM AUTHOR]

This paper presents a scalable Fully-digital differential analog voltage comparator designed in Semi-Conductor Laboratory (SCL) 180 nm complementary metal-oxide semiconductor technology. The proposed design is based on a digital design approach and is easily configurable to lower technology nodes. This design methodology makes the circuit less sensitive to process variations and takes fewer design efforts suitable for Systems-on-a-Chips (SOCs) application. The proposed circuit is designed and simulated in Cadence Virtuoso Analog Design Environment at the supply voltage ranging from 1 V to 1.8 V. The fully-digital analog voltage comparator has been synthesized using Synopsys Design Vision and auto-placed & auto-routed using Synopsys IC Compiler. This proposed comparator has a resolution of up to 7-bit at a supply voltage of 1.8 V and a worst-case operating frequency of about 750 MHz at the TT corner. The obtained value of the offset voltage and delay is 0.55 mV and 0.72 ns, respectively. The simulated results have shown that the power dissipation of the proposed scalable analog voltage comparator is 1 5 0 μ W @ 1 V and 3 1 2 μ W @ 1. 8 V supply voltage, respectively. Also, the RC extracted post-layout simulations have been implemented to verify the performance, which does not affect the results much. [ABSTRACT FROM AUTHOR]

Reduced voltage head room availability for input signal swing is one of the major bottlenecks in the design of circuits operating with low supply voltages which attracts investigations leading to improvement in the input signal dynamic range of such circuits. Employing bulk-driven MOSFETs (BDMOS) at the input section of the circuit is a popular technique used for increasing the input dynamic range, but the smaller bulk transconductance of the bulk-driven MOSFET degrades the performance of the circuit in comparison with that of a conventional gate-driven counterpart. A double tail voltage comparator employing BDMOS technique offering rail-to-rail input dynamic range and capable of operating at sub-1 V power supply is presented in this paper. A transconductance improvement scheme is employed for the first time in the literature for a voltage comparator to overcome the major drawbacks associated with the reduced bulk transconductance of BDMOS input transistors and double tail topology permits low voltage operation. The performance parameters of the proposed voltage comparator are comparable to that of conventional gate-driven comparators, with an additional advantage of rail-to-rail input dynamic range. Pre-layout and post-layout simulations were performed in Cadence Virtuoso suite with gpdk 90 nm library at power supply as low as 0.6 V. The worst case delay of the proposed circuit is 0.71 ns and the worst case power consumption of the circuit is 15 uW. The circuit consumes a silicon area of 33 μm × 46 μm. An analytical model of the transconductance enhancement technique and delay of the proposed comparator are also presented. [ABSTRACT FROM AUTHOR]

In low power electronics technology, a lot of new technology has already been introduced to reduce the power consumption of comparator. This paper presents the comparative study of preamplifier circuit on power consumption and delay prospects. The preamplifiers are explained to make the clear difference in the state-of the art. Every circuit has their own importance in the different application such as analog-to-digital converter and comparator. The general trend to design an efficient preamplifier is that it should have low power consumption in their operation. Operating region of preamplifier circuit is observed as sub threshold and saturation. A small modification has been performed in preamplifier in comparator circuit and compared the power and delay with the reported comparator circuits. All the preamplifier circuits are implemented on 180nm CMOS technology node. The voltage supply used 1.2 V in implemented circuit. [ABSTRACT FROM AUTHOR]

In the present scenario, power, speed, and area of an electronic device play a significant role specifically in the field of modern VLSI technology. In this research, small power dissipation and a less area-based single 12-bit comparator has been designed using a multiplexer. To improve the speed of the comparator a completely unique technique has applied, where three 4-bit comparator blocks have been used rather than a single 12-bit comparator. These comparator blocks compare simultaneously two signals each having 4-bits. The aim of this paper is to design and implement a 2-bit digital comparator using different logic techniques to compare power consumption, propagation delay, and transistor count. Finally, the novel technique has been applied to improve the overall performance of a 12-bit comparator. The results of this paper are simulated on the EDA tanner tool realized in 32-nanometer technology at 0.7 V supply voltage. It shows that the propagation delay of 12-bit digital comparator using the novel technique is 5.15 nanoseconds which is approximately 30% less than the proposed multiplexer-based single 12-bit comparator. [ABSTRACT FROM AUTHOR]

This work presents the design of a front-end MEMS piezoresistive pressure sensor readout circuit along with a drug actuator model based on TSMC 0.18 μm CMOS technology. The overall system finds application in implantable systems based on micro-pressure sensing and actuation such as the closed loop automatic micturition chip. The system consists of high performance and ultra-low noise chopper stabilized differential amplifier front-end, a digitally programmable threshold generator and window comparator circuit for setting up the pressure thresholds for urination, and an actuator model that simulates drug delivery for micturition, overactive bladder control, and bladder closure. The system also has a novel core circuit enable for power savings mode. The corresponding sub-circuits have been designed to operate in low power that is suitable for implantation and be powered by energy harvesters. [ABSTRACT FROM AUTHOR]

Quantum dot-cellular automata (QCA) technology has recently emerged as a potential candidate for the design of nanometer-scale computational circuits. In digital logic circuits, the comparator is the basic building block for comparing two binary values. This paper presents and implements two 1-bit QCA-based comparator designs. The proposed QCA implementations are compact, require only a single layer and are less complex compared to recently reported designs. The QCADesigner tool has been used to confirm the functional validity of the proposed QCA structures. The simulation results of the proposed comparators have shown considerable improvements compared to their existing counterparts in terms of the number of QCA cells and occupational area requirements in addition to cost and efficient complexity values. Furthermore, all of the proposed structures are dissipating extremely low energy values. Thus, the proposed QCA-based comparators can be viewed as viable options for low power digital applications. [ABSTRACT FROM AUTHOR]

In this paper, an area-and-energy-efficient 10-bit single-ended (SE) counter-type (CT) analog-to-digital converter (ADC) with dual 5-bit capacitive digital-to-analog converter (DAC) arrays and dual 5-bit counters is presented. The 10-bit capacitive-DAC (CDAC) array and counter of the conventional counter-type structure are divided into two 5-bit CDAC arrays and counters, respectively. Significant improvements are achieved in comparison to the conventional counter-type ADC as follows: the capacitance of the most-significant-bit (MSB) capacitor is reduced by 96.88 % from 512C to 16C; the total capacitors are reduced by 93.75 % from 1024C to 64C; the total clock cycles required in the conversion phase are reduced by 93.94 % from 1023 to 62; the average switching energy is reduced by 98.55 % from 2390CV2 to 35CV2. The proposed ADC occupies a smaller area, performs much faster, and its power consumption is greatly reduced. This structure has a simple design with small sampling capacitor (32C) and does not require a rail-to-rail comparator compared to SAR ADCs. It is suitable for biomedical and multi-channel applications. The proposed ADC is post-layout simulated in 65-nm CMOS technology which occupies 0.016 mm2 area. This ADC has 85.43 nW power consumption, 9.64 ENOB on 33.33 kS/s sampling rate, and 3.23 fJ/conversion-step FOM. [ABSTRACT FROM AUTHOR]

This paper presents a high-speed low-power cryogenic CMOS two-stage dynamic comparator for SAR ADC. The pre-amplifier uses the dynamic bias technique to save power. To increase the output voltage difference of the pre-amplifier, the StrongARM latch is inserted. The proposed latch keeps a cross-coupled inverter to ensure good positive feedback. The tail current source of the proposed latch is replaced by the input pair to suppress the through current. The auxiliary input pair enhances the gain and positive feedback to speed up the latch. The paper also presents a delay analysis of the dynamic bias technique, which gives a deep understanding and a good intuition for circuit design. The simulation results demonstrate the proposed comparator achieved a CLK-Q delay of 162.1 ps and 295.4 ps at V i d = 1 mV and V C M = 0.7 V with V D D = 1.2 V and f s = 1 GHz in 300 K and 4K. The energy per comparison is 34.04 fJ and 27.75 fJ. [ABSTRACT FROM AUTHOR]

Power supply noise in current nanometer technologies represents a growing risk, specially because of the uncertainties it produces in the critical paths delays which can result in erroneous computations. Also, these very short variations can affect the functionality of analog circuits like a comparator or an ADC. To tackle with these issues and to have a better power management, on-line power supply monitors have become one common solution. Traditional approaches use an external reference, are very sensitive to temperature and process variations or present high latency. In this work we propose a 3 sigma monitor with a novel detector circuitry that employs a feedback loop that works without an external reference and it is hardened against temperature and process variations. The sensor was designed in the 40 nm CMOS technology node, operating at 1.1 V and has been validated for a temperature range of 0 ∘ C to 85 ∘ C covering all process corners. Also, considering the 3 σ confidence, the sensor is able to detect over/undershoots voltage fluctuations up to 2 GHz in the range of -70 mV to +90 mV from the nominal voltage with a maximum latency of 1.1 ns and an energy consumption per measurement of 0.8 pJ. [Display omitted] • Power supply noise in current nanometer technologies represents a growing risk. • There is a need to tackle the supply voltage noise with a better power management. • On-line power supply monitors have become one common solution. • We propose a 3 σ monitor with a novel detector circuitry. • The monitor is hardened against temperature and process variations. • The sensor covers the commercial temperature range of 0° C to 85° C. • The proposed architecture presents small area and energy per measurement overheads. [ABSTRACT FROM AUTHOR]

The highlight of in vivo or ex vivo measurement to monitor the pH value from blood or saliva is emerging in these years since changes in pH suggest that hidden diseases are about to occur. In this paper, we design and implement a SoC for pH measurement, and a dual offset cancelation technique in comparator featured with 150‐uV input referred voltage and 1‐GHz comparison bandwidth is verified. The SoC by utilizing proposed dual offset cancelation technique can sense 8 femto farad capacitance change in the deionized water, 12 femto farad change in the glucose liquid, and 14 femto farad in the 0.5% hydrochloric acid. The SoC for pH measurement is not only used to detect pH change in blood or saliva, but can also extend to wearable device to monitor human's biomarkers such as pH and Na+ in sweat to prevent the disease in advance. [ABSTRACT FROM AUTHOR]

Single-slope analog-to-digital converter (SS ADC) and time-to-digital converter (TDC) architectures in their high-speed or high-resolution status tend to either have high-power consumption or occupy large area. However, using the hybrid structure of these two, although synchronizing them might be a limiting factor, can solve the area and power consumption issues. In this paper, a 4-bit SS ADC is combined with a 4-bit TDC. Moreover, a new low-powered continuous-time comparator architecture is designed to adjust its current based on not only the inputs amplitude but also their proximity near the flip point. In addition, a novel delay correction technique is utilized to resolve its nonlinear propagation delay. The presented technique reduces 90% nonlinearity of the comparator's propagation delay and decreases its delay variation to 450 ps. Using TSMC CMOS 130 nm technology with a sampling frequency of 5.88 MHz, the simulation result illustrates 788 μ W power consumption with the master clock frequency of 100 MHz while an integral nonlinearity (INL) of − 1.41–+0.76 LSB and a differential nonlinearity (DNL) of − 1.05–+0.05 LSB is achieved in 625 ps resolution. Finally, figure-of-merit (FoM) depicts 31.2 fJ/conv. step. The presented converter can be used in CMOS image sensors and multi-resolution applications. [ABSTRACT FROM AUTHOR]

Pt100 is a resistance temperature detector characterized by a relatively linear resistance/temperature relationship in a narrow temperature range. However, the Pt100 sensor shows a certain degree of static transfer function nonlinearity of 4.42 % in the range between −200 °C and 850 °C, which is unacceptable for some applications. As a solution to this problem, a mixed-mode linearization method based on a special dual-stage piecewise linear ADC design is proposed in this paper. The first stage of the proposed dual-stage piecewise linear ADC is performed with a low-complex and low-power flash ADC of a novel sequential design. The novelty of the proposed sequential design is reflected in the fact that the number of employed comparators is equal to the flash ADC resolution. The second stage is performed with a delta-sigma ADC with a differential input and differential reference. Using the 6-bit flash ADC of novel design and the 24-bit delta-sigma ADC, the nonlinearity error is reduced to 2.6·10−3 %, in the range between −200 °C and 850 °C. Two more ranges are examined, and the following results are obtained: in the range between 0 °C and 500 °C, the nonlinearity error is reduced from 1.99 % to 5·10−4 %, while in the range between −50 °C and 150 °C, the nonlinearity error is reduced from 0.755 % to 2.15·10−4 %. [ABSTRACT FROM AUTHOR]

In this paper, a comparator and an operational amplifier considered as essential components, constituting a 10-bit 50-MHz pipeline Analog-to-Digital Converter for Wireless Local Area Network (WLAN) applications, are described and designed. All post-layout and Monte-Carlo simulations, using a 0.35 μ m CMOS AMS process technology with 3. 3 V supply voltage and an input common-mode range of 1. 1 5 – 2. 1 5 V, are achieved. An improved clocked comparator with a dynamic latch, based on a switched capacitor network, using the current reuse technique for slew rate enhancement and positive feedback for offset voltage compensation, is presented. The operational amplifier, consisting of a fully differential folded cascode operational transconductance amplifier, providing high-gain and good stability, is exhibited. A new frequency compensation technique, based on active resistors, is used to improve amplifier phase-margin. The Monte-Carlo performance results of the designed clocked comparator provide an offset voltage of 3 2. 3 2 mV with 2. 4 9 mV 3 σ deviation, a slew rate of 8. 2 9 V/ns with 0. 4 5 V/ns 3 σ deviation, and a propagation delay of 4. 1 6 ns with 0. 1 5 ns 3 σ deviation. Monte-Carlo performance results of the designed operational amplifier provide a phase-margin of 6 3. 0 1 ∘ , and a high-gain of 7 9. 2 2 dB with 1. 9 2 ∘ and 4. 8 6 dB 3 σ , respectively, by using 1 pF load capacitance. [ABSTRACT FROM AUTHOR]

Quantum image processing focuses on the use of quantum computing in the field of digital image processing. In the last few years, this technique has emerged since the properties inherent to quantum mechanics would provide the computing power required to solve hard problems much faster than classical computers. Binarization is often recognized to be one of the most important steps in image processing systems. Image binarization consists of converting the digital image into a black and white image, so that the essential properties of the image are preserved. In this paper, we propose a quantum circuit for image binarization based on two novel comparators. These comparators are focused on optimizing the number of T gates needed to build them. The use of T gates is essential for quantum circuits to counteract the effects of internal and external noise. However, these gates are highly expensive, and its slowness also represents a common bottleneck in this type of circuit. The proposed quantum comparators have been compared with other state-of-the-arts comparators. The analysis of the implementations has shown our comparators are the best option when noise is a problem and its reduction is mandatory. [ABSTRACT FROM AUTHOR]

A voltage supply scalable analog voltage comparator for a wide input range is presented in this paper. A digital gate-based methodology is used to design the comparator in order to extend the use of automation in the analog designs. Therefore, the proposed comparator is enormously cost-effective, reduces the time-to-market, scalable to newer technologies, and more immune to process variations than the conventional CMOS analog voltage comparators. The comparator is designed using Semi-Conductor Laboratory (SCL) 180 nm digital CMOS technology at a supply voltage of 1.8 V. The power consumption of the proposed comparator is 160 µW approximately with total delay and offset voltage of 1.63 ns and 4.28 mV, respectively. Also, 4-bit and 5-bit flash ADC is designed as an application. The measured values of DNL/INL are ± 0.4/± 0.4 LSB and 0.42/± 0.6 LSB for 4-bit and 5-bit, respectively. [ABSTRACT FROM AUTHOR]

The need of energy-efficient, high-speed, and low-offset analog-to-digital converters is forcing to design the dynamic latch comparators to enhance the speed and energy efficiency with minimum offset. This paper presents a novel double tail dynamic latch comparator using bulk-driven process and common-gate (CG) amplifier in amplification stage. The gain of amplification stage is enhanced using GACOBA load in which gain is controlled by bulk amplification through CG amplifier. It results in remarkable enhancement in regeneration speed and reduction in power consumption. The analytical expressions of delay and offset due to mismatch are also derived. These derivations explore the key contributors to reduce the delay and offset of proposed comparator. The outcomes are verified in CADENCE SPECTRE at 45-nm CMOS process technology through various simulations and Monte-Carlo analysis at different process corners. The post-layout analysis validates the simulation results. The proposed comparator is 93% more energy-efficient and lessens more than 84% delay in comparison of conventional design. The 1– σ input offset voltage and average input voltage error due to kickback noise are 2.48 mV and 0.824 μ V, respectively at 0.8 V power supply with 34.32 μ m2 active area. [ABSTRACT FROM AUTHOR]