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High-performance integrated tin monoxide bottom-gate staggered p-channel thin-film transistors (TFTs) are realized and reported. The active layer has been formed by thermal vacuum evaporation and rapid thermal annealing under a continuous nitrogen flow, resulting in field-effect mobilities up to 1.6 cm2/( $\textsf {V}\cdot \textsf {s}$ ) and contact resistances of around $148~\Omega \cdot \textsf {cm}$ . The integration of these TFTs in elementary building blocks for digital circuit applications such as inverters and ring-oscillators is demonstrated, resulting in stage delays down to 300 ns. Furthermore, a unipolar p-type-only 8-bit radio frequency identification code generator is realized, achieving 12.2 kb/s and comprising 294 tin monoxide TFTs.

In this study, we have compared the performance of self-aligned a-IGZO thin-film transistors (TFTs) whereby the source/drain (S/D) region's conductivity enhanced in three different ways, that is, using SiNx interlayer plasma (hydrogen diffusion), using calcium (Ca as reducing metal) and using argon plasma (changing the atomic ratio). All these TFTs show comparable characteristics such as field-effect mobility (μFE) of over 10.0 cm2/(V.s), sub-threshold slope (SS-1) of 0.5 V/decade, and current ratio (ION/IOFF) over 108. However, under negative-bias-illumination-stress (NBIS), all these TFTs showed strong degradation. We attributed this NBIS stability issue to the exposed S/D regions and changes in the conductivity of S/D contact regions. The hydrogen plasma-treated TFTs showed the worst NBIS characteristics. This is linked to increased hydrogen diffusion from the S/D contact regions to the channel. In this study, we observed that the negative-bias-illumination-stress stabilities of self-aligned a-IGZO thin-film transistors are strongly dependent upon the source/drain (S/D) region's direct exposure to stress light. Among few different techniques for S/D conductivity enhancements such as metal reduction (Ca metal), Ar plamsa, and SiNx plasma (hydrogen diffusion), the SiNx plasma-treated thin-film transistors showed the worst negative-bias-illumination-stress suitabilities. This is linked to increased hydrogen diffusion from the S/D contact regions to the channel. cop. 2015 Society for Information Display.

We present a QVGA (320x240 with 3 sub-pixel) top-emitting AMOLED display with 250ppi resolution using a self-aligned (SA) IGZO TFT backplane on polyimide-foil with full barrier. The back plane process flow is based on a 7 layer photolithography process. The aperture ratio of the top-emitting OLEDs is approx. 80%. An integrated gate driver is shown that can be driven at operation speed equivalent to a 4k2k display at 100Hz

In this work we present the impact of buffer layers deposited by various techniques such as plasma enhanced chemical deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD) techniques on self-aligned (SA) top gate amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) TFT characteristics. Finally an optimized layer was integrated in TFT backplane on polyimide (PI) foil and a QQVGA AMOLED display is demonstrated.

We demonstrated self-aligned amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistors (TFTs) where the source–drain (S/D) regions were made conductive via chemical reduction of the a-IGZO via metallic calcium (Ca). Due to the higher chemical reactivity of Ca, the process can be operated at lower temperatures. The Ca process has the additional benefit of the reaction byproduct calcium oxide being removable through a water rinse step, thus simplifying the device integration. The Ca-reduced a-IGZO showed a sheet resistance (RSHEET) value of 0.7 kΩ/sq., with molybdenum as the S/D metal. The corresponding a-IGZO TFTs exhibited good electrical properties, such as a field-effect mobility (μFE) of 12.0 cm2/(V s), a subthreshold slope (SS−1) of 0.4 V/decade, and an on/off current ratio (ION/OFF) above 108. Cop. 2015 The Korean Information Display Society.

In this work, we report on amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with medium frequency physical vapor deposited (mf-PVD) etch-stop-layer (ESL). TFT with mf-PVD ESL show comparable characteristics such as fieldeffect mobility (μFE), sub-threshold slope (SS−1) and current ratio (ION/OFF) to the conventional plasma enhanced chemical vapor deposition (PECVD) ESL based TFT, however significant differences were observed in gate bias-stress stabilities. The TFTs with mf-PVD ESL showed lower threshold-voltage (VTH) shifts compared to TFTs with PECVD ESL when stressed under a gate field of +/−1 MV/cm for duration of 104 seconds in dark and light conditions. We associate the better bias-stress stability of the mf-PVD ESL based TFT to better passivating properties and the low hydrogen content of the mf-PVD layer compared to PECVD layer.

A process to make self-aligned top-gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) on polyimide foil is presented. The source/drain (S/D) region's parasitic resistance reduced during the SiN interlayer deposition step. The sheet resistivity of S/D region after exposure to SiN interlayer deposition decreased to 1.5 kΩ/□. TFTs show field-effect mobility of 12.0 cm2/(V.s), sub-threshold slope of 0.5 V/decade, and current ratio (I ON/OFF) of >107. The threshold voltage shifts of the TFTs were 0.5 V in positive (+1.0 MV/cm) bias direction and 1.5 V in negative (-1.0 MV/cm) bias direction after extended stressing time of 104 s. We achieve a stage-delay of ~19.6 ns at V-DD = 20 V measured in a 41-stage ring oscillator. A top-emitting quarter-quarter-video-graphics-array active-matrix organic light-emitting diode display with 85 ppi (pixels per inch) resolution has been realized using only five lithographic mask steps. For operation at 6 V supply voltage (V-DD), the brightness of the display exceeds 150 cd/m2. A process to make self-aligned top-gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) is presented. TFTs show field-effect mobility of 12.0 cm2/(V.s), sub-threshold slope of 0.5 V/decade, and current ratio (I ON/OFF) of over 107. In applications, a 41-stage ring oscillator with a stage-delay of ~19.6 ns (at V-DD = 20 V) and a top-emitting quarter-quarter-video-graphics-array (QQVGA) active-matrix organic light-emitting diode (AMOLED) display with 85 ppi (pixels per inch) resolution using five lithographic mask steps have been realized on a polyimide foil. Copyright 2015 Society for Information Display.

In this work, we compared the thin-film transistor (TFT) characteristics of amorphous InGaZnO TFTs with six different source–drain (S/D) metals (MoCr, TiW, Ni, Mo, Al, and Ti/Au) fabricated in bottom-gate bottom-contact (BGBC) and bottom-gate top-contact (BGTC) configurations. In the BGTC configuration, nearly every metal can be injected nicely into the a-IGZO leading to nice TFT characteristics; however, in the BGBC configuration, only Ti/Au is injected nicely and shows comparable TFT characteristics. We attribute this to the metal-containing deposits in the channel and the contact oxidation during a-IGZO layer sputtering in the presence of S/D metal. In bias-stress stability, TFTs with Ti/Au S/D metal showed good results in both configurations; however, in the BGTC configuration, not all the TFTs showed as good bias results as Ti/Au S/D metal TFTs. We attribute this to backchannel interface change, which happened because of the metal-containing deposits at the backchannel during the final the SiO2 passivation.

We present a QQVGA (160times120 with 3 sub-pixel) top-emitting AMOLED display with 85ppi resolution using a self-aligned (SA) IGZO TFT backplane on polyimide-foil. The back plane process flow is based on a 5 layer photolithography process. The aperture ratio of the top-emitting OLEDs is approx. 25%. For operation at 6 V supply voltage (VDD), the brightness of the display exceeds 150cd/m2. On the same substrate a 160 stage gate-driver was measured at FHD rate. cop. 2014 Society for Information Display.

In this work, we report on high-performance bottom-gate top-contact (BGTC) amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with SiO2 as an etch-stop-layer (ESL) deposited by medium frequency physical vapor deposition (mf-PVD). The TFTs show field-effect mobility (μFE) of 16.0cm2/(V.s), sub-threshold slope (SS -1) of 0.23V/decade and off-currents (IOFF)

In this study, we report high-quality amorphous indiunrv-galiium-zinc-oxide (a-IGZO) thinfilm transistors (TFTs) fabricated on a polyethylene naphthalate foil using a new back-channel-etch (BCE) process flow. The BCE flow allows a better scalability of TFTs for high-resolution backplanes and related circuits. The maximum processing temperature was limited to less than loS'C in order to ensure good overiay accuracy (

In this study, the authors report high-quality amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) thin film transistors (TFTs) fabricated using a new back-channel-etch (BCE) process flow on Polyethylene Naphthalate (PEN) foil. The BCE flow allows a better scalability of TFTs for high-resolution backplanes and related circuits. The maximum processing temperature was limited to less than 165oC in order to ensure good overlay accuracy (< 1µm) on foil. The presented process flow differs from to previously reported by defining the Mo S/D contacts by dry etch prior to a-IGZO patterning. The TFTs show good electrical performance, including field-effect mobilities in the range of 15.0cm2/(V.s), sub-threshold slopes of 0.3V/decade and off-currents

In this study, the authors report on high-quality amorphous indium-galliunv-zinc oxide thinfilm transistors (TFTs) based on a single-source dual-layer concept processed at temperatures down to ISCC. The dual-layer concept allows the precise control of local charge carrier densities by varying the 02/Ar gas ratio during sputtering for the bottom and top layers. Therefore, extensive annealing steps after the deposition can be avoided. In addition, the dual-layer concept is more robust against variation of the oxygen flow in the deposition chamber. The charge carrier density in the TFT channel is namely adjusted by varying the thickness of the two layers whereby the oxygen concentration during deposition is switched only between no oxygen for the bottom layer and very high concentration for the top layer. The dual-layer TFTs are more stable under bias conditions in comparison with single-layer TFTs processed at low temperatures. Finally, the applicability of this dual-layer concept in logic circuitry such as 19-stage ring oscillators and a TFT backplane on polyethylene naphthalate foil containing a quarter video graphics array active-matrix organic lightemitting diode display demonstrator is proven.

We suggest an analytic theory based on the effective medium approximation (EMA) which is able to describe charge-carrier transport in a disordered semiconductor with a significant degree of degeneration realized at high carrier concentrations, especially relevant in some thin-film transistors (TFTs), when the Fermi level is very close to the conduction-band edge. The EMA model is based on special averaging of the Fermi-Dirac carrier distributions using a suitably normalized cumulative density-of-state distribution that includes both delocalized states and the localized states. The principal advantage of the present model is its ability to describe universally effective drift and Hall mobility in heterogeneous materials as a function of disorder, temperature, and carrier concentration within the same theoretical formalism. It also bridges a gap between hopping and bandlike transport in an energetically heterogeneous system. The key assumption of the model is that the charge carriers move through delocalized states and that, in addition to the tail of the localized states, the disorder can give rise to spatial energy variation of the transport-band edge being described by a Gaussian distribution. It can explain a puzzling observation of activated and carrier-concentration-dependent Hall mobility in a disordered system featuring an ideal Hall effect. The present model has been successfully applied to describe experimental results on the charge transport measured in an amorphous oxide semiconductor, In-Ga-Zn-O (a-IGZO). In particular, the model reproduces well both the conventional Meyer-Neldel (MN) compensation behavior for the charge-carrier mobility and inverse-MN effect for the conductivity observed in the same a-IGZO TFT. The model was further supported by ab initio calculations revealing that the amorphization of IGZO gives rise to variation of the conduction-band edge rather than to the creation of localized states. The obtained changes agree with the one we used to describe the charge transport. We found that the band-edge variation dominates the charge transport in high-quality a-IGZO TFTs in the above-threshold voltage region, whereas the localized states need not to be invoked to account for the experimental results in this material. ispartof: Physical Review B vol:93 issue:19 status: published

AMOLED backplanes were fabricated on both rigid glass and flexible plastic substrates using a solution processed oxide semiconductor processed at temperatures

It is shown in this paper that the finite resistance of the accumulation channel in amorphous In–Ga–Zn–O thin-film transistors (a-IGZO TFTs) is the main cause of the frequency dispersion of the capacitance–voltage curves in these devices. A transmission line model, accounting for the distributed nature of channel resistance, is used to explain this. Multi-frequency analysis techniques for trap density distribution use a lumped series resistance model and attribute dispersion solely to the charging and discharging of trap states. As the resistance–capacitance (RC) time constant values of the IGZO TFTs are in the range of 10–100 µs, a distributed RC network is better suited for the measured frequency range (1 kHz–1 MHz). cop. 2014 The Korean Information Display Society.

We validate a model which is a combination of multiple trapping and release and percolation model for describing the conduction mechanism in amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFT). We show that using just multiple trapping and release or percolation model is insufficient to explain TFT behavior as a function of temperature. We also show the intrinsic mobility is dependent on temperature due to scattering by ionic impurities or lattice. In solving the Poisson equation to find the surface potential and back potential as a function of gate voltage, we explicitly allow for the back surface to be floating, as is the case for a-IGZO transistors. The parameters for gap states, percolation barriers and intrinsic mobility at room temperature that we extract with this comprehensive model are in good agreement with those extracted in literature with partially-complete models.

We report on the impact of source/drain (S/D) metal (molybdenum) etch and the final passivation (SiO2) layer on the bias-stress stability of back-channel-etch (BCE) configuration based amorphous indium–gallium–zinc oxide (a-IGZO) thin-film transistors (TFTs). It is observed that the BCE configurations TFTs suffer poor bias-stability in comparison to etch-stop-layer (ESL) TFTs. By analysis with transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS), as well as by a comparative analysis of contacts formed by other metals, we infer that this poor bias-stability for BCE transistors having Mo S/D contacts is associated with contamination of the back channel interface, which occurs by Mo-containing deposits on the back channel during the final plasma process of the physical vapor deposited SiO2 passivation.