954 results on '"Groeseneken, Guido"'
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52. Reliability of strained-Si devices with post-oxide-deposition strain introduction
53. New developments in charge pumping measurements on thin stacked dielectrics
54. Stress-induced positive charge in Hf-based gate dielectrics: impact on device performance and a framework for the defect
55. On the correct extraction of interface trap density of MOS devices with high-mobility semiconductor substrates
56. Accurate gate impedance determination on ultraleaky MOSFETs by fitting to a three-lumped-parameter model at frequencies from DC to RF
57. Study of the reliability impact of chlorine precursor residues in thin atomic-layer-deposited Hf[O.sub.2] layers
58. High-[kappa] metal gate MOSFETs: Impact of extrinsic process condition on the gate-stack quality--A mobility study
59. Channel Hot Carriers and Other Reliability Mechanisms
60. Techniques and Devices
61. Conclusions and Perspectives
62. Negative Bias Temperature Instability in Nanoscale Devices
63. Introduction
64. Negative Bias Temperature Instability in (Si)Ge pMOSFETs
65. Degradation Mechanisms
66. Planar bulk MOSFETs versus FinFETs: An analog/RF perspective
67. MOSFET ESD breakdown modeling and parameter extraction in advanced CMOS technologies
68. Electrical characteristics of 8 Angstrom EOT Hf[O.sub.2]/TaN low thermal-budget n-channel FETs with solid-phase epitaxially regrown junctions
69. Comparative study of drain and gate low-frequency noise in nMOSFETs with hafnium-based gate dielectrics
70. GaN power ICs design using the MIT virtual source GaNFET compact model with GateLeakage and V T instability effect
71. Electronic voltage control of magnetic anisotropy at room temperature in high- κ SrTiO3/Co/Pt trilayer
72. Integration of 650 V GaN Power ICs on 200 mm Engineered Substrates
73. Hot hole degradation effects in lateral nDMOS transistors
74. Analytical percolation model for predicting anomalous charge loss in flash memories
75. Hole traps in silicon dioxides-part II: generation mechanism
76. Hot-carrier degradation phenomena in lateral and vertical DMOS transistors
77. A study of relaxation current in high-kappa dielectric stacks
78. Charge trapping and dielectric reliability of SiO[subscript 2]-Al[subscrip 2]O[subscript 3] gate stacks with TiN electrodes
79. LaSiO x - and Al 2 O 3 -Inserted Low-Temperature Gate-Stacks for Improved BTI Reliability in 3-D Sequential Integration.
80. Two types of neutral electron traps generated in the gate silicon dioxide
81. Impact of MOSFET gate oxide breakdown on digital circuit operation and reliability
82. Hole trapping and trap generation in the gate silicon oxide
83. Characterization of soft breakdown in thin oxide NMOSFETs based on the analysis of the substrate current
84. Photo-carrier generation as the origin of Fowler-Nordheim-induced substrate hole current in thin oxides
85. Spectroscopic identification of light emitted from defects in silicon devices
86. Signature of Ballistic Band-Tail Tunneling Current in Tunnel FET
87. RF/High-Speed I/O ESD Protection: Co-optimizing Strategy Between BEOL Capacitance and HBM Immunity in Advanced CMOS Process
88. The Influence of Gate Bias on the Anneal of Hot-Carrier Degradation
89. Observation of Dynamic V TH of p-GaN Gate HEMTs by Fast Sweeping Characterization
90. The influence of elevated temperature on degradation and lifetime prediction of thin silicon-dioxide films
91. Degradation of oxides and oxynitrides under hot hole stress
92. Interface Trap Characterization and Fermi Level Pinning in Si-Passivated Ge/HfO2 Capacitors
93. High-k Characterization by RFCV
94. Instability and Defects in Gate Dielectric: Similarity and Differences Between Hf-Stacks and SiO2
95. A Step Towards a Better Understanding of Silicon Passivated (100)Ge p-Channel Devices
96. Novel Device Concepts for Nanotechnology: The Nanowire Pinch-Off FET and Graphene TunnelFET
97. CARBonCHIP: Carbon Nanotubes Technology on Silicon Integrated Circuits; Some Key Results
98. Tunnel Field-Effect Transistors for Future Low-Power Nano-Electronics
99. Trends and Challenges in Si and Hetero-Junction Tunnel Field Effect Transistors
100. A physics-aware compact modeling framework for transistor aging in the entire bias space
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