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A unified drain current model of complementary (p- and n-type) organic thin film transistors (OTFTs) is presented. The model is physically based and takes into account the detailed properties of the organic semiconductor through the density of states (DOS). The drain current depends on the geometrical and physical parameters of the transistor, on the applied gate, drain and source voltages, and on the surface potential at the source and drain contacts. An analytical expression of the surface potential is derived. The proposed model is validated with the numerical calculations and the measurements of both p- and n-type OTFTs fabricated in a printed complementary technology. The provided analyses show that the model is continuous, accurate, and includes the main physical effects taking place in complementary organic transistors. Thanks to its analytical and symmetric formulation, it is suitable for the design of organic integrated circuits. Moreover, the unified physical picture provided by the model enables the extraction of the OTFTs physical parameters, thus it is a very powerful tool for the technology characterization.

A revolutionary approach to the technology design is required for the integration of the laser annealing process in nano-electronic device fabrication. The list of the integration issues includes: the patterning effect, the extreme non-equilibrium kinetics of dopant and defects, the material modification due to the melting-regrowth phenomena (in the melting regime) and the residual damage problem. The intense research effort required surely benefits from an adequate development of dedicated technology computer aided design tools. We present the computational apparatus needed for the simulation of the laser annealing process in Si-based devices. The tools aim at the simulation at a different resolution (from the atomic to the continuum level) of the phenomena occurring inside the specimen during the irradiation. The usage impact of such simulation tools on the process integration is conclusively crucial for a reliable device design and the final optimisation of fabricated MOS transistors.

In this work, we studied the effects of different thermal annealing on the electrical characteristics of non-self-aligned low-temperature p-channel polycrystalline silicon (polysilicon) thin film transistors. Different thermal treatments were performed after Al-gate formation at different temperature (200 degrees C, 250 degrees C, 350 degrees C and 450 degrees C) and annealing times. We found that optimal conditions were obtained at 350 degrees C, with transfer characteristics showing a subthreshold slope of 0.5 V/dec, field effect mobility > 100 cm(2)/Vs and threshold voltage around -3.5 V. Hot carrier induced degradation was also analyzed performing bias-stress measurements on devices annealed at 350 degrees C and at different bias stress conditions. The experimental data show that a maximum transconductance degradation is obtained for V,(stress) - V-t = -4 V while bias-stress at V-g = V-t and vertical bar V-g(stress)vertical bar >> vertical bar V-ds(stress)vertical bar did not produce appreciable changes in both transfer and output characteristics.

We analysed the electrical characteristics and the stability of gate overlapped lightly doped drain (GOLDD) thin-film transistors (TFTs) with different channel length, n- region doping concentration and lateral doping profile at the junctions. A reduction of kink effect and an increase of device stability have been observed with the increase of the lateral doping profile. These results are explained by numerical simulation of electrical characteristics and hot carrier induced degradation. We found that different doping profiles produce, after bias stress, different interface state distributions across the channel/n- and n-/n+ junctions.

Integration of excimer laser annealing (ELA) process for power MOSFET devices is currently studied and evaluated within the frame of the IST project FLASH (Fundamentals and applications of laser processing for highly innovative MOS technology), funded by the European Commission. Final goal of the project is to show that ELA can be industrialized in the context of semiconductor device fabrication. In this work, the recent advancements of the FLASH project are described, including the formation of n + /p source junctions in both one and two dimensions. The experimental results are analysed by using a two-dimensional simulation program, specifically developed by the consortium. The simulation tool allowed a deeper insight of the ELA process and has been successfully used to optimise the process parameters. Finally, data on electrical integrity of the test devices are also presented, showing a yield for optimum ELA conditions up to 84%.

Parasitic resistance effects have been investigated in n-channel polycrystalline (polysilicon) silicon thin film transistors (TFTs). We show, both experimentally, and by using two-dimensional numerical simulations, that the transfer characteristics and, in particular, the transconductance are degraded by parasitic resistance effects, which are related to residual implant damage. In particular, we show that residual implant damage gives rise to two types of defected regions across the edges of the gate: the first, not overlapped by the gate, which mainly controls the parasitic resistance. The second, which is gate overlapped, can affect the behavior of the threshold voltage by modifying the classical short channel effect to the reverse short channel effect. The analysis demonstrates that for the fabrication of short-channel polysilicon TFTs an exact control of the implant-damaged regions is necessary.

The influence of channel doping on the threshold voltage of poly-Si thin film transistors (TFTs) has been investigated using both boron and phosphorus implants. For each dopant type, asymmetric TFT behaviour was seen between enhancement and depletion mode TFTs, with the enhancement mode TFTs always showing a greater shift in threshold voltage for a given dose. From a detailed analysis of the boron-doped samples, using a two-dimensional device simulator, it was demonstrated that the results could be best explained in terms of a non-symmetric density of states, in which the deep trapping state density in the lower half of the band-gap increased with increasing boron concentration. This is the first reported observation in poly-Si of shallow level dopants also introducing deep levels in the majority carrier half band-gap.

In this work we present the electrical characterization of non self-aligned p-channel thin film transistors fabricated by using laser doping technique for source/drain contact formation and gate oxide deposited at room temperature by Electron Cyclotron Resonance Plasma Enhanced Chemical Vapour Deposition. These techniques are suitable for a very low temperature process for TFT fabrication. The output characteristics show a current increase at high drain voltage, (“kink” effect) rather moderate, if compared to self aligned polysilicon TFTs, probably due to the gradual doping profile induced by laser doping process. After bias stress at low gate voltage and high drain voltage condition a strong reduction of kink current has been observed in the output characteristics at high drain voltage, whereas minor changes has been observed in the transfer characteristics. This behaviour is similar to what observed in n-channel Gate Overlapped Thin Film Transistors. In the high gate voltage and high drain voltage bias-stress condition we observed only a rigid shift of the transfer characteristics probably related to charge injection in the gate oxide, while subthreshold slope remains constant.

Short channel effects have been investigated in n-channel polysilicon thin film transistors. Transconductance degradation has been observed when reducing the channel length L and this effect has been explained with the presence of a parasitic resistance related to residual implant damage. Threshold voltage slighlty decreases for channel length around L=1 μm and simulations confirm that the roll-off of the threshold voltage is expected for L

Silicon dioxide films have been deposited at temperatures less than 270 °C in an electron cyclotron resonance (ECR) plasma reactor from a gas phase combination of O2, SiH4 and He. The physical characterization of the material was carried out through pinhole density analysis as a function of substrate temperature for different μ-wave power (Ew). Higher Ew at room deposition temperature (RT) shows low defects densities ( 10 MV/cm are observed from ramps I–V. Moreover, from high frequency and quasi-static C–V characteristics we studied interface quality as function of annealing time and annealing temperature in N2. We found that even for low annealing temperature (200 °C) is possible to reduce considerably the interface state density down to 5 × 1011 cm−2 eV−1. These results show that a complete low-temperatures process can be achieved for the integration of SiO2 as gate insulator in polysilicon TFTs on plastic substrates.

Excimer laser annealing (ELA) of As-, B- and BF2-implanted Si has been studied by secondary ion mass spectrometry (SIMS), spreading resistance probe (SRP) and transmission electron microscopy (TEM). The implantations have been performed in the energy range from I to 30 keV with doses of 10(15)-10(16) cm(-2). ELA has been carried out with the energy densities in the range of 600-1200 mJ/cm(2) and the number of laser pulses from 1 to 10. It is shown that ELA results in a more uniform dopant distribution over the doped region with a more abrupt profile edge as compared to those after rapid thermal annealing (RTA). Besides, in contrast to RTA, ELA demonstrates a highly confined annealing effect, where the distribution of dopants below the melting region is not affected. SRP measurements demonstrate almost complete activation of the implanted dopants after ELA, and TEM does not reveal extended defects in the ELA-treated samples. The depth of the doped layers, abruptness of the profiles and the total doping dose as a function of ELA energy density and number of laser pulses are investigated. Computer simulations of ELA show a good agreement with the experimental data.

We report on the correlation between structural and electrical properties of pentacene thin film transistors fabricated by the novel supersonic molecular beam epitaxy (SuMBE) technique. We exploited the ability of SuMBE that, through the control on the molecular precursors in the beam, allows improving the quality in terms of structure and morphology of the semi-conducting thin films compared to the more standard OMBE growth. Different growth conditions were explored to find the better range of beam parameters improving the performance of the TFT device whereas the quality of the films grown was studied by atomic force microscopy. We show that the initial kinetic energy of the pentacene molecule strongly affects both the morphology of the films and the electrical properties of the devices that result to be strongly correlated. With our FET devices prepared, on SiO 2 /Si and top Au contact, we achieved the very promising field effect mobility larger than 0.5 cm 2 V −1 s −1 for films grown at room temperature at a pentacene kinetic energy of about 5.5 eV that are characterized by large crystalline grains (>2 μm).

We propose the implementation of graphene-based field effect transistor (FET) as radiation sensor. In the proposed detector, graphene obtained via chemical vapor deposition is integrated into a Si-based field effect device as the gate readout electrode, able to sense any change in the field distribution induced by ionization in the underneath absorber, because of the strong variation in the graphene conductivity close to the charge neutrality point. Different 2-dimensional layered materials can be envisaged in this kind of device.

Different drain field architectures have been recently investigated to reduce field-enhanced effects in conventional self-aligned polysilicon thin-film transistor (TFT) architecture, induced by the intense electric fields at the drain junction. Among these, gate overlapped lightly doped drain (GOLDD) architecture has been shown to be effective in reducing the drain field in both on and off states of the TFT, without introducing appreciable series resistance effects. In this paper, we investigate the electrical characteristics, both in the on- and in the off-regime, of GOLDD polysilicon TFTs, made with different LDD doses, by combining experimental data with two-dimensional (2-D) numerical analysis. We also demonstrate that both the on-state and off-state features of the GOLDD structure can be readily understood in terms of a simple, new model, based upon two TFTs series. This is consistent both with the experimental data and the results of full 2-D simulations. This paper not only clarifies the dependence of kink effect, leakage current, and series resistance upon the LDD-doping, but also provides the guidelines to optimize physical parameters of GOLDD TFTs.

The analysis of the grain size (GS) vs. energy density of silicon films irradiated with long pulse (LP) (150–200 ns) excimer laser has revealed that the maximum GS achievable is limited to 250–350 nm. In general, maximum GS occurs when the so-called super lateral growth (SLG) mechanism is triggered (almost complete melting) and in short-pulse (30 ns) irradiated films the maximum GS can be well above 1 μm. In order to clarify this discrepancy between the SLG regimes observed with short and LP irradiations, we performed an experiment with a LP (170 ns) excimer laser (HERCULES), having opportunely profiled the energy density to a ‘ramp’ distribution. In this way it was possible to have a continuous energy distribution and by analysing the structural (SEM) and topographical (AFM) properties it was possible to produce an accurate picture of their dependence upon the laser energy density. We were able to identify the SLG regime, with GS up to 1.5 μm and energy window Δ E / E =0.002, pointing out the difficulties in observing SLG in LP irradiations.

Structural properties of thin polycrystalline silicon films, crystallized by single shot excimer laser annealing at different laser energy densities, have been investigated. Formation of disk structures has been observed in a wide range of energy densities, from complete melting down to 180 mJ/cm 2 . These structures have been correlated to the lateral growth of grains starting from the small grains present in the central regions of the disks. We propose a new crystallization scenario for energy densities below the complete melting. In this framework, the recalescence effect plays an important role while the super lateral growth-regime is no longer a particular crystallization condition but simply represents the upper energy density limit of partial melt crystallization regime.

Grain size control in excimer laser crystallization has stimulated a growing activity aiming to locate large silicon grains in the thin-film transistor (TFT) channel. We present a new technique that can be applied to control the lateral growth (LG), by using thickness spatial modulation, and that can be used to the fabrication of high performance polysilicon TFTs. In particular LG can be triggered when thinner regions are completely melted and thicker regions are partially melted. Thicker regions are formed by a two layer structure of doped and undoped material while thinner regions are obtained by removing the doped layer. In this way the thicker regions can be used as source–drain regions of the device while the thinner regions, where large grains are formed, can be used as channel regions. In order to control the LG, different doped and undoped layer thickness have been investigated. The structures have been irradiated at different laser energy densities and we observed that the thicker regions became highly conductive (∼70 Ω/□), due to doping activation and redistribution induced by the melt/regrowth process, while triggering of the LG in the thinner region has been observed within an opportune energy density window. As the LG extension is limited at approximately 1 μm, active channel region ⩽2 μm could be formed. The proposed process is very attractive for polysilicon TFTs as LG-control and doping activation can be simultaneously achieved.

Hot-carrier induced degradation is a main issue in the electrical stability of polysilicon TFTs and drain field relief architectures have been introduced, such as lightly doped drain (LDD) and gate overlapped LDD (GOLDD), to improve the stability. Bias-stress experiments were performed on both LDD and GOLDD structures, biasing the devices above pinch-off at constant V g and different V ds . While the LDD structure presented considerable hot-carrier induced degradation, GOLDD devices were characterised by a very high electrical stability. To explain such a difference in electrical stability, we first analysed the spatial distributions of the electric fields, which are lower in GOLDD structures. In addition, we developed a new model to describe the hot-carrier induced degradation, based on the correlation between hot carrier injection currents and interface state generation. Indeed, hot carrier injection is known to produce interface states and oxide trapped charge, and, depending upon their spatial distribution, can strongly influence the local electric fields as well as the current. The proposed model nicely reproduces the degraded characteristics, thus providing indications on the spatial distribution of the generated interface states.

A novel fabrication process for low-temperature (

In this work we investigate the electromechanical behavior of a flexible piezoelectric sensor, based on Polyvinylidene-fluoride-trifluoroethylene (PVDF-TrFE) capacitor fabricated on ultra-thin polyimide film (5 µm thick). The piezocapacitor has been integrated with a high mobility p-channel organic thin film transistor, made on polyethylene naphthalate (PEN, 125 µm thick), by adopting a multi-foil approach. An extensive study of the effects of the electrical and mechanical stress on the device components has been reported in order to evaluate the sensor's reliability in a real environment. Then the sensor was tested, at different working frequencies and applied forces with the intent of mimicking the human sense of touch. We believe that this device can represent a key element for a high performing electronic skin system to be deployed on humanoid robot.

In this work, the design of a high-frequency AM demodulator in a printed complementary organic technology is presented. The behaviour and the variability of printed circuits are predicted by means of accurate transistor modelling, statistical characterization, and Monte Carlo simulations. The effectiveness of the design approach is readily verified by comparing measurements and simulations of simple digital blocks as well as two differential amplifiers. These amplifiers can be used as continuous-time comparators in the demodulator. In addition, the possibility of high-frequency rectification using the printed organic TFTs is shown by providing the experimental results of an envelope detector measured under different load and input conditions. All the measurements are performed in air. Finally, the simulation of a complete AM demodulator system including the measured blocks is demonstrated. © 2014 Elsevier B.V. All rights reserved.

Low-frequency noise has been investigated in self-aligned (SA) and gate overlapped lightly doped drain (GOLDD) polysilicon thin-film transistors (TFTs). We found that, at low Vds, both device structures are characterised by 1/f noise, originating from carrier number fluctuations. However, when the SA devices were operated in the kink regime, an excess noise was observed, in contrast to GOLDD TFTs. This has been explained by attributing the excess noise to supplemental oxide charge fluctuations induced by hot-carrier injection into the gate oxide. By using two-dimensional numerical simulations, we show that the hot-electron emission current in SA polysilicon TFTs is much higher than in the GOLDD structure.

Self-heating-related instabilities have been studied in p-channel polycrystalline-silicon thin-film transistors. The spatial distribution of the interface-state and fixed-oxide-charge densities generated during self-heating experiments has been analyzed and quantitatively determined by using negative-bias temperature stress experiments and 2-D numerical simulations. In addition, the observed asymmetry in the output characteristics with respect to source/drain contact reversal is also perfectly reproduced, confirming the validity of the proposed model.

The introduction of excimer laser crystallization (ELC) techniques in the fabrication of polysilicon thin-film transistors (TFTs) has produced a tremendous improvement in the device characteristics. When the Super Lateral Growth (SLG) mechanism is triggered, large (>1 μm) grains are formed and this crystallization regime appears very attractive from the device fabrication point of view. In fact, using SLG-polysilicon active layers high performance (electron field-effect mobility>300 cm 2 /V s) TFTs can be obtained and a detailed analysis of the electrical characteristics of such devices is presented. However, the SLG mechanism has a very narrow energy density window and, consequently, highly uniform beam profiles and pulse-to-pulse stability better than 2% are required. This implies that standard ELC-process is technologically quite critical and several approaches have been proposed to improve the process uniformity. Among these we will discuss three main techniques: (1) the use of opportunely (semi-gaussian) profiled beams; (2) the combined use of Solid Phase Crystallization (SPC) and ELC techniques; (3) control of the lateral growth. In particular, we present a novel technique to control the lateral growth, based on a two-pass ELC-process. The proposed technique can be rather attractive for polysilicon TFT fabrication, allowing a precise grain location control (through the mask geometry) and being characterized by a few (3–5) laser shots process and wide energy density windows.

Hot-carrier effects on both the electrical characteristics and the noise performance in polycrystalline silicon thin film transistors are analysed. The devices were fabricated by using a combined solid phase crystallization (SPC) and excimer laser annealing (ELA) process, combining the beneficial aspects of the two techniques. Hot-carrier degradation results in the formation of both interface states, which have been evaluated through the analysis of the sheet conductance and of oxide traps near the insulator/semiconductor interface, as evidenced by the 1/f noise measurements. Oxide traps are calculated evaluating the flat band voltage spectral density associated with interface charge fluctuations in the damaged part of the interface. A strong correlation between interface state and oxide trap densities has been found, suggesting a common origin for the generation mechanism of the two types of defects.

Polysilicon thin-film transistors (TFTs) are of great interest for their circuit application in the large area microelectronics. A successful circuit design requires an accurate prediction of the circuit performances, which in turn needs a proper modeling of the electrical device characteristics. In this present work the specific aspects of the anomalous current increase in the output characteristics, often called the “kink” effect, are analysed. A new procedure to determine the excess current is presented and we analysed the excess current for different gate voltages, temperatures and device geometries. We show that, from the parameters that can be extracted by analysing a reduced set of experimental data, the excess current can be easily predicted for any bias and temperature condition and also for devices with different geometries. These results can be used to further up-grade the modeling of the electrical characteristics of polysilicon TFTs in circuit simulators.

Organic Thin film Transistors (OTFT) have been widely investigated in these last years as potential candidate for the development of low cost, flexible and lightweight active- matrix backplanes for display applications. Indeed the organic semiconductors provide both promising electrical performances tunable by chemistry and the ability to be processed at low temperature with innovative printing technics on various large scale substrates. Thanks to the recent developments on both n-type and p-type solution-processed organic

The effects of the laser irradiation on metal-oxide-semiconductor structures are investigated by means of a phase-field methodology. We numerically solved the model equations in one- and two-dimensional structures also containing SiO2/amorphous-Si/crystalline-Si stacks. The simulated laser annealing processes are discussed in detail, pointing out the influence of the geometrical constraints on the irradiation effects in the samples. The simulation results are compared with the experimental two-dimensional delineation of dopant profiles. These comparisons show the importance of the joint theoretical and experimental investigations in order to fully understand the phenomena occurring in submicron sized laser irradiated structures.

Many functional properties of organic semiconductors, such as charge transport, are regulated by structural order. The control of crystallinity, orientation, and positioning of crystals—the highest form of order—inside devices presents an extraordinary opportunity to fully exploit their potentialities. On page 2387, M. Cavallini and co-workers demonstrate direct patterning of crystals of conjugated molecules onto devices, with defined shape and controlled size

Low-frequency noise in polycrystalline silicon (polysilicon) thin-film transistors (TFTs), made using the sequential lateral solidification (SLS) technique, has been investigated. Two types of devices have been analyzed: SLS polysilicon TFTs, where the noise is dominated by the carrier number fluctuations, and extended grain polysilicon TFTs, where an excess noise was present for low drain currents. The noise induced by carrier number fluctuations was seen to scale, in both types of devices, with the inverse of the channel area, as expected from the theory. The excess noise was explained considering the mobility fluctuations induced by the scattering with low angle grain boundaries present in the extended grain polysilicon.

Contact effects have been analyzed in fully printed p-channel OTFTs based on a pentacene derivative as organic semiconductor and with Au source-drain contacts. In these devices, contact effects lead to an apparent decrease of the field effect mobility with decreasing L and to a failure of the gradual channel approximation (GCA) in reproducing the output characteristics. Experimental data have been reproduced by two-dimensional numerical simulations that included a Schottky barrier (Phi(b) = 0.46 eV) at both source and drain contacts and the effects of field-induced barrier lowering. The barrier lowering was found to be controlled by the Schottky effect for an electric field E < 10(5) V/cm, while for higher electric fields we found a stronger barrier lowering presumably due to other field-enhanced mechanisms. The analysis of numerical simulation results showed that three different operating regimes of the device can be identified: (1) low vertical bar V-ds vertical bar, where the channel and the Schottky diodes at both source and drain behave as gate voltage dependent resistors and the partition between channel resistance and contact resistance depends upon the gate bias; (2) intermediate V-ds, where the device characteristics are dominated by the reverse biased diode at the source contact, and (3) high vertical bar V-ds vertical bar, where pinch-off of the channel occurs at the drain end and the transistor takes control of the current. We show that these three regimes are a general feature of the device characteristics when Schottky source and drain contacts are present, and therefore the same analysis could be extended to TFTs with different semiconductor active layers.

In this work we present a flexible pyroelectric capacitive sensor, based on PVDF-TrFE, fabricated on a ultra-thin polyimide film (8 μm thick) connected to a fully printed p-channel organic thin film transistor that is used to amplify the sensor signal. We fabricate a standalone device, exploiting a multi-foil approach, where the pyroelectric capacitor was glued on the organic TFT substrate, that consists of a PEN foil 125 μm thick, previously made in CEA-LITEN labs. The pyroelectric properties of the PVDF-TrFE capacitor were enhanced using a thermal poling procedure before the TFT integration. The sensor behavior was analyzed at different working frequencies (up to 500 Hz) under a specific infrared (IR) radiation provided by a He-Ne laser, with a wavelength of 632 nm and maximum power of 5 mW. An output signal of few millivolts was observed, exploiting the pre-amplification of the fully printed organic transistor.

Electrical characteristics of fully self-aligned gate overlapped lightly doped drain (FSA-GOLDD) polysilicon thin-film transistors (TFTs), fabricated with a spacer technology and providing submicron (0.35 μm) LDD regions, have been analyzed. Device characteristics show negligible series resistance of the LDD region while effective drain field relief has been demonstrated by a reduced kink effect and off-current, if compared to conventional self-aligned (SA) devices. Short channel effects are also mitigated by the LDD region, while substantial reduction in the hot-carrier induced instability is found, when compared with conventional SA devices. Optimum doping dose of the LDD region has been identified to be 9 × 1012 cm2.

The electrical properties of untreated and hydrogen-irradiated GaAs${}_{1\ensuremath{-}x}$N${}_{x}$ are investigated by conductive-probe atomic force microscopy (CP-AFM). After hydrogen irradiation, the resistance R of GaAs${}_{1\ensuremath{-}x}$N${}_{x}$ increases by more than three orders of magnitude while that of a N-free GaAs reference slightly decreases. Thermal annealing at 550 \ifmmode^\circ\else\textdegree\fi{}C of H-irradiated GaAs${}_{1\ensuremath{-}x}$N${}_{x}$ restores the pristine electrical properties of the as-grown sample thus demonstrating that this phenomenon is fully reversible. These effects are attributed to the nitrogen-hydrogen complexes that passivate N in GaAs${}_{1\ensuremath{-}x}$N${}_{x}$ (thus restoring the energy gap of N-free GaAs) and, moreover, reduce the carrier scattering time by more than one order of magnitude. This opens up a route to the fabrication of planar conductive/resistive/conductive heterostructures with submicrometer spatial resolution, which is also reported here.

Applications of polycrystalline silicon (polysilicon) thin film transistors (TFTs) to active matrix organic light emitting displays require further performance improvement. The biggest leverage in circuit performance can be obtained by reducing channel length from the typical current values of 3-6?m to 1?m, or less. However, short channel effects and hot-carrier induced instability in scaled down conventional self-aligned polysilicon TFTs can substantially degrade the device characteristics. To reduce these effects and allow proper operation of the circuits, drain field relief architectures have to be introduced. In this work we show that a fully self-aligned gate overlapped lightly doped drain (LDD) structure, with submicron LDD regions, can provide an excellent solution, allowing effective short channel effect control and improved electrical stability. ©The Electrochemical Society.

Self-heating-related instabilities have been investigated in p-channel polycrystalline-silicon thin-fllm transistor, showing an anomalous transconductance (gm) increase. The gm increase is a fingerprint of edge effects, resulting from a buildup of positive trapped charge in the gate oxide at the channel edges. This was confirmed by the annihilation of such positive charges obtained by sequential hot-carrier bias-stress experiments. From the analysis of the edge effects in devices with different channel lengths, we were able, using 2-D numerical simulations, to deter mine the size of the defected edge regions to be 400 nm.

Different amounts of single wall carbon nanotubes (SWCNTs) have been sprayed on amorphous silicon substrates to form Schottky barrier solar cells. The measured external quantum efficiency showed a spectral behavior depending on the SWCNT network optical transparency, presenting a maximum up to 35% at a wavelength of about 460 nm. Ultrathin network of SWCNTs acts as semitransparent electrode and forms Schottky barrier with amorphous silicon, enabling new generation low cost amorphous silicon based solar cells. Numerical simulations show a poor efficiency of SWCNT contacts in collecting holes suggesting that improvement in contact quality is needed to further improve solar cell efficiency.

Carrier quantum confinement has been achieved in dilute nitrides by controlling the peculiar kinetics of hydrogen in those materials. ${\text{GaAs}}_{1\ensuremath{-}x}{\text{N}}_{x}/{\text{GaAs}}_{1\ensuremath{-}x}{\text{N}}_{x}:\text{H}$ planar heterostructures have been fabricated by deposition of submicrometer titanium wires (width $w=485$, 175, and 80 nm) on ${\text{GaAs}}_{1\ensuremath{-}x}{\text{N}}_{x}$ and subsequent H irradiation. Continuous-wave photoluminescence, PL, in ensembles of ${\text{GaAs}}_{1\ensuremath{-}x}{\text{N}}_{x}/{\text{GaAs}}_{1\ensuremath{-}x}{\text{N}}_{x}:\text{H}$ heterostructures shows a blueshift of the PL peak energy and a marked increase in the PL radiative efficiency with decreasing one of the wire dimensions down to the nanometer-scale length. Concomitantly, time-resolved microphotoluminescence in single structures exhibits a pronounced slow down of carrier relaxation toward the ground state. All these results, supported by numerical calculations of H diffusion profiles, indicate that carrier quantum confinement can be achieved by H engineering of dilute nitrides.

High densities of self-catalyzed Si nanowires have been grown at temperatures down to 320 degrees C on different Si substrates, whose surfaces have been roughened by simple physical or chemical treatments. The particular substrates are Si(110) cleavage planes, chemically etched Si(111) surfaces and microcrystalline Si obtained by laser annealing thin amorphous Si layers. The NW morphology depends on the growth surface. Transmission electron microscopy indicates that the NWs are made of pure Si with a crystalline core structure. Reflectivity measurements confirm this latter finding.

Junctions shallower than 100 nm, obtained by ion implantation and excimer laser annealing, have been characterized in two dimensions by transmission electron microscopy (TEM) on chemically treated samples. The chemical treatment selectively removes silicon as a function of the B concentration, making thinner the regions where B is present in the cross section of the sample, with respect to the n-type substrate. Both secondary ion mass spectrometry and spreading resistance profiling measurements have been performed, in order to quantify the contour line obtained by TEM in terms of B concentration. The results achieved by the two-dimensional technique show interesting features, related to the particular redistribution of B occurring when silicon is melted by excimer laser annealing irradiation. In particular, a rectangular shape of the doped region obtained by laser annealing could be evidenced, caused by the fast diffusion in the melted material, completely different from the typical half-moon-shaped, ther...

Dilute nitrides alloys, as GaAsxN1−x, have been extensively studied in the last few years since the presence of small amounts of N in III–V semiconductors leads to major changes in the physical properties of the host materials. In particular, the strong reduction of band gap induced by N enables important technological applications in the field of active optical devices and microelectronics.

We present the design and fabrication of a chemoresistive sensor array for the volatile organic compounds and gas detection. Different nanofibrous conductive polymers, produced by electrospinning technique, have been used as chemical interactive materials. Sensor array was integrated with read-out electronic circuits on flexible substrate. In order to obtain high electrical performances maintaining integration capability, on plastic materials, respect to standard c-Si CMOS technology, polycrystalline silicon thin film transistor based circuitry has been used. The performances of the fabricated sensor array have been tested with different concentrations of Methanol, Lactic acid and Ammonia.

The expansion of the GaAsN lattice following hydrogen incorporation is spatially patterned so as to generate an anisotropic stress in the sample growth plane. The resulting in-plane symmetry breaking determines an in-plane polarization dependence of the light emitted along the crystal growth direction in agreement with optical selection rules and strain field calculations.

Hydrogenated amorphous silicon thin-film transistors have been fabricated by using electron-beam lithography to define channel length down to 0.2 μm. In this way it has been possible to evidence, for the first time, short-channel effects on these devices. In this work two short-channel effects occurring in 0.2 μm devices are discussed: degradation of the off-current as the source-drain voltage is increased and avalanche increase of the drain current for high source-drain voltage.

Negative bias stress experiments on a-Si:H/a-SiO 2 Thin Film Transistors show that the instability is predominantly related to charge injection in the gate insulator. We propose that charge injection is occurring in a defected region of the gate insulator adjacent to a-Si:H, caused by the effect of activated hydrogen on a-SiO 2 surface during deposition. To investigate the hydrogen influence, we have studied low-energy (100 eV) hydrogen-ion and Ar-ion bombardment effects on a-SiO 2 using synchrotron radiation photoemission spectroscopies. Comparing the two kind of treatments, we show that hydrogen treatment produces predominantly Si-H defects, which are observed to induce gap states in a-SiO 2 .

In this work the application of a-Si:H thin film transistor (TFT) technology in the field of chemical sensors is presented. In particular, two different types of devices have been fabricated: a) Pd-gate hydrogen sensors; b) K+-ion sensitive FET (ISFET). The obtained results show that a-Si:H TFT can be successfully used as gassensitive and ion-sensitive sensors and can represent a promising technology in this area.

The transfer characteristics of polysilicon thin film transistors have been measured in the temperature range from 400 to 80 K. The active layer has been made by excimer laser crystallization of amorphous silicon. The devices show high field-effect mobility values (>200 cm2/V s), even at low temperature. The electrical characteristics have been analyzed using a uniformly distributed density of states (DOS) model. The DOS has been derived using the values of the conductance at various temperatures. Using the DOS derived from the “temperature method,” we have calculated the transfer characteristics and the threshold voltage versus temperature, obtaining a very good agreement with experimental data.

In this paper we present the design and fabrication of two flexible sensor devices: humidity sensor and ammonia sensor integrated with electronic circuit interface on thin flexible substrate (8 mum). The transducers layout has been optimized by means of numerical simulations. A thin layer of Bisbenzocyclobytene (BCB) is used as dielectric sensitive material in humidity sensor. Conversely a mixed polymer layer based on polyaniline emeraldine base (PANi-EB) is used as sensing conductive polymer for ammonia.