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This article demonstrates all-digital tuning and dynamic control of feedback compensator in digital low drop out regulators to enhance the transient performance under process and passive variations, aging, and load changes. The measured results from a 130-nm CMOS test-chip shows 2.1× improvement in transient performance under process variations and 30% improvement for aging-induced degradations. We demonstrate 55-ns setting time for a 5 to 45 mA load step in 100 ps, with 97.8% peak current efficiency. [ABSTRACT FROM AUTHOR]

System-in-package (SiP) integration of multiple dies in a single package can achieve much higher performance than onboard integration of integrated circuits (ICs) while reducing the design cost/effort compared to a large system on chips (SoCs). However, a major challenge in the design of SiPs with many dies is automated design and insertion of input/output (I/O) cells to minimize energy and delay of the wire traces. This article presents an automated cell library generation flow for all-digital I/O circuits for SiP integration. Given parameterized models of SiP wire traces, our method automatically designs, optimizes, and generates layouts of I/O cells for delay/energy minimization. The proposed flow is demonstrated on interposer-based SiP integration considering 28-nm CMOS technology and 65-nm BEOL technology. Given a multidie SiP design and associated interposer wire traces, this article demonstrates that automated I/O library cell generation can reduce the maximum die-to-die communication delay or energy. We demonstrate the proposed flow for various interposer parameters and SiP designs to show the feasibility of chip-interposer codesign. [ABSTRACT FROM AUTHOR]

Neural networks generally require significant memory capacity/bandwidth to store/access a large number of synaptic weights. This paper presents design of an energy-efficient neural network inference engine based on adaptive weight compression using a JPEG image encoding algorithm. To maximize compression ratio with minimum accuracy loss, the quality factor of the JPEG encoder is adaptively controlled depending on the accuracy impact of each block. With 1% accuracy loss, the proposed approach achieves $63.4{\times }$ compression for multilayer perceptron (MLP) and $31.3 {\times }$ for LeNet-5 with the MNIST dataset, and $15.3 {\times }$ for AlexNet and $10.2 {\times }$ for ResNet-50 with ImageNet. The reduced memory requirement leads to higher throughput and lower energy for neural network inference ($3 {\times }$ effective memory bandwidth and $22 {\times }$ lower system energy for MLP). [ABSTRACT FROM AUTHOR]

This paper presents, DeepTrain, an embedded platform for high-performance and energy-efficient training of deep neural network (DNN). The key architectural concept of DeepTrain is to develop a spatially homogeneous computing (and memory) fabric with temporally heterogeneous programmable data flows to optimize memory mapping and data reuse during different phases of training operation.The DeepTrain is demonstrated as an in-memory accelerator integrated in the logic layer of a 3-D memory module. A programming model and supporting architecture utilizes the flexible data flow to efficiently accelerate training of various types of DNNs. The cycle level simulation and synthesized design in 15 nm FinFET shows power efficiency of 500 GFLOPS/W, and almost similar throughput for a wide range of DNNs, including convolutional, recurrent, and mixed (CNN+RNN) networks. [ABSTRACT FROM AUTHOR]

This paper presents design, experimental characterization, and feasibility analysis of integrated in-package fluidic cooling for mobile systems-on-chips (SoCs). A pin fin interposer for fluidic cooling is designed and integrated with a commercial SoC. The demonstrated system integrates an active low-power piezoelectric pump controlled by the SoC itself and a metal/acrylic-based board-scale heat spreader and exchanger. Different software-based policies in the SoC for controlling the fluid flow based on SoC’s temperature and performance are implemented and compared. The measurement results demonstrate that the in-package fluidic cooling improves the SoC’s energy efficiency and reduces design footprint compared to external passive cooling. [ABSTRACT FROM AUTHOR]

This paper experimentally demonstrates a methodology for proactive estimation of spatiotemporal variations in junction temperature of a silicon chip using multi-input multi-output (MIMO) thermal filters. The presented approach performs on-chip measurements to estimate the relations between power and temperature variations in the frequency domain to construct a MIMO thermal filter. The extracted filter is then used to predict spatiotemporal temperature variations from a known power pattern, even for locations without temperature sensors. The accuracy of the proposed approach is verified through a thermal emulator designed in 130-nm CMOS technology with on-chip digitally controllable power (heat) generators and temperature sensors. Using the proposed MIMO thermal filter, spatiotemporal temperature variations are accurately estimated with small error bound even at locations with no temperature sensors. [ABSTRACT FROM PUBLISHER]

Deposition of a metal gate on high- \kappa dielectric {\rm HfO}_{2} is known to generate oxygen vacancy (OVs) defects. Positively charged OVs in the dielectric affect the gate electrostatics and modulate the effective gate workfunction (WF). Count and spatial allocation of OVs varies from device-to-device and induces significant local variability in WF and V_{th}$ . This paper presents the statistical models to simulate OV concentration and placement depending on the gate formation conditions. OV-induced variability is studied for SOI FinFET, and compared against the other sources of variability across the technologies. The implications of gate first and gate last processes to the OV concentration/distribution are studied. Simulations show that with channel length and gate dielectric thickness scaling, the OV-induced variability becomes a significant concern. [ABSTRACT FROM PUBLISHER]

Thermal system identification (TSI) is presented as a methodology to characterize and estimate the transient thermal field of a packaged IC for various workloads considering chip-to-chip variations in electrical and thermal properties. The time–frequency duality is used to identify the thermal system as a low-pass filter in frequency domain through on-line power/thermal measurements on a packaged IC. The identified characteristic system for an individual IC is used for on-line prediction of the transient thermal field of that specific IC for a power pattern. A test-chip, fabricated in 130-nm CMOS, demonstrates the effectiveness of TSI in post-silicon characterization and prediction of transient thermal field. The application TSI in thermal analysis of multicore processors is presented. [ABSTRACT FROM PUBLISHER]

In this paper, we analyze the variability in a 3-D clock network designed with single and multiple through-silicon vias and present a post-silicon tuning methodology, called tier adaptive body biasing (TABB), to reduce skew and data path variability in 3-D clock trees. TABB uses specialized on-die sensors to independently detect the process corners of n-channel metal–oxide–semiconductor (nMOS) and p-channel metal–oxide–semiconductor (pMOS) devices and accordingly tune the body biases of nMOS/pMOS devices to reduce the clock skew variability. We also present the system architecture of TABB and circuit techniques for the on-die sensors. Circuit-level simulation and statistical analysis of the TABB architecture in a predictive 45-nm technology demonstrate the effectiveness of TABB in reducing the clock skew variability considering the data path variability in 3-D ICs. [ABSTRACT FROM AUTHOR]

This paper analyzes the effect of tier-to-tier thermal and supply crosstalk on the performance and robustness of the static random access memory (SRAM) within a 3-D stack under crosstalk influence of the logic cores. Our framework integrates distributed process variation aware circuit analysis, RC-based thermal simulation, and distributed RLC-based power delivery network simulation. The analysis shows when the logic cores and SRAMs are integrated in 3-D stack, the thermal and supply crosstalk degrade the SRAM performance and noise margin during read and write operations. [ABSTRACT FROM AUTHOR]

3-D technologies with stacked chips have the potential to provide new chip architecture, and improved device density, performance, efficiency, and bandwidth. The increased power density in 3-D technologies can become a daunting challenge for heat removal. Furthermore, power density can be highly nonuniform, leading to time- and space-varying hotspots, which can severely affect performance and reliability of integrated circuits. It is important to mitigate on-chip thermal gradients while considering the associated cooling costs. One efficient method of hotspot thermal management is to use superlattice thermoelectric coolers (TECs), which can provide on demand and localized cooling. In this paper, a detailed 3-D thermal model of a stacked electronic package with two dies and four ultrathin integrated TECs is developed to investigate the efficacy of TECs in hotspot cooling for 3-D technology. A strong vertical coupling has been observed between TECs located in top and bottom dies. Bottom TECs can significantly heat the top hotspots in both steady-state and transient operation. TECs need to be carefully placed inside the package to avoid such undesired heating. Thermal contact resistances between dies, inside the TEC module, and between TEC and heat spreader are shown to have a crucial effect on the TEC performance. We observe up to 5.6^\circC of active hotspot cooling in steady state and 7.4^\circC of active hotspot cooling using a square root current pulse. [ABSTRACT FROM PUBLISHER]

This paper presents the effect of proactive spatiotemporal power multiplexing on the thermal field in many-core processors. Power multiplexing migrates the locations of active cores within a chip after each fixed time interval, referred to as the migration interval, to redistribute the generated heat and thereby reduce the peak temperature and spatial and temporal nonuniformity in the thermal field. Clock and supply gating is used to minimize the power of the deactivated cores. The control of the migration interval is studied considering a 256-core processor at the predictive 16-nm node to evaluate the conflicting impact of the migration interval on thermal field and system performance. [ABSTRACT FROM PUBLISHER]

This paper estimates the temperature distribution within a spin-torque-transfer RAM (STTRAM) cell due to self-heating using a thermal simulation based on the finite volume method. The analysis shows that, due to high switching current and small volume of the magnetic tunnel junction (MTJ), there can be significant rise in temperature in the MTJ as well as the silicon transistor. The impacts of the increased temperature on operational reliability metrics of the STTRAM cell, i.e., read disturb, write failure, and sensing accuracy, are evaluated. It is shown that, due to the self-heating effect, the operational reliability of an STTRAM cell depends on the read–write history of that cell. [ABSTRACT FROM AUTHOR]

In this paper, we present a methodology for characterization and repair of signal degradation in through-silicon-vias (TSVs) in 3-D integrated circuits (ICs). The proposed structure can detect the signal degradation through TSVs due to resistive shorts in liner oxide and variations in resistance of TSV due to weak open and/or bonding resistance. For TSVs with moderate signal degradations, the proposed structure reconfigures itself as signal recovery circuit to maintain signal fidelity. This allows electrical repair of TSVs with moderate defects leading to better design yield and system functionality. This paper presents the design of the test and recovery structure and demonstrates their effectiveness through stand alone simulations as well as in a full-chip physical design of a 3-D IC. [ABSTRACT FROM PUBLISHER]

In this paper, we analyze the effect of clock slew in subthreshold circuits. Specifically, we address the issue that variations in clock slew at the register control can cause serious timing violations. We show that clock slew variations can cause frequency targets to deviate by as much as 28% from the design goals. Based on these observations, we recognize the importance of clock slew control in subthreshold circuits. We propose a systematic approach to design the clock tree for subthreshold circuits to reduce the clock slew variations while minimizing the energy dissipation in the tree. The combined approach, including the wire sizing and dynamic nodal capacitance control, can achieve better slew control (and better timing control) at lower energy in subthreshold circuits. [ABSTRACT FROM PUBLISHER]

• A new deep learning architecture that integrates spiking neural network (SNN) for contextual information extraction is proposed. • The proposed design shows improved robustness for both random and structured input perturbation during inference. • SNN is implemented with a novel frequency-dependent stochastic spike-timing-dependent-plasticity learning rule. Spiking neural network (SNN) is a type of artificial neural network that uses biologically inspired neuron models and learning rules to develop artificial intelligence with capability parallel to human brain. Deep neural networks (DNNs), on the other hand, uses less biologically plausible neurons and training methods such as gradient descent, and has shown good accuracy in computer vision tasks. However, human brain can still outperform DNN in certain scenarios. For example, DNN experiences significant performance degradation when perturbation from various sources is present in the input, which makes DNN less reliable for systems interacting with physical world. In this paper, we present a hybrid deep net work architecture with s pike-assisted c ontextual i nformation e xtraction (ScieNet) as a solution to the problem. ScieNet integrates a front-end SNN with a novel stochastic spike-timing-dependent plasticity (STDP) algorithm that extracts visual context from images. The back-end DNN is trained for classification given the contextual information. The integrated network demonstrates high resilience to input perturbations without relying on pre-training on perturbed inputs. We demonstrate ScieNet with various back-end DNNs for image classification using different datasets and considering both stochastic and structured input perturbations. Experimental results demonstrate significant improvement in accuracy on perturbed images, while maintaining state-of-the-art accuracy on clean images. [ABSTRACT FROM AUTHOR]

Dual-threshold-voltage (VT) CMOS is an effective way to reduce leakage power in high-performance very-large-scale-integration circuits. In this paper, we explore the technology design space for dual-threshold-voltage transistor design in deep-sub-100-nm technology nodes. We propose a technique of achieving high-VT (HVT) devices using thicker gate-sidewall offset spacers to increase the channel length without increasing the printed-gate length. The effectiveness of all the dual-VT technology options--increasing channel doping, increasing gate length, and proposed technique of increasing spacer thickness--is analyzed at transistor and basic logic gate level. Results on 65-nm partially depleted silicon-on-insulator and double-gate technologies indicate that the proposed technique yields lower dynamic power consumption and lower performance penalty compared with longer gate length and high body-doping devices. Our proposed technique, however, incurs extra fabrication mask similar to achieving HVT by increasing body doping. [ABSTRACT FROM AUTHOR]

Percutaneous transcatheter closure of ruptured sinus of valsalva aneurysm was attempted in eight patients between January 1995 and March 2003 as an alternative strategy to surgery as this technique at present is an accepted therapeutic modality for various intracardiac defects. The age range was 14–35 years, all were male, seven in symptomatic class III and one in class IV on medical treatment. Two-dimensional and color Doppler echocardiography revealed rupture of an aneurysm of right coronary sinus into right ventricle in five and noncoronary sinus into right atrium in three and none had associated ventricular septal defect. The echo estimated size of the defect was 7–12 mm. On cardiac catheterization left ventricular end-diastolic pressure ranged from 20 to 40 mmHg and the calculated Qp/Qs ratio was 2–3.5. In all patients the defect was crossed retrogradely from the aortic side and over an arterio-venous wire loop after balloon sizing, devices were successfully deployed by antegrade venous approach (Rashkind umbrella device in two and Amplatzer occluders in six, which included Amplatzer duct occluder in five and Amplatzer septal occluder in one). One patient who had residual shunt developed hemolysis on the next day and was taken up for reintervention. That patient continued to have intermittent hemolysis and was sent for surgical repair. On follow-up (2–96 months), there was no device embolization, infective endocarditis, and aortic regurgitation. One patient died of progressive congestive heart failure while other six are asymptomatic. These data highlight that transcatheter closure is feasible and effective, especially safe with the available Amplatzer devices. Definitely, it has the advantage of obviating open heart surgery but complete occlusion is mandatory to prevent hemolysis and infective endocarditis. (J Interven Cardiol 2004;17:53–58) [ABSTRACT FROM AUTHOR]

Deep Neural Network (DNN) systems tend to produce overconfident or uncalibrated outputs. This poses problems for active sensor systems that have a DNN module as the main feedback controller. In this paper, we study a closed-loop feedback smart camera from the lens of uncertainty estimation. The uncertainty of the task output is used to characterize and facilitate the feedback operation. The DNN uncertainty in the feedback system is estimated and characterized using both sampling and non-sampling based methods. In addition, we propose a closed-loop control that incorporates uncertainty information when providing feedback. We show two modes of control, one that prioritizes false positives and one that prioritizes false negatives, and a hybrid approach combining the two. We apply the uncertainty-driven control to the tasks of object detection, object tracking, and action detection. The hybrid system improves object detection and tracking accuracy on the CAMEL dataset by 1.1% each respectively. For the action detection task, the hybrid approach improves accuracy by 1.4%. [ABSTRACT FROM AUTHOR]