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Abstract: Both n-channel and p-channel metal-oxide-semiconductor (MOS) transistors were fabricated by using CeO x /La2O3 stacked gate dielectric film and tungsten metal electrode. X-ray photoelectron spectroscopy (XPS) measurements indicated that the as-deposited CeO2 was reduced to CeO x (a mixture of CeO2 and Ce2O3 phases) and the released oxygen atoms filled up the oxygen vacancies in the La2O3 film and thus improved the electrical characteristics of the transistors. We found that the amount of the dielectric defects in this structure were very low as evidenced by the recorded small threshold voltages for both types of transistors. The transistors also have excellent subthreshold characteristics and hot-carrier robustness. The subthreshold slopes were 72 and 73 mV/dec for n-channel and p-channel transistors with effective gate length of 1.8 μm, respectively, and remain fairly unchanged upon prolonged hot-carrier stressing. [Copyright &y& Elsevier]

Abstract: The effect of a thin Si layer insertion at W/La2O3 interface on the electrical characteristics of MOS capacitors and transistors is investigated. A suppression in the EOT increase can be obtained with Si insertion, indicating the inhibition of diffusion of oxygen atoms into La2O3 layer by forming an amorphous La-silicate layer at the W/La2O3 interface. In addition, positive shifts in V fb and V th caused by Si insertion implies the formation of amorphous La-silicate layer at the top of La2O3 dielectrics reduces the positive fixed charges induced by the metal electrode. Consequently, a large improvement in mobility has been confirmed for both at peak value and at high E eff of 1MV/cm with Si inserted nFETs. Although a degradation trend on EOT scaling has been observed, the insertion of thin Si layer is effective in pushing the scaling limit. [Copyright &y& Elsevier]

Abstract: The effect of La2O3 incorporation on the spatial trap distribution in HfO2 gate dielectrics is investigated. The incorporation of La2O3 in HfO2 dielectric has been found to improve the effective mobility in addition to reduced interface-state density. The trap distribution analysis in the HfO2 layer extracted by combining the charge pumping (CP) method and the low-frequency noise (LFN) method has revealed significant reduction in the amount of traps at HfO2/SiO2-interlayer interface and in the HfO2 layer by La2O3 incorporation. [Copyright &y& Elsevier]

Abstract: We experimentally examine the effective mobility in nMOSFETs with La2O3 gate dielectrics without SiO x -based interfacial layer. The reduced mobility is mainly caused by fixed charges in High-k gate dielectrics and the contribution of the interface state density is approximately 30% at N s =5×1011 cm−2 in the low 1011 cm−2 eV−1 order. It is considered that one of the effective methods for improving mobility is to utilize La-silicate layer formed by high temperature annealing. However, there essentially exists trade-off relationship between high temperature annealing and small EOT. [Copyright &y& Elsevier]

Highlights: [•] We observed different temperature dependences of the leakage current in CeO2/La2O3 stack. [•] The CeO2 capping layer resulted in the barrier lowering at La2O3/Si interface. [•] Poole–Frankel conduction dominating the leakage current with a barrier height of 0.119eV. [•] The oxygen atoms from the CeO2 layer also affected the current conduction at higher voltages. [Copyright &y& Elsevier]

Highlights: [•] AR-HPES is useful to the chemical bonding states and depth profiles of MOS structure. [•] We measure the effect of Si-cap layer and PDA on the compositional depth profiles. [•] We measure the effect of Si-cap layer and PDA on the chemical bonding states. [•] The La2O3 interlayer can suppress the oxide formation at high-κ/InGaAs during PMA. [ABSTRACT FROM AUTHOR]

Abstract: It is shown in this work that the presence of an ultrathin (~1.5nm) SiO2 interfacial layer reactively formed in between a thick (~20nm) high-permittivity CeOx film and a metal NiSi2 bottom electrode in a metal–insulator–metal structure has remarkable consequences for the hysteretic current–voltage (I–V) characteristic of the device. Conductance values in the low resistance state (LRS) close to integer and half-integer values of the quantum conductance unit G 0 =2e 2 / h, where e is the electron charge and h the Planck constant, reveal the formation of filamentary structures across the stack with bottlenecks of atomic dimensions. Even though the hysteretic behavior partially remains when the bottom electrode (Ti, TiN, or W) is changed, the LRS I–V no longer exhibits so well defined conductance levels as in the NiSi2 case. This distinctive behavior is attributed to the presence of the SiO2 switching layer. Supplementary post-breakdown I–V data obtained from Al/SiO2/Si capacitors supports this hypothesis. [Copyright &y& Elsevier]

Abstract: Effect of W and TiN/W gate metal on the interface quality of La2O3/InGaAs metal–oxide-semiconductor (MOS) interface is investigated. Hard X-ray photoelectron spectroscopy revealed that gate metal greatly affects the oxidation states at La2O3/InGaAs interface after post-metallization annealing (PMA). Results demonstrate that TiN/W gate metal can effectively control the reaction at La2O3/InGaAs interface and also suppress the formation of As, Ga, and In oxides. As a result, superior capacitance–voltage (C–V) characteristics with low interface state density (D it) of 4.6×1011 cm−2/eV (∼0.1eV from midgap) and leakage current below 10−5 A/cm2 was obtained for TiN/W/La2O3 (10nm)/InGaAs MOS capacitors. The MOS structure integrity was preserved for annealing temperature up to 620°C. [Copyright &y& Elsevier]

Abstract: A novel interpretation for conductance spectra obtained by conductance method of La2O3 gated MOS capacitors has been proposed. Two distinct peaks, one with broad spectrum ranging from 10k to 200kHz and the other near 1kHz with a single time constant spectrum, have been observed at depletion condition. The former spectrum can be assigned as the interface traps (Dit ) located at the interface between La-silicate and the Si substrate by statistical surface potential fluctuation model. On the other hand, as the latter slow trap signal shows strong influence with the thickness of La-silicate layer, it can be assigned as the trappings (Dslow ) at the interface between La2O3 and La-silicate. Finally, the Dit and Dslow trends on annealing temperature are summarized. [Copyright &y& Elsevier]

Abstract: Oxygen incorporation for compensation of oxygen defects is investigated with La-silicate dielectrics in directly contacted with the Si substrate. The amount of oxygen is controlled by the temperature of annealing in oxygen atmosphere (oxygen annealing) and the thickness of the gate electrode. The positive shift in flatband voltage (V FB) by oxygen incorporation is an experimental evidence for defects compensation in La-silicate dielectrics. Optimum oxygen annealing provides the V FB shift toward positive direction without increasing equivalent oxide thickness (EOT). Although the oxygen annealing degrades the interfacial property at La-silicate/Si interface, subsequent forming gas annealing (FGA) can recover the interfacial property. It is experimentally revealed that the positive V FB shift of La-silicate dielectrics is stable even after subsequent FGA. The supplied oxygen in La-silicate is expected to maintain even after reducing process. Movement of Fermi level toward the Si valence band edge caused by oxygen incorporation is successfully observed by XPS. Moreover, no chemical reaction between La-silicate and Si substrate by oxygen annealing are confirmed from TEM observation and analyses of X-ray photoelectron spectra. It is experimentally demonstrated that effective hole mobility can be improved without increase in EOT by combination of oxygen annealing and FGA. [Copyright &y& Elsevier]

Abstract: In this work, the effect of nitrogen implantation on thin La2O3 films grown by e-beam evaporation are investigated using x-ray photoelectron spectroscopy (XPS), current–voltage (I–V) and capacitance–voltage (C–V) measurements. The amount of nitrogen incorporation in the oxide film by plasma immersion ion-implantation (PIII) is found to be quite low (about 3% near the surface). However, introduction of nitrogen atoms into La2O3 network results in a significant reduction in the oxide traps and leads to a notable improvement in both material and electrical properties of the dielectric. [Copyright &y& Elsevier]

Abstract: This study reports the electrical characteristics of La-Sc oxides complex and effect of nitrogen incorporation for applications to high-k gate stack. We found that Vfb can be controlled by the ScO concentration. Moreover, large bumps in C-V curves, which indicate high interfacial state density, can be suppressed with large ScO concentration. nMOSFETs using the La-Sc oxides complex in the gate stack are fabricated. In addition, nitrogen incorporation into the La-Sc oxide films was fond to be useful to suppress the EOT growth during annealing at high temperatures. [Copyright &y& Elsevier]

Abstract: By measuring the current–voltage and capacitance–voltage characteristics of thin La2O3 film at several different temperatures ranging from 100 to 400K and after constant-voltage stressing at different durations, we reveal the existence of a shallow electron trap with energy of about 0.19eV below the conduction band edge of La2O3. This kind of trap is involved in the thermal-assisted Poole–Frenkel tunneling through the dielectric layer. Significant charge trapping and detrapping are found in samples annealed in nitrogen at 400°C. The charge trapping–detrapping events are attributed to the oxygen vacancies with activation energy of 0.332eV, which is assigned to the relaxation between the charging states of the O-vacancies. The trapping characteristics of samples annealed at 600°C are greatly improved as a consequence of O-vacancy removal and formation of interfacial silicon oxide layer. [Copyright &y& Elsevier]

Abstract: This work reports the effects of low-temperature post-deposition annealing (PDA) and post-metallization annealing (PMA) on the electrical properties of ultrathin (with EOT ranging from 1.29 nm to 2.33 nm) La2O3 gate dielectric films. We found that positive charges were generated during the PDA as evidenced by the negative flat-band voltage (V FB ) shift. Forming of La-silicate interface layer and a reduction in the channel mobility are found for the PDA samples at temperature higher than 300°C. Better electrical characteristics were achieved by the PMA. The PMA sample has a peak channel mobility of 319 cm2 /Vs. [Copyright &y& Elsevier]

The current conduction behaviors in CeO2/La2O3 stack are studied. We found that large amount of hole injection under large negative gate bias can give rise to the accumulation of neutral interstitial oxygen (OI) species which serve as acceptors and promotes the hole conduction in the La2O3 film. Whereas if the amount of hole injection is lower than that of the oxygen anions injected from the capping CeO2 layer under a sufficient large negative gate bias, the amount of OI reduces and a negative charge built-up results which further reduces the leakage current and threshold voltage of p-channel metal-oxide-semiconductor transistors. [ABSTRACT FROM AUTHOR]

The presence of grain boundaries (GBs) in polycrystalline high-κ (HK) gate dielectric materials affects the electrical performance and reliability of advanced HK based metal-oxide-semiconductor devices. It is important to study the role of GB in stress-induced-leakage current (SILC) degradation and time-dependent dielectric breakdown of polycrystalline HK gate stacks. In this work, we present nanoscale localized electrical study and uniform stressing analysis comparing the electrical conduction properties at grain and GB locations for blanket cerium oxide (CeO2)-based HK thin films using scanning tunneling microscopy. The results clearly reveal higher SILC degradation rate at GB sites and their vulnerability to early percolation, supporting the phenomenon of GB-assisted HK gate dielectric degradation and breakdown. [ABSTRACT FROM AUTHOR]

The effects of lanthanum incorporation into HfO2 dielectrics were studied using first-principles total energy calculations. The author’s computational result clearly showed that the formation energy of a neutral oxygen vacancy (VO0) in the vicinity of substitutional La atoms at Hf sites is 0.7 eV larger than that in pure HfO2, indicating that the concentration of VO0’s is drastically reduced by La incorporation. This effect is understood to be caused by the decrease in the local dielectric constant κL around La atoms due to the strong ionic character of the La–O bond compared to the Hf–O bond. [ABSTRACT FROM AUTHOR]

The electron transport in W/CeOx/SiO2/NiSi2 resistive switching devices fabricated onto a p+-type Si substrate is investigated. It is shown that the structures exhibit bipolar switching with conductance values in the low resistance state (LRS) close to integer and half integer values of the quantum unit G0 = 2e2/h, e and h being the electron charge and Planck constant, respectively. This behavior is consistent with the so-called nonlinear conduction regime in quantum point-contacts. A simple model for the LRS current-voltage characteristic based on the finite-bias Landauer formula which accounts for the right- and left-going conduction modes dictated by the constriction's cross-section area and the voltage drop distribution along the filamentary path is reported. [ABSTRACT FROM AUTHOR]

This work reports, for the first time, the phenomenon of lateral Poole-Frenkel current conduction along the dielectric/Si interface of a silicon nanowire metal-oxide semiconductor (MOS) transistor. This discovery has a great impact on the study of device characteristic modeling and device reliability, leading to a new kind of electronic device with a distinct operation mechanism for replacing the existing MOS transistor structure. By measuring the current-voltage characteristics of silicon nanowire MOS transistors with different nanowire widths and at elevated temperatures up to 450 K, we found that the current level in the conventional ohmic region of MOS transistors, especially for the transistors with a nanowire width of 10 nm, was significantly enhanced and the characteristics are no longer linear or in an ohmic relationship. The enhancement strongly depended on the applied drain voltage and strictly followed the Poole-Frenkel emission characteristics. Based on this discovery, we proposed a new type of MOS device: a Poole-Frenkel emission MOS transistor, or PF-MOS. The PF-MOS uses the high defect state Si/dielectric interface layer as the conduction channel and is expected to possess several unique features that have never been reported. PF-MOS could be considered as the ultimate MOS structure from a technological point of view. In particular, it eliminates the requirement of a subnanometer gate dielectric equivalent oxide thickness (EOT) and eradicates the server mobility degradation issue in the sub-decananometer nanowires.

Layered materials, such as graphene and transition metal dichalcogenides, are able to obtain new properties and functions through the modification of their crystal arrangements. In particular, ferromagnetism in polycrystalline MoS 2 is of great interest because the corresponding nonmagnetic single crystals exhibit spontaneous spin splitting only through the formation of grain boundaries. However, no one has reported direct evidence of this unique phenomenon thus far. Herein, we demonstrate ferromagnetism modulation by an ultralow current density < 10 3 A/cm 2 in 7.5-nm-thick polycrystalline MoS 2 , in which magnetoresistance shows three patterns according to the current intensity: wide dip, nondip and narrow dip structures. Since magnetoresistance occurs because of the interaction between the current of 4d electrons in the bulk and localized 4d spins in grain boundaries, this result provides evidence of the current modulation of ferromagnetism induced by grain boundaries. Our findings pave the way for the investigation of a novel method of magnetization switching with low power consumption for magnetic random access memories., (© 2022. The Author(s).)

This work performs a detailed comparison of the channel width folding effectiveness of the FinFET, vertically stacked nanosheet transistor (VNSFET), and vertically stacked nanowire transistor (VNWFET) under the constraints of the same vertical (fin) height and layout footprint size (fin width) defined by the same lithography and dry etching capabilities of a foundry. The results show that the nanosheet structure has advantages only when the intersheet spacing or vertical sheet pitch is less than the sheet width. Additionally, for the nanowire transistors, the wire spacing should be less than 57% of the wire diameter in order to have a folding ratio better than a FinFET with the same total height and footprint. Considering the technological constraints for the gate oxide and metal gate thicknesses, the minimum intersheet/interwire spacing should be in the range of 7 to 8 nm. Then, the VNSFET structure has the advantage of boosting the chip density over the FinFET ones only when the sheet width is wider than 8 nm. On the other hand, the VNWFET structure may have a better footprint sizing than the FinFET ones only when the nanowire diameter is larger than 14 nm. In addition, considering the different channel mobilities along the different surface directions of the silicon channel and also some other unfavorable natures such as more complicated processes, more significant surface roughness scattering, and parasitic capacitance effects, the nanosheet transistor does not show superior scaling capability than the FinFET counterpart when approaching the ultimate technology node.

As CMOS devices are scaled down to a nanoscale range, characteristic variability has become a critical issue for yield and performance control of gigascale integrated circuit manufacturing. Nanoscale in size, few monolayers thick, and less thermally stable high-k interfaces all together cause more significant surface roughness-induced local electric field fluctuation and thus leads to a large device characteristic variability. This paper presents a comprehensive study and detailed discussion on the gate leakage variabilities of nanoscale devices corresponding to the surface roughness effects. By taking the W/La 2 O 3 /Si structure as an example, capacitance and leakage current variabilities were found to increase pronouncedly for samples even with a very low-temperature thermal annealing at 300 °C. These results can be explained consistently with the increase in surface roughness as a result of local oxidation at the La 2 O 3 /Si interface and the interface reactions at the W/La 2 O 3 interface. The surface roughness effects are expected to be severe in future generations' devices with even thinner gate dielectric film and smaller size of the devices.

The atomic scale characterization of dopant atoms in semiconductor devices to establish correlations with the electrical activation of these atoms is essential to the advancement of contemporary semiconductor process technology. Spectro-photoelectron holography combined with first-principles simulations can determine the local three-dimensional atomic structures of dopant elements, which in turn affect their electronic states. In the work reported herein, this technique was used to examine arsenic (As) atoms doped into a silicon (Si) crystal. As 3d core level photoelectron spectroscopy demonstrated the presence of three types of As atoms at a total concentration of approximately 10 20 cm -3 , denoted as BEH, BEM, and BEL. On the basis of Hall effect measurements, the BEH atoms corresponded to electrically active As occupying substitutional sites and exhibiting larger thermal fluctuations than the Si atoms, while the BEM atoms corresponded to electrically inactive As embedded in the As n V (n = 2-4) type clusters. Finally, the BEL atoms were assigned to electrically inactive As in locally disordered structures.

When pushing the gate dielectric thickness of metal-oxide-semiconductor (MOS) devices down to the subnanometer scale, the most challenging issue is the interface. The interfacial transition layers between the high-k dielectric/Si and between the high-k dielectric/gate metal become the critical constraints for the smallest achievable film thickness. This work presents a detailed study on the interface bonding structures of the tungsten/lanthanum oxide/silicon (W/La2O3/Si) MOS structure. We found that both W/La2O3 and La2O3/Si are thermally unstable. Thermal annealing can lead to W oxidation and the forming of a complex oxide layer at the W/La2O3 interface. For the La2O3/Si interface, thermal annealing leads to a thick low-k silicate layer. These interface layers do not only cause significant device performance degradation, but also impose a limit on the thinnest equivalent oxide thickness (EOT) to be achievable which may be well above the requirements of our future technology nodes.

Low-temperature photoluminescence (PL) spectra of electron-hole systems in Si nanowires (NWs) prepared by thermal oxidization of Si fin structures were studied. Mapping of PL reveals that NWs with uniform width are formed over a large area. Annealing temperature dependence of PL peak intensities was maximized at 400 °C for each NW type, which are consistent with previous reports. Our results confirmed that the micro-PL demonstrated here is one of the important methods for characterizations of the interface defects in Si NWs.

Dislocation is a lattice imperfection of crystalline materials. Dislocation movement is induced during plastic deformation and influences the mechanical properties. Although the role of dislocation in mechanical properties has been well understood, the role of dislocation in electrical properties is completely lacking. Only Matthiessen's rule addresses the electrical influence of dislocations at the macroscale. Here, we show that the electrical conductance change due to dislocations and show their movements through in situ observation of a gold nanocontact. The density of the dislocations in the gold nanocontact did not affect the electrical conductance. The repeated and discrete dislocation movements resulted in an electrical conductance oscillation. Our results demonstrate how dislocations and their movements affect electric conductance at the nanoscale. This instability issue will cause a big problem for future electric devices such as ultra low power electric devices and nanowire photovoltaic devices.