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International audience; 3D-IC test becomes a challenge with the increasing number of TSVs and demands for effective 3D aware test techniques. In this work, we propose a timing aware model to capture delay variations on a path due to resistive open TSVs. The key idea is to analytically model delay and apply our correlation-based resistive open TSV detection method to attain path delay fault coverage. We propose two methods to investigate timing variation introduced by resistive open TSVs in a critical path delay with multiple TSVs. Method I computes the correlation of multiple TSVs in a path to overall path delay to determine if TSVs are the source of the introduced delay. Method II pinpoints which TSV is faulty by computing the delay fault coverage of each TSV in a path with multiple TSVs. Our results indicate the accuracy of our proposed method and promotes early identification of resistive open defects TSVs.

International audience; CMOS technology trends at one side open up some opportunities like making small and power efficient devices available, which in turn allow to put more functionality into a single chip. However, on the other side it poses some challenges like making devices vulnerable to hard and soft errors. In this paper we propose an efficient fault-tolerant architecture able to deal with permanent and transient faults in combinational parts of pipeline structures. The principle consists in triplicating the combinational logic parts but, unlike TMR, only two copies are running in parallel while the third one remains in standby until an error is detected. We implement this approach on a MIPS microprocessor as case study to make it resilient against transient and permanent faults.

International audience; Through-Silicon-Vias (TSVs) are the key enablers of 3D integration technology. Therefore, the reliability of 3D-ICs rely on the quality of TSV testing. TSVs are prone to defects that may introduce small delay variations that can cause quality and reliability issues. Moreover, physical and electrical conditions, such as TSV dimensions, coupling and IR-drop, may affect path delay variations and consequently affect the detectability of small delay faults (SDF) induced by defective TSVs. In this work, we study the test quality and pattern effectiveness for SDF induced by TSVs. We quantity test quality using statistical delay quality level (SDQL) metric and test patterns are generated with commercial ATPG tools.

International audience; This paper is in the field of Analog or RF integrated circuit testing. The conventional practice for testing those circuits relies on the measurement of the device-under-test (DUT) specifications. In order to reduce test costs, a promising approach, called indirect or alternate testing has been proposed. Its basic principle consists in using the correlation between the conventional analog/RF performances and some low-cost measurements, called Indirect Measurements (IMs), in order to estimate the analog/RF parameters without measuring directly them. The objective of this paper is to perform a comparative analysis of different IM selection strategies in order to define efficient alternate testing implementation. Efficiency is discussed in terms of model accuracy and predictions robustness. Results are illustrated on a Power Amplifier (PA) test vehicle for which we have experimental test data on 10,000 circuits.

International audience; Abstract The greedy specification testing remains mandatory for analog and radio frequency (RF) integrated circuits because of the accuracy of the sorting based on these measurements. Unfortunately, to be implemented, this kind of testing method often incurs very high costs (expensive instruments, long test time…). A common approach, in the literature, is the so-called indirect/alternate test strategy. This strategy consists in deriving targeted specifications from low-cost Indirect Measurements (IMs). During the industrial test phase, the estimation of regular specifications using \IMs\ is based on a correlation model that has been built previously, during a training phase. Despite the substantial test cost reduction offered by this strategy, its deployment in industry is limited, mainly because of a lack of confidence in the accuracy of estimations made by the correlation model. A solution to increase the confidence in the estimation of specifications using the indirect approach is to implement redundancy in the prediction phase. In this paper, we demonstrate that the redundancy implementation brings more than identifying rare misjudged circuits from a high-correlated model. Indeed redundancy massively increases the accuracy despite of the lack of accurate models that have been assumed in previous implementations of redundant indirect testing. This approach is illustrated on a real case study for which we have experimental measurements on a set of 10,000 devices.

International audience; CERN hosts a large number of electronic devices and equipment, functioning over its different particle accelerators. In certain areas, they operate in harsh radiation environments. In order to assure their proper functionality, the equipment or some of their sensitive components undergo several tests in experimental test areas representative of the LHC radiation fields, while specialized monitors constantly record the respective radiation levels. The purpose of this study is to evaluate the use of monitors using recent technology nodes (90 nm) in order to have a better estimation of the expected error rate of the devices. The H4IRRAD experimental test area has been specifically designed to reproduce the radiation field that is present within the LHC tunnel and shielded areas. It has been used to test our custom SRAM based monitors. The monitors have been exposed to a maximum dose and high energy hadron fluence of about 76 Gy and 1.3 × 1011 cm-2 respectively. The results show that the total ionizing dose (TID) effect does not impact the bit cross section of our devices. Moreover the Single Event occurrence is coherent to the beam intensity fluctuations, proving that these devices are appropriate for SEU monitoring under mixed particle fields.

International audience; In this paper, different strategies for post-silicon yield improvement of MEMS convective accelerometers are explored. A key feature of the proposed strategies is that they can be implemented at low-cost using electrical test equipment since they only rely on the measurement of the relative deviation of Wheatstone bridge impedance due to power dissipation in the heating element. Different electrical test flows are defined that implement either sensitivity binning, sensitivity calibration, or both. Optionally, an additional constraint can be inserted in the test flows in case power consumption performance has also to be satisfied in addition to sensitivity. The efficiency of the different strategies is evaluated and discussed considering a population of 1,000 devices generated through Monte-Carlo simulation. Finally, experimental measurements that validate the calibration principle are presented.

International audience; In order to improve performance and reduce cost, multi-processor system on chip (MPSoC) is increasingly becoming attractive. At the same time, 3D integration emerges as a promising technology for high density integration. 3D homogeneous MPSoCs combine the benefits of both. However, high current demand and large on-chip switching activity variations introduce severe power supply noises (PSN) for 3D MPSoCs, which can increase critical path delay, and degrade chip performance and reliability. Meanwhile, thermal gradient should also be considered for 3D MPSoCs to avoid hot spots. In the paper, we investigate the PSN effects of different workloads and propose an effective PSN estimation method. Then, a heuristic workload assignment algorithm is proposed to suppress PSN under the given thermal constraint. The experimental results show that PSNs can be reduced significantly compared with thermal-balanced workload assignment scheme, and the system performance can be improved as well.

International audience; Design of power delivery network (PDN) is a constrained optimization problem. An ideal PDN must limit voltage drop that results from switching circuits' transients, satisfy current density constraints that arise from electromigration limits, yet use only minimal metal resources so that design density targets can be met. It should also provide an efficient thermal conduit to address heat flux. Furthermore, an ideal PDN should be a regular structure to facilitate design productivity and manufacturability, yet be resilient to address varying power demands across its distribution area. In 3-D ICs, these problems are further constrained by the need to minimize through-silicon via (TSV) area and bridge power lines of different dimensions across tiers, while addressing varying power demands in lateral and vertical directions. In this paper, we propose an unconventional power grid optimization solution that allows us to resize each tier individually by applying tier-specific constraints and yet be optimal in a multitier network, where each tier is locally resized while globally constrained. Tier-specific constraints are derived from electrical and thermal targets of 3-D PDNs. Two resizing algorithms are presented that optimize 3-D PDNs standalone or 3-D PDNs together with TSVs. We demonstrate these solutions on a three-tier setup where significant area savings can be achieved.

International audience; Magnetic random access memory (MRAM) is an emerging technology with potential to become the universal on-chip memory. Among existing MRAM technologies, thermally assisted switching (TAS)-MRAM technology offers several advantages compared with other technologies: selectivity, single magnetic field, and high-integration density. In this paper, we analyze the impact of resistive-open defects on TAS-MRAM behavior. Electrical simulations were performed on a hypothetical 16 word TAS-MRAM architecture enabling any combination of read and write operations. Results show that read and write sequences may be affected by resistive-open defects that may induce single and double-cell faulty behaviors. As a next step, we will exploit the analyses results to guide the test phase by providing effective test algorithms targeting faults related to actual defects affecting TAS-MRAM architectures.

International audience; This paper discusses new implementations of the predictive alternate test strategy that exploit model redundancy in order to improve test confidence. The key idea is to build during the training phase, not only one regression model for each specification as in the classical implementation, but several regression models. This redundancy is then used during the testing phase to identify suspect predictions and remove the corresponding devices from the alternate test flow. In this paper, we explore various options for implementing model redundancy, based on the use of different indirect measurement combinations and/or different partitions of the training set. The proposed implementations are evaluated on a real case study for which we have production test data from 10,000 devices.

International audience; Bulk Built-In Current Sensors (BBICSs) are able to detect anomalous transient currents induced in the bulk of integrated circuits when hit by ionizing particles. This paper presents a new strategy to design BBICSs with optimal transient-fault detection sensitivity while keeping low both area and power overheads. The approach allows increasing the detection sensitivity by setting an asymmetry in the flipping ability of the sensor's latch. In addition, we introduce a mechanism to tune the delay of the bulk access transistors that improves even more the BBICS detection sensitivity. The proposed design strategy offers a good compromise between fault detection sensitivity and power consumption; moreover it makes feasible the use of several CMOS processes.

International audience; This work proposes a novel built-in current sensor for detecting transient faults of short and long duration as well as multiple faults in combinational and sequential logic. Unlike prior similar strategies, which are formed by pairs of PMOS and NMOS sensors, the proposed scheme is a single sensor connected to PMOS and NMOS bulks of the monitored logic. In comparison with existing transient-fault mitigation techniques, the paper presents very competitive results that indicate no performance penalty, and overheads of only 26 % in power consumption and 23 % in area.

This paper presents a digital embedded test instrument (ETI) for on-chip phase noise (PN) testing of analog/RF integrated circuits. The technique relies on 1–bit signal acquisition and dedicated processing to compute a digital signature related to the PN level. An appropriate algorithm based on on-the-fly processing of the 1-bit signal is defined in order to implement the BIST module with minimal hardware resources. Its implementation in CMOS 140[Formula: see text]nm technology occupies only 7,885[Formula: see text][Formula: see text]m2, which represents an extremely small silicon area. Hardware measurements are performed on an FPGA prototype that validates the proposed instrument.

International audience; Instruments operating in particle accelerators and colliders are exposed to radiations that are composed of particles of different types and energies. Several of these instruments often embed devices that are not hardened against radiation effects. Thus, there is a strong need for monitoring the levels of radiation inside the mixed-field radiation areas, throughout different positions. Different metrics exist for measuring the radiation damage induced to electronic devices, such as the Total Ionizing Dose (TID), the Displacement Damage (DD) and of course the fluence of particles for estimating the error rates of the electronic devices among other applications. In this paper, we propose an SRAM based monitor, that is used to define the fluence of High Energy Hadrons (HEH) by detecting Single Event Upsets in the memory array. We evaluated the device by testing it inside the H4IRRAD area of CERN, a test area that reproduces the radiation conditions inside the Large Hadron Collider (LHC) tunnel and its shielded areas. By using stability estimation methods and presenting experimental data, we prove that this device is proper to be used for such a purpose.

National audience; Cet article présente une analyse d'expérience relative à une approche pédagogique par projet mise en œuvre pour responsabiliser les étudiants face à leur apprentissage en favorisant les rôles d'acteurs et d'auteurs par rapport à celui d'auditeur. Les étudiants concernés sont les élèves-ingénieurs de 4ème année de l'école Polytechnique de Montpellier dans le cadre de leur formation au test industriel de circuits intégrés digitaux.

Despite great improvements of the semiconductor industry in terms of energy efficiency, the computer systems’ energy consumption is constantly growing. Many largely used applications – usually referred to as Recognition, Mining and Synthesis (RMS) applications – are more and more deployed as mobile applications and on Internet of Things (IoT) structures. Therefore, it is mandatory to improve the future silicon devices and architectures on which these applications will run. Inherent resiliency property of RMS applications has been thoroughly investigated over the last few years. This interesting property leads applications to be tolerant to errors, as long as their results remain close enough to the expected ones. Approximate Computing (AxC) , is an emerging computing paradigm which takes advantages of this property. AxC has gained increasing interest in the scientific community in last years. It is based on the intuitive observation that introducing selective relaxation of non-critical specifications may lead to efficiency gains in terms of power consumption, run time, and/or chip area. So far, AxC has been applied on the whole digital system stack, from hardware to application level. This work focuses on approximate integrated circuits (AxICs), which are the result of AxC application at hardware-level. Functional approximation has been successfully applied to integrated circuits (ICs) in order to efficiently design AxICs. Specifically, we focus on testing aspects of functionally approximate ICs. In fact – since approximation changes the functional behavior of ICs – techniques to test them have to be revisited. In fact, some previous works – have shown that circuit approximation brings along some challenges for testing procedures, but also some opportunities. In particular, approximation procedures intrinsically lead the circuit to produce errors, which have to be taken into account in test procedures. Error can be measured according to different error metrics. On the one hand, the occurrence of a defect in the circuit can lead it to produce unexpected catastrophic errors. On the other hand, some defects can be tolerated, when they do not induce errors over a certain threshold. This phenomenon could lead to a yield increase, if properly investigated and managed. To deal with such aspects, conventional test flow should be revisited. Therefore, we introduce Approximation-Aware testing (AxA testing). We identify three main AxA testing phases: (i) AxA fault classification, (ii) AxA test pattern generation and (iii) AxA test set application. Briefly, the first phase has to classify faults into catastrophic and acceptable; the test pattern generation has to produce test vectors able to cover all the catastrophic faults and, at the same time, to leave acceptable faults undetected; finally, the test set application needs to correctly classify AxICs under test into catastrophically faulty, acceptably faulty, fault-free. Only AxICs falling into the first group will be rejected. In this thesis, we thoroughly discuss the three phases of AxA testing, and we present a set of AxA test techniques for approximate circuits. Firstly, we work on the classification of AxIC faults into catastrophic and acceptable according to an error threshold (i.e. the maximum tolerable amount of error). This classification provides two lists of faults (i.e. catastrophic and acceptable). Then, we propose an approximation-aware (ax-aware) Automatic Test Pattern Generation. Obtained test patterns prevent catastrophic failures by detecting catastrophic defects. At the same time, they minimize the detection of acceptable ones. Finally – since the AxIC structure often leads to a yield gain lower than expected – we propose a technique to correctly classify AxICs into “catastrophically faulty”, “acceptably faulty”, “and fault-free”, after the test application. To evaluate the proposed techniques, we perform extensive experiments on state-ofthe-art AxICs.; Au cours des dernières décennies, la demande d’efficacité informatique n’a cessé de croître. L’affirmation d’applications de nouvelle génération consommatrices d’énergie d’un côté, et d’appareils portables basse consommation de l’autre, exige un nouveau paradigme informatique capable de faire face aux exigences concurrentes des défis technologiques actuels. Ces dernières années, plusieurs études sur les applications dites de "Recognition, Mining and Synthesis (RMS)" ont été menées. Une particularité très intéressante a été identifiée : la résilience intrinsèque de ces applications. Une telle propriété permet aux applications RMS d’être très tolérantes aux erreurs. Ceci est dû à différents facteurs, tels que les données bruyantes traitées par ces applications, les algorithmes non déterministes utilisés et les réponses non uniques possibles. Ces propriétés ont été exploitées par un nouveau paradigme informatique de plus en plus établi : le calcul approximé (AxC). L’AxC profite intelligemment de la résilience intrinsèque des applications RMS pour réaliser des gains en termes de consommation électrique, de temps de fonctionnement et/ou de surface de puce. En effet, en introduisant des assouplissants sélectifs des spécifications non critiques, certaines parties du système informatique cible peuvent être simplifiées, pour finalement atteindre l’objectif de l’AxC. De plus, l’AxC est capable de cibler différentes couches des systèmes informatiques, du matériel au logiciel. Dans cette thèse, nous nous concentrons sur les circuits intégrés approximés (AxICs) qui sont le résultat de l’application AxC au niveau matériel. En particulier, nous nous concentrons sur l’approximation fonctionnelle des circuits intégrés, utilisée au cours des dernières années afin de concevoir efficacement les AxICs. En raison de la pertinence croissante des AxICs, il devient important de relever les nouveaux défis pour tester de tels circuits. À cet égard, certains travaux ont attiré l’attention sur les défis que représente l’approximation fonctionnelle pour les procédures de test. En même temps, l’approximation fonctionnelle des circuits intégrés offre également des possibilités. Plus en détails - d’une part - le concept de circuit acceptable change : alors qu’un circuit est conventionnellement bon si ses réponses ne sont jamais différentes de celles attendues, dans le contexte AxIC certaines réponses inattendues peuvent encore être acceptables. Pour la même raison - d’autre part - certaines fautes acceptables peuvent ne pas être détectées, ce qui mène à un gain de rendement de production (c.-à-d., augmentation du pourcentage de circuits acceptables, parmi tous les circuits fabriqués). Pour mesurer l’erreur produite par un AxIC, plusieurs métriques d’erreur ont été proposées dans la littérature. Dans cette thèse, nous présentons un ensemble de techniques de test pour les circuits approximés. En particulier, nous nous concentrons sur trois phases fondamentales du déroulement du test. Premièrement, la classification des fautes AxIC en non-redundant et ax-redundant (c.-à-d. catastrophique et acceptable, respectivement) en fonction d’un seuil d’erreur (c.-à-d. la quantité maximale tolérable d’erreur). Cette classification permet d’obtenir deux listes de fautes (c.-à-d. nonredundant et ax-redundant). Ensuite, nous proposons une génération automatique de séquences de test qui soit “consciente de l’approximation”. Les tests obtenus préviennent les défaillances catastrophiques en détectant les fautes non-redundant. En même temps, ils minimisent la détection sur les ax-redundant. Enfin – puisque dans certains cas le gain de rendement obtenu ne correspond toujours pas à celui attendu, à cause de la structure propre des AxICs – nous proposons une technique pour classer correctement les AxICs dans les catégories “catastrophiquement défectueux” et “acceptablement défectueux”, après l’application du test.

International audience; The Design, Automation, and Test in Europe (DATE) 2017 Conference and Exhibition closed doors last Friday, March 31, 2017, receiving more than 1,500 registrations from over 50 countries and ending with excellent feedback from both participants and exhibitors. 2017 was a special year for the world’s favorite electronic systems design and test conference, as the community celebrated its 20th edition, and it was held for the first time in Switzerland, at the SwissTech Convention Center on the EPFL campus in Lausanne, from March 27–31, 2017.

International audience