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According to previous studies, the workforce competencies of engineers in manufacturing industries generally comprise technical, generic, and knowledge competencies. However, these categories of workforce competencies are insufficient for firms whose manufacturing processes are very easily interrupted by anomalies and whose core competency is highly related to production yield. In addition to drawing attention to the importance of identifying engineers’ problem-solving competencies, this article proposes a procedure to identify and rate workforce competencies for firms in the manufacturing industry. An IC packaging process engineer was used as an example to illustrate the proposed competency identification and rating procedure. In contrast to previous studies, this article suggests that problem-solving competencies can be identified from engineers’ responses to the anomalies commonly encountered in each step of the manufacturing process and that operational competency can be identified from the knowledge, techniques, or capabilities required to fulfill a task in each step of the manufacturing process. For the IC packaging and testing industry, this article can help human resources not only evaluate the competency of job candidates but also design training courses according to the job tenure of engineers. Furthermore, this article results can be used to design teaching material for apprenticeship to help engineers develop competencies in a structured manner and enhance their sensitivities to production-line problems. [ABSTRACT FROM AUTHOR]

Silicon carbide integrated circuits (SiC ICs) have been demonstrated to operate at high temperatures, such as ~460 °C at the Venus’ surface, for two months, and for over a year at 500 °C. At these high temperatures, the SiC integrated circuits and sensors need to be packaged in quite different ways than those below 300 °C. In addition, to integrate more devices into the limited footprint of the high-temperature circuit board, three-dimensional (3-D) packaging is a notable advantage. In this work, 3-D stacking of SiC chips using a gold wirebonding interconnect is investigated. The gold bonding wire is used due to its mechanical robustness and chemical inertness at high temperatures. Triple-stacked SiC chips are bonded to each other and to the gold conduction pads on the alumina substrate with screen-printed gold pastes. The mechanical die shear test, wire pull tests, and interconnect electrical resistance tests are executed and analyzed before and after the 3-D SiC chip packages are subject to a 600 °C thermal aging process in the air for up to 10 days. This 3-D SiC chip packaging has promise for long-duration high-temperatures (up to 600 °C) applications and may be potential for use for applications such as Venus’s surface sensing and telemetry. [ABSTRACT FROM AUTHOR]

Efficient fabrication and high reliability of flexible integrated circuit package substrates (FICS) urgently need effective defect detection methods. Based on the defect categories of FICS images, including yellow circuit backgrounds, film backgrounds with speckles, and black backgrounds, a novel rapid detection algorithm of impurity defects in FICS images is proposed. Three successive procedures are indispensable to realize the rapid detection with high accuracy, including image contrast enhancement based on image gray value analysis, obtaining the standard templates to weaken the texture interferences, and the probability calculation of the background feature of each pixel in the edge region between background and defect. Then, the accurate identification of film/black backgrounds and impurity defects in high-density FICS images is achieved. Furthermore, the comparisons of time–accuracy tradeoff obtained by using existing methods (Lk-means, Ostu, GMEM, SPCNN, MBGCT, FTC) and the proposed algorithm are carried out to experimentally verify the feasibility. The defect detection algorithm will facilitate a solution for the high similarity between the inherent texture features of FICS and external impurity defects at micrometer scale and substantially improve the detection accuracy and efficiency of high-density FICS, which will meet the real-time industrial requirement for the rapid fabrication of high-density FICS. [ABSTRACT FROM AUTHOR]

The annual output value of Taiwan’s wafer foundry and IC packaging test ranks first worldwide. The electronics industry has a complete industrial ecological chain in the supply chain system of global information and communication technology. In order to increase market competitiveness and increase the operational flexibility, manufacturing process outsourcing has become a trend in the business model of the electronics industry. The quality of the outsourcing affects the quality and function of the final product, the outsourcer selection is crucial to ensure the quality of the final product. This article takes the wire bonding process as an example, and proposes a fuzzy selection model of quality-based IC packaging process outsourcers. Then, this article selects the six standard deviation indicator that can fully reflect the process yield and quality level as the evaluation tool. Since the indicator contains unknown parameter, in order to improve the accuracy of estimation and overcome the uncertainty of measurement data, this paper applies mathematical programming to derive the confidence interval of six sigma quality index, and proposes a confidence-interval-based fuzzy testing meth as a green outsourcer selection tool to reduce the risk of misjudgment due to sampling errors and improve the accuracy of the selection. [ABSTRACT FROM AUTHOR]

Transfer-molding process is enjoying growing interest when aiming for novel high-power density system-in-packages (power SiPs), where not only transistors and diodes but also drivers, passives, coils, and transformers are supposed to be integrated in one package. Encapsulating modules in a transfermolding process induces higher mechanical load onto module components compared with conventional silicone potting. Previous investigations have shown that integration of delicate components as ferrite cores into molded packages is not as trivial as integration of conventional surface-mount devices or power semiconductors; the brittle ferrites tend to fracture during the encapsulation process, resulting in higher ferrite core loss. The current study aims to identify main root causes for ferrite core cracking during manufacturing of molded power SiPs. The test vehicle is a symmetrical printed circuit board-based package with three pairs of E-shaped ferrite cores. The epoxy molding compound deployed here is characterized to enable filling simulations. Because technical datasheets of ferrites typically lack specifications of mechanical properties, ferrite materials are analyzed in more detail. Filling simulations and thermomechanical simulations are performed to gain insight into process-induced stress, which may induce cracks in the ferrites. In addition, different ferrite designs are evaluated regarding core losses and mechanical stability and, thus, their tendency to fracture. [ABSTRACT FROM AUTHOR]

Complex looping with five kinks has been commonly used in the stacked die 3-D packaging and simulation models were desired to help control the loop profile in modern thermosonic wire bonding. The traditional finite-element model was time consuming and cost intensive, and the simple link-spring analysis model cannot provide precision simulation of the complex looping as it ignores the stage when the capillary is moving upward from the first bond to the highest point. In this paper, a variable-length link-spring model is proposed to deal with the above problems. In this model, the wire segments and moment equilibrium equations at the opening end of the wire are dynamically added during the capillary upward movement stage, to simulate the wire feeding and loop formation process. The experiment was carried and the complete wire loop profile in the model agree well with the experimental results. Based on this verified model, the effects of various parameters on loop profiles with five kinks were studied. It seems that the first kink height has little effect on the final loop profiles, while the second kink height can change the loop profiles and sweep resistance obviously. [ABSTRACT FROM AUTHOR]

The demand for high-performance, high-functionality packages for integrated circuits continues to grow. Three-dimensional (3D) integration is strongly being pursued to meet this demand and has started to reach maturity and industrial adoption. As advanced 3D system designs progress, requiring higher 3D interconnect density with pitches of 10 mm and lower, traditional chip attachment through solder bump technology will likely face complex manufacturing and reliability challenges. Cu-Cu thermocompression bonding has been proposed as a key 3D-enabling technology and alternative to solder. One of the main issues challenging its commercialization in high-volume manufacturing is the sensitivity of Cu-Cu bond quality to prebond surface conditions. This is especially true for die bonding applications which have limited rework options once chips have been singulated. This article outlines further development and demonstration of a tack and collective bonding scheme for Cu-Cu thermocompression bonding. This approach mitigates many of the thermal and throughput issues of a chip-level Cu-Cu attachment process by performing the quick chip alignment at a low temperature and then subsequently completing all Cu bonding simultaneously. The specific use of an intermediate handle wafer between the tack and collective bonding steps allows chips to be reconstructed into a wafer form that facilitates the cleaning and surface preparation of the chips before bonding using standard wafer processing equipment. A chip-to-wafer test structure designed for Cu pillar-to-pad bonding was used as part of this demonstration and illustrates the feasibility of the application. Full transfer of chips to a receiving device wafer using the tack and collective bonding process is shown with electrical test results and selected bond-integrity metrology confirming substantial bond yield and strength. [ABSTRACT FROM AUTHOR]

The article discusses technical advancements in integrated circuit (IC) multi-die packages, focusing on the use of copper as a metal layer during the process of acid decapsulation. Topics discussed include decapsulation tests performed by Digit Concept, end-of-etch detection method, and accelerate the rinsing process after decapsulation.

On-chip antennas are frequently used as radiating elements for monolithic microwave integrated circuits (MMICs) operating above 100 GHz. Their radiation pattern is wide since the radiator extension is typically about half wavelength. In a package, the wide radiation pattern is easily disturbed by interference from parasitic radiation of the package. In this paper, an approach to minimize and adjust the interference of the package is proposed and applied to a quad flat no leads (QFN) package housing. A structured metal sheet positioned between chip and exposed pad is used to generate enough degrees of freedom for the optimization of the 3-D-radiation pattern in open-cavity and molded QFN packages. For the open-cavity QFN package, a U-shaped slot is introduced, which reduces the propagation of surface waves to the sides and creates a uniform radiation pattern. For the molded QFN package with opening around the on-chip antenna, a corrugated metal sheet is introduced. This leads to a robust packaged radar MMIC with an on-chip antenna at 160 GHz, which provides a directed radiation pattern to boresight. Both optimized radiation patterns are well suited for the illumination of dielectric lenses, which results in a higher lens gain and a lower sidelobe level of the lens pattern compared to the standard QFN packaging. The proposed concepts are verified by measurements for the open-cavity and molded QFN packages at 160 GHz. [ABSTRACT FROM AUTHOR]

The design, materials, process, fabrication, and reliability of a heterogeneous integration of four chips and four capacitors by a fan-out wafer-level packaging (FOWLP) method are investigated in this paper. Emphasis is placed on the application of a new assembly process for fabricating the redistribution layers of the FOWLP. Reliability assessments, such as the thermal cycling and drop test, are also performed. [ABSTRACT FROM AUTHOR]

The Through-Silicon (Si) Via (TSV) is the integration technology for three-dimensional integrated-circuit packaging. The layer-by-layer (LbL) technique has been used to deposit flexible poly(allylamine) hydrochloride (PAH)/polystyrene sulfonate (PSS) multilayers inside scalloped Si trenches of a high aspect ratio, fabricated by the Bosch-etching process. An outstanding control of the thickness and the conformality of the polymer layers, along with a significantly improved planarization, was achieved due to the LbL-technique self-termination effects. In addition, the basic properties of the polymer layers have been characterized: diffusion-barrier properties, adhesion, density, and elastic modulus. The results of this study demonstrate the feasibility of LbL multilayers regarding the TSV liner for the vertical interconnect accesses with a high aspect ratio of highly scalloped surface walls. [ABSTRACT FROM AUTHOR]

The advances in packaging technology in the past decade have overcome a few engineering limitations in integrated circuit (IC) manufacturing. This has greatly complicated the manufacturing process and created a huge challenge in the operations management of the semiconductor back-end production. In particular, the modern demand of lighter and smaller products expedites the multichip packaging technology, which requires reentrant processes and hence makes resource scheduling more difficult. Apart from the fact that IC packaging shares many key features with the semiconductor front-end production, the cycle time of back-end production is significantly shorter than that of the front-end production. Therefore, there is an urgent need of a rapid solution procedure to generate a reliable production schedule for IC packaging. To respond to customer requests efficiently, this paper models the production scheduling of IC packaging as an optimization model and formulates a hybrid genetic algorithm (GA) to solve the problem efficiently. The embedded structure of our model enables the decomposition of the original problems into many small-sized subproblems, which can be solved by available optimization solvers. These subproblems communicate via a master problem, which is solved by a GA to determine the due dates assigned to subproblems. The master and the subproblems are iteratively solved in turn to obtain a satisfactory solution. Computational experiments and an empirical study are performed to validate the efficiency and the feasibility of the proposed approach. [ABSTRACT FROM AUTHOR]

This Letter presents for the first time radio frequency (RF) reliability studies of fully integrated CMOS RF integrated circuits (RFICs) for next generation wireless communication applications involving conformal bodies where wireless communication RFICs will be embedded on ultra‐thin flexible packages. As a test case, RF characteristics of a CMOS voltage‐controlled oscillator (VCO) chip with multiple die‐substrate thicknesses were measured and results are analysed. The CMOS VCO chip under study was designed and fabricated using 180 nm RF‐CMOS process. Reliability of performances of the VCO chips are characterised and results are compared before and after die thinning from 250 to 50, 35, and 25 μm, respectively. Critical RF performance parameters such as frequency of oscillation, output power, and phase noise are considered for analysis, respectively. All the dies are placed face‐up for probing on the top of a metal chuck with ground connection inside the micro‐chamber of a probe station. While the deviations of frequency and output power are within ±1% and ±1 dB, respectively, due to the die thinning affect, the phase noise deteriorations are observed significant. It confirms the well‐known fact of phase noise sensitiveness to the substrate thickness due to the leakage and SOI CMOS is discussed widely to minimise these parasitic effects. [ABSTRACT FROM AUTHOR]

This paper presents a method of modeling bondwires of arbitrary shapes using lumped element models. As an example, a semi-circular multi-wire configuration is presented. Effects of wire angles and dielectric thicknesses are taken into account. A fixture containing three- and five-wire networks is fabricated, assembled, and tested with a vector network analyzer which extracts the S-parameters of each two-port network. These measurements are compared to the proposed model and two benchmark models from a widely used design software package. As a comparison, mean absolute error and root mean square error are used to analyze results showing that the proposed model is better at tracking the measured physical data compared to the two benchmark models. Although semicircular bondwires is presented as an example, any geometry is supported using the proposed model. As an illustration of the easy-use of this proposed bondwire model in a system design, the performance of a high-frequency amplifier is given with and without the bondwire model. The results clearly demonstrate the compatibility of the model with widely used circuit simulators and the importance of including the effects of bondwires when determining circuit performance. [ABSTRACT FROM AUTHOR]

This paper presents a novel organic embedded trace damascene redistribution layer (RDL) process for panel-scale 2.5-D interposers and high-density fan-out package (HDFO) substrates. A minimum feature size of 1.5- \mu \textm line and space using ultrathin polymer dielectrics on glass, silicon, and as well as on organic laminate was demonstrated. This is the first demonstration of a complete set of materials and processes that can be applied to large glass or organic panels, to bridge the interconnect gap between current semiadditive process (SAP) RDL and wafer back-end-of-line (BEOL) RDL. The ultra-fine pitch multilayer RDL structures demonstrated in this paper achieve an optimum balance of high IO density, high electrical performance, and low process costs. IO density in terms of IOs per mm per layer, as defined by Intel, refers to the number of traces routed per millimeter of die edge on one RDL layer of an interposer or package substrate. The current SAP technology can achieve an IO density of about 40 IOs/mm/layer on 510 mm $\times \,\, 510$ mm organic laminate panels. The challenges of fabricating copper metal traces below 5 20~\mu \text{m} or less; 3) high AR of routing traces in the range of 2–4; 4) precise RDL linewidth control; 5) double-sided process with glass core; and 6) reduced number of process steps and panel-scalability leading to lower fabrication costs. [ABSTRACT FROM PUBLISHER]

The mechanical/optical configuration of moiré interferometry for real-time observation of thermal deformations is advanced to quantify the thermomechanical behavior of fan-out wafer level packages (FO-WLPs). Two most notable advancements are on the: 1) mechanical front: conduction-based thermal chamber for a wide range of ramp rates with accurate temperature control, and 2) optical front: microscope objectives to observe a microscopic field of view. The advancements enable the method to document the global and local behavior of an FO-WLP while it is subjected to a controlled thermal excursion. After describing the details of two advancements, a procedure of actual testing is presented. The advanced configuration is implemented to analyze an FO-WLP in a package-on-package with and without a reworkable underfill. The results obtained from the global and local analyses are presented, and reliability implications are discussed. [ABSTRACT FROM PUBLISHER]

Reliability evaluation of integrated circuit (IC) packages to assess drop impact is critical, especially in the case of handheld electronic products. The objective of this study is to experimentally identify the location of damage in solder joints in electronic packaging after a board level reliability (BLR) evaluation. The BLR drop test is a useful way to characterize the drop durability of different soldered assemblies onto a printed circuit board (PCB). It is also of great importance when there is a need to evaluate the solder joint between the chip package and PCB through a daisy-chained structure during the evaluation period. However, there is no detailed information available on a pattern ground with a hatched copper PCB layout for high speed responses that are closely related to actual working conditions. In this paper, a fault location on a daisy-chained structure with a pattern ground is shown through a non-destructive analysis using a time-domain reflectometry (TDR) approach. The results obtained in this project indicate that the TDR approach can be used to detect the location of a crack in the string based on changes in the waveform response. The fault location in critical solder balls as predicted by TDR correlate well with experimental observation by cross-section. [ABSTRACT FROM AUTHOR]

In order to investigate the electrical characteristics of microprobe in integrated circuit testing, a wafer probe admittance testing system with motion control and admittance measurement instruments was organized by using pogo microprobe whose impedance characteristics are automatically measured and analyzed. The probe’s admittance characteristics under different loading frequency were explored based on voltammetry. The results show that the probe was resistive when loading frequency was less than 100 kHz, and being inductive when the frequency was larger than 100 kHz. Furthermore, the probe’s admittance was the least when the frequency was between 200 and 400 kHz. Meanwhile, the conductivity of tipped needle is smaller than claw pin when the frequency is between 1 and 500 kHz, whereas the susceptance and resistance of tipped needle is larger than claw pin, which mainly due to the change of contact between probe and the solder. [ABSTRACT FROM PUBLISHER]

This paper presents an original modular plug-in-type assembly approach for a single-phase inverter. The main focus here is, indicatively, on the power range 1–20 kW, but the methodology can be transferred to higher power levels too. At the core of the inverter lies a power-dense double-sided-cooled half-bridge power switch architecture with integrated cooler, which is interconnected to filter elements, gate driver, and control circuitry by means of compact flat connectors. The integration exercise targets, on the one hand, the optimization of the power switch performance and reliability, as well as the reduction of circuit parasitic elements; on the other, the production of a system compatible with maintenance and repairing, featuring minimized impact of single component failure on the system maintenance and repair cost, and, thus, on its availability. Preliminary experimental tests demonstrate the nominal functionality of the inverter. [ABSTRACT FROM PUBLISHER]

The article discusses the development of a new optical technique to reveal invisible defects and contaminants in advanced packaging applications. It mentions that the technique can reveal contaminants that escape inspection technologies in many advanced packaging applications like wafer level packaging (WLP). It mentions challenges in advanced packaging applications like redistribution layer (RDL) line widths, use of metal and organic polymers.

This study investigates fluid-structure interaction (FSI) analysis of stacked chip in the encapsulation of molded underfill packaging using ANSYS Coupling Work bench with fluid and structural solvers. During encapsulation, FSI analysis is applied to a molded package with different layouts, namely cases 1-4 of stacked chip. An even ratio of inlet and outlet gate pressures is used to produce a regular melt front advancement. An experimental setup is fabricated to validate the simulation results in the FSI study. A digital camera is used to capture the melt front advancement and structural deformation. The interaction between structures (silicon chip) and epoxy molding compound (EMC) is displayed in the displacement profile. Maximum deformation is evaluated during the final stage of filling. The silicon die experiences von Mises stresses, which are monitored to observe the risk of die cracking. The results of this study showed that, the EMC flow front advancement was the fastest in case 4. The pressure distribution of each case was nearly identical, and the maximum von Mises stress was distributed unevenly at the middle of the stacked chip. The proposed analysis can serve as a reference and guide in designing and improving 3D integration packages in industry. [ABSTRACT FROM AUTHOR]

Short-reach optical interconnection mainly focuses on the power consumption, the cost, and the volume. According to these requirements, the design and implementation of a multichannel transceiver are presented in this paper. In this paper, a high-coupling method without the 90° beam deflection is proposed so as to reduce the total power consumption to 0.9 W. Moreover, only the mature and low-cost packaging methods such as wire bonding and flip chip are adopted to satisfy the requirement of the optical coupling, which reduces the cost. Finally, the designed transceiver retains a small size of $28\times 16 \,\, \times $ 3 mm3. To ensure normal function of the transceiver, the organic substrate is carefully designed, and the post-design simulation is conducted to characterize the electrical performance. At last, the test results show that the optical transceiver with this novel packaging structure is able to transmit the data at 10 Gb/s per channel successfully. [ABSTRACT FROM AUTHOR]

In this paper, a rigorous methodology for extracting the thermal compact model parameters of packaged chips is presented. The methodology is based on using a custom-designed test chip with multiple heating and temperature sensing elements in order to predict the temperature distribution in packaged chips after packaging. The technique involves measurement of various chips with different thicknesses, different packages, and for different power dissipation scenarios through which the thermal model parameters can be extracted. The results show that ultrathin chips with a total thickness below 20~\mu \textm experience a dramatically increased temperature for localized heat dissipation. In addition to this, the measurements conducted in time domain and frequency domain show that at high enough frequencies of heat pulsing, the temperature variations become independent of the thermal boundary conditions of the chip. The measurement results are compared to the finite-element method simulation data. The simulations together with the measurement methodology serve as a technique to extract the thermal compact model parameters of packaged chips after being fabricated and packaged in an accurate and efficient way. [ABSTRACT FROM AUTHOR]

This study is for fan-out wafer-level packaging with chip-first (die face-up) formation. Chips with Cu contact-pads on the front side and a die attach film on the backside are picked and placed face-up on a temporary-glass-wafer carrier with a thin layer of light-to-heat conversion material. It is followed by compression molding with an epoxy molding compound (EMC) and a post-mold cure on the reconstituted wafer carrier and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. This is followed by the debonding of the carrier with a laser and then the dicing of the whole reconstituted wafer into individual packages. A 300-mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100 μm has also been fabricated (a total of 32= test packages on the reconstituted wafer). This test package has three RDLs; the line width/spacing of the first RDL is = μm/= μm, of the second RDL is 10 μm/10 μm and of the third RDL is 15 μm/ 15 μm. The dielectric layer of the RDLs is fabricated with a photosensitive polyimide and the conductor layer of the RDLs is fabricated by electrochemical Cu deposition (ECD). [ABSTRACT FROM AUTHOR]

In this paper, bond via array (BVA) wirebond is used to achieve compact vertical integration and improve the electrical performance for system in package (SiP). Two techniques are presented. In the first technique, BVA wirebonds are utilized to integrate some passive or active components vertically onto other components. This significantly reduces the horizontal footprint of the entire SiP. In terms of electrical performance, this vertical integration provides much lower parasitic inductance than conventional 2-D horizontal integration design because of shorter interconnection. For example, the proposed technology can significantly reduce power delivery network impedance compared to a conventional design. In the second technique, we propose BVA wirebond wires as an electromagnetic interference (EMI) shield between different domains within SiP. This provides a lower cost solution for EMI shielding, particularly when regions within a package need to be shielded. [ABSTRACT FROM PUBLISHER]

It is challenging to understand and predict interfacial delamination in multi-layered integrated circuit (IC) packaging due to the difficulties in experimentally quantifying the critical fracture energy of interfacial adhesion. This study takes a combined approach based on molecular dynamics (MD) simulation and finite element method (FEM) to characterize the interfacial fracture energy and predict delamination in the Cu/Ti/SiO 2 /Si multilayer systems. MD simulation is first conducted on each interface of the multiple layers at the atomistic level to obtain the material parameters such as the critical interfacial fracture energy that are required for the interfacial cohesive constitutive relation. Then, FEM is used to model and predict the interfacial delamination of the multi-layered system under indentation loading at the macroscale with the cohesive zone being considered around the delamination or crack tips. Finally, the indentation damage test is performed to validate the modeling results. The proposed combined modeling approach will have the potential to provide guidance in design and applications of IC packaging for improved stability and reliability. [ABSTRACT FROM AUTHOR]

With the fast development of IC (integrated circuit) packaging industry, IC test is becoming more and more important, especially the probe test of the wafer packaging. Based on experimental data and theoretical analysis, an electromechanical model is first proposed to describe the characteristics of the testing process of wafer probe to understand the behavior of micro-probe testing process, and to simulate the whole physical process. The model consists of a dynamic mechanical model, a dc electro-mechanical coupling model and an ac impedance model, which is used to analyze the overall physical properties of the probe test process and has a good agreement with the experimental data. Based on the electromechanical model, a simulation platform is established first, which will provide a simulation tool for the design of the microprobe and setting of multiparameters. [ABSTRACT FROM AUTHOR]

This paper describes the design of a precision bipolar junction transistor based temperature sensor implemented in standard 0.7-μm CMOS technology. It employs substrate p-n-ps as sensing elements, which makes it insensitive to the effects of mechanical (packaging) stress and facilitates the use of low-cost packaging technologies. The sensor outputs a duty-cycle-modulated signal, which can easily be interfaced to the digital world and, after low-pass filtering, to the analog world. In order to eliminate the errors caused by the component mismatch, chopping and dynamic element matching (DEM) techniques have been applied. The required component shuffling was done concurrently rather than sequentially, resulting in a fast DEM scheme that saves energy without degrading accuracy. After a single-temperature trim, the sensor's inaccuracy is ±0.1 °C (−20 to 60 °C) and ±0.3 °C (−45 to 130 °C), respectively. Measurements of sensors in different packages show that the package-induced shift is less than 0.1 °C. Measurements of eight sensors over 367 days show that their output drift is less than 6 mK. While dissipating only 200 μW, the sensor achieves a resolution of 3 mK (rms) in a 1.8-ms measurement time, and a state-of-the-art resolution figure of merit of 3.2 pJK2. This combination of high accuracy, high resolution, high speed, and low-energy consumption makes this sensor suited for commercial and industrial applications. [ABSTRACT FROM AUTHOR]

Wafer-level characterization of functional prototypes of solid state current sensors is usually the first step in the development stage, therefore a dedicated wafer-level measurement systems are required. Especially for MHz characterization, where electromagnetic interference issues became strongly relevant. Thus, for frequencies above 1 MHz, a sophisticated measurement techniques are needed, because parasitic couplings can significantly affect sensor response and other signal processing stages, causing errors or malfunction of the whole system. We propose technique for high immunity MHz current measurement by solid state sensor in wafer-level configuration. The system is especially well-suited for MHz characterization, where electromagnetic interference issues become highly relevant. We showed that balanced transmission provides possibility to reduce interference in the sensor biasing circuit of about 60 dB compared to single-ended method. The effectiveness of the proposed technique was tested in monitoring MHz current in the external line by single magnetoresistive sensors on wafer level. [ABSTRACT FROM AUTHOR]

Portable devices have been popularly used nowadays. Liquid crystal display driver integrated circuit is an essential component in portable devices in which gold bumping process is a critical interconnection technology. To enhance bargaining power and to reduce cost, group suppliers are commonly selected from multiple suppliers. For high-definition display devices, a very low fraction of defectives is the basic quality requirement in gold bumping processes. Unfortunately, conventional yield measurement methods for supplier selection no longer work since any sample of reasonable size probably contains no defective gold bump product items. In this paper, we propose a group supplier selection procedure for multiple suppliers with multiple-line processes that are quite common due to high demands in semiconductor industry. For various significance levels, the number of suppliers, the number of manufacturing lines, predetermined capability requirements, and sample sizes, different selected suppliers are suggested based on the multiple-line yield index Cpk^{M} . In addition, the power comparisons between different methods are also discussed. For the illustration purpose, real-world applications in a gold bumping factory that is located in the Science-Based Industrial Park in Hsinchu, Taiwan, are included. [ABSTRACT FROM PUBLISHER]

In this paper, the Taguchi method and finite-element analysis (FEA) were used to improve the vibration reliability of the package-on-package (PoP) assembly and to achieve an optimal design of the PoP under random vibration loading. A finite-element model of the PoP assembly was developed, and experimental modal tests were performed to verify the finite-element model. Four geometry parameters of the PoP were chosen as the variable factors, including body size of PoP, bottom solder joint standoffs, thickness of bottom substrate, and top solder joint standoffs. The volume averaged von Mises stress of the critical solder joint obtained by FEA was chosen as the quality factor, and an L9 ( 3^4) orthogonal array was applied for Taguchi experiment to estimate the effects of the four factors and find the optimal design of the PoP on the vibration reliability. It is found that bottom solder joint standoffs have an important effect on the reliability, and more than 36% of the volume averaged Von Mises stress could be reduced by the optimal design. [ABSTRACT FROM PUBLISHER]

In this paper, a power/ground (P/G) pin assignment method using simulated annealing (SA) for large-scale high-pin-count ball-grid-array (BGA) packages is proposed. Two objective functions describing the power integrity (PI) and signal integrity (SI) of the pinout are introduced. The SA algorithm is customized to meet the needs of the pin assignment problem. Accelerating strategies are introduced, and some special considerations for customized SA optimization are discussed. The SA method can generate large-scale P/G pinout with any power–ground–signal pin ratios ( P\mathrm {0}/G\mathrm {0}/S\mathrm {0} ) in a few minutes. Large-scale BGA packages with more than 2000 pin numbers including the I/O, core, and different-pair blocks can be generated by the proposed SA method quickly, with a similar PI and SI performance compared to the products from Xilinx and Altera. [ABSTRACT FROM PUBLISHER]

We present a method for quantifying a risk for killer defects at layer level and estimating yield for substrate packages using information from design files. To calculate risk ranks and predicted yield, we define a risk distance that is a key parameter extracted from designs using image processing techniques. In order to validate our model, we analyze two different designs, each having multiple layers, and compare with data from baseline lots. It is shown that there is an inverse correlation between risk layer ranks and yield. Estimated yield based on our model is compared with baseline yield for four layers of the second design. The model-to-baseline yield difference is less than 1% for three layers we tested. [ABSTRACT FROM PUBLISHER]

Under bump metallization (UBM)–Al delamination is a high-value chip-package interaction reliability problem in flip-chip Cu pillar packaging. We devised a test vehicle for quick reliability assessment. We demonstrate that preclean is a critical step to ensure reliable UBM-Al adhesion and achieve bump shear strength >12 g/mil2 for 15- \mu \textm polymer opening. Key parameters affecting bump shear strength, such as UBM critical dimension (CD), polyimide (PI) CD, SiN CD, and PI thickness, were reviewed from both simulation and experimental standpoints and good agreement was achieved between the two. Based on the observed failure mode, a 1-D model was also proposed to correctly predict the experimental trend. Optimum design rules for Cu pillar were outlined. Chip-substrate assembly was demonstrated on 80- \mu \textm bump pitch with staggered bump configuration using mass reflow. Progressive thermal cycling was performed to evaluate package performance. Failure mode was found to be solder crack, verifying the improvement in UBM-Al adhesion. [ABSTRACT FROM PUBLISHER]

This paper shows the investigation of gap waveguide (GW) packaging for an irregular perfect electric conductor (PEC) composed of two layers of metal surfaces. The stopband for a GW with two-layer PEC surfaces is carefully studied, considering the top-layer PEC width, pin size, pin height, columns of pins, as well as dielectric substrate thickness and permittivity. A strategy of the GW packaging for such an irregular PEC surface is presented. In addition to the unit cell-based stopband study, such GW packaging is also demonstrated for a substrate-integrated waveguide (SIW)–microstrip line structure, which is typical of the circuit with two-layer PEC surfaces. A Chebychev bandpass filter built on the SIW and microstrip line is finally designed and fabricated to provide experimental verifications. In particular, a dedicated defect of the side air gap existing in the SIW-based circuits using the GW PMC packaging is found, and an effective remedy is presented. [ABSTRACT FROM PUBLISHER]

Three-dimensional (3D) integration using the through-silicon via (TSV) approach becomes one promising technology in 3D packaging. 2.5D through-silicon interposer (TSI) is one of the applications of TSV technology, which provides a platform for realizing heterogeneous integration on the TSI interposer. However, TSV manufacturing faces several challenges including high cost. Si-less interconnection technology (SLIT) could overcome such challenges and provide the similar function and benefits as TSI interposer. In SLIT technology, TSVs and silicon substrate are eliminated and the back-end-of-line (BEOL) structures are the same as that in the TSI interposer. Thermo-mechanical reliability is still one important concern under process condition and thermal cycling (TC) test condition for both packaging technologies. In this study, solder joint reliability has been investigated and compared for both packaging technologies through finite element analysis (FEA). Reflow process induced low-k stress and package warpage have also been simulated and compared between packages with TSI and SLIT technologies. The simulation results show that SLIT-based package has comparable micro bump TC reliability as TSI-based package, but SLIT-based package has better C4 joint TC reliability than TSI-based package. SLIT-based package also has lower reflow-induced package warpage and low-k stress than TSI-based package. FEA simulation results verify that SLIT-based packaging is one of promising packaging technologies with good thermo-mechanical performance and cost efficiency. [ABSTRACT FROM AUTHOR]

We describe an X-ray diffraction imaging technique for nondestructive, in situ measurement of die warpage in encapsulated chip packages at acquisition speeds approaching real time. The results were validated on a series of samples with known inbuilt convex die warpage, and the measurement of wafer bow was compared with the results obtained by optical profilometry. We use the technique to demonstrate the impact of elevated temperature on a commercially sourced micro quad flat nonlead chip package and show that the strain becomes locked in at a temperature between 94 °C and 120 °C. Using synchrotron radiation at the Diamond Light Source, warpage maps for the entire 2.2~\textrm mm \times 2.4~\textrm mm \times 150 - \mu \textm Si die were acquired in 50 s, and individual line scans in times as short as 500 ms. [ABSTRACT FROM PUBLISHER]

The article discusses the application of plasma focused ion beam (PFIB) technology which provides larger-scale integrated circuit structures a delayering or deprocessing and site-specific failure analysis capabilities. Topics discussed include the technology's ability to modify packaging circuits, the development of an open through-silicon vias (TSV) interconnect technology, and the interconnects quality in microelectronic packaging.

For the objects with repeated motion characteristics such as Integrated Circuit(IC) packaging, Iterative Learning Control (ILC) offers a good scheme for achieving the control of high precise positioning and fast system response. However, in actual production, the performance is significantly deteriorated because of the unavoidable related disturbances when the learning data of a specific position are transferred to other positions, even in the same leading length motion condition. To improve the trajectory tracking performance of the same leading length operations in total workspace, this study proposes an iterative learning controller with wavelet filtering method to eliminate the dependence of iterative learning feed-forward on the special positions of different trajectory conditions. Through the wavelet analysis of the tracking errors with two different starting points, corresponding wavelet coefficients are obtained separately. Then by means of adjusting the wavelet coefficients, the non-consistent disturbance related to positions are removed, thus a universal feed-forward sequence unrelated to the special position is acquired which can be used for trajectory tracking of the same leading length operations in total workspace. Finally, the effectiveness of the proposed method has been demonstrated with the experimental results of a voice coil motor actuating positioning system. [ABSTRACT FROM AUTHOR]

This work proposes a method based on microstrip multi-size T-resonators to increase the accuracy of extracted dielectric characteristics. The dielectric characteristics of an ultra-thin and low-loss build-up substrate for system-in-package modules are obtained, which closely correspond to the measured S-parameters. An electromagnetic simulation is performed to verify the extracted dielectric characteristics. The proposed method is also used to improve the accuracy of prediction of far-field radiated emission at resonant frequencies from a microstrip component. [ABSTRACT FROM PUBLISHER]

Package-on-package (PoP) assemblies may experience warpage during package fabrication and later during surface mount assembly. Excessive warpage may result in loss of coplanarity, open connections, misshaped joints, and reduction in package board-level reliability under environmental stresses of thermal cycling, shock, and vibration. Previous researchers have shown that warpage may be influenced by a number of design and process factors including underfill properties, mold properties, package geometry, package architecture, board configuration, underfill and mold dispense and cure parameters, and package location in the molding panel. A comprehensive inverse model incorporating a full set of design and process parameters and their effect on PoP and PoP assembly warpage is presently beyond the state of the art. In this paper, data have been gathered on multiple PoP assemblies under a variety of assembly parameters. The packages have been speckle coated. The warpage of the PoP assemblies have been measured using a glass-top reflow oven using multiple cameras. Warpage measurements have been taken at various temperatures of the reflow profile between room temperature and the peak reflow temperature. Finite-element models have been created, and the PoP warpage predictions have been correlated with the experimental data. The experimental data set has been augmented with the simulation data to evaluate configurations and parameter variations, which were not available in the experimental data set. Statistical models have been developed to capture the effect of single and multiple parameter variations using principal component regression and ridge regression. The best subset variables obtained from stepwise methods have been used for model development. The developed models have been validated with the experimental data using a single factor design of the experimental study and are found to accurately capture material and geometry effects on part warpage. The results show that the proposed approach has the potential of predicting both single and coupled factor effects on warpage. [ABSTRACT FROM PUBLISHER]

A new sidewall interconnection approach using a perpendicular circuit die is implemented in this paper; this device can be applied to the fabrication of chip stacks. Thermal stress analysis is implemented using the ABAQUS software package to investigate the reliability issues of a stacked chip. The analysis indicates that it has little effect on the reliability of the stacked chip. Experiments were conducted by stacking four chips each having a thickness of 180 \mu \textm ; the configuration of the pads on the test chip is similar to that of a memory chip. The stacked chips were fabricated successfully by dicing the wafer. Vertical interconnection was made by thermo-compression bonding a perpendicular circuit die on an edge of the chip stack. The interconnection quality of the stacked chip was examined through 3-D images obtained via Computed Tomography (CT) and X-ray imagery. The images show that the interconnections were made successfully. The electrical contact resistance of the interconnection is comparable with that obtained using the wire bonding. [ABSTRACT FROM PUBLISHER]

This paper describes a submillimeter-scale package intended for microsystem components in high-pressure and high-salinity environments, such as downhole environments in oil wells. The outer dimensions of the package are 0.8 \times 0.8 \times 0.8 \mathrm{mm}^{3} , whereas the interior cavity is 0.4 \times 0.4 \times 0.45~\mathrm{mm}^{3}$ . The package consists of a stainless steel 17–4 PH metal can and a borosilicate glass lid, and is hermetically sealed by an Au–In bond. The measured bond strength is $\approx 13$ MPa. A component integration strategy is demonstrated: test silicon chips are assembled into a stack using a folded flexible polyimide cable that provides electrical interconnections among the chips. The packages coated with thin-film alumina by atomic layer deposition and Parylene-C survive >48 h in the American Petroleum Institute standard brine (with 8 wt% NaCl and 2 wt% CaCl2 in deionized water) at 80 °C, and subsequently, in 50-MPa ( $\approx 7250$ psi) hydraulic pressure. [2014-0108] [ABSTRACT FROM AUTHOR]

Eutectic compounds play an important role in the fabrication and packaging of devices with low thermal budgets. Taking low-cost polymers into account, eutectic soldering and eutectic bonding temperatures below the glass transition temperature of the aforementioned polymers, 150 °C and below, need to be met. In this regard, thermocompressive eutectic bonding processes of silicon integrated circuits by means of the binary eutectic compounds indium–tin and indium–bismuth were optimized with regard to least necessary thermal energy, and the feasibility thereof onto polycarbonate and poly(methyl methacrylate) substrates was investigated. [ABSTRACT FROM PUBLISHER]

Chip–package interaction (CPI) is becoming a critical issue for the reliability of back-end-of-line (BEOL) during or after package assembly. Complex BEOL layer stacks must have sufficient mechanical strength to survive the thermally induced stresses during processing or working lifetime. Therefore, it is necessary to assess possible failure mechanisms already at early phases of development so that the integrity of the chips can be guaranteed. This paper presents an advanced experimental stability test that combines a BABSI test (Bump Assisted BEOL Stability Indentation test) with in-situ monitoring of the induced stress during this test. A good agreement was found between the applied loads to the BEOL stack, the response of stress sensors below the bump (a Cu pillar) and finite element simulations. [ABSTRACT FROM AUTHOR]

This paper considers electrochemical tin deposition for producing contact elements in integrated circuit packaging. We examine the effect of organic additives to sulfate electrolytes on the growth of local vertical structures, with the aim of suppressing lateral growth of the deposit. [ABSTRACT FROM AUTHOR]

Semiconductor encapsulation is crucial to electronic packaging because it provides protection against mechanical stress, electrical breakdown, chemical erosions, $\alpha $ radiations, and so on. Conventional encapsulants are only applicable below 150 °C. However, with increasing demand for high-density and high-temperature packaging, encapsulants that are functional at or above 250 °C are required. In this paper, five types of encapsulants, including conformal coatings, underfills, molding compounds, potting compounds, and glob tops, are surveyed. First, recommended properties and selection criteria of each type of encapsulant are listed. Second, standard test methods for several crucial properties, including glass-transition temperature ( T_{g}) , coefficient of thermal expansion (CTE), dielectric strength, and so on are reviewed. Afterward, commercial products with high-operation temperature are surveyed. However, the results of the survey reveal a lack of high-temperature encapsulants. Therefore, this paper reviews recent progress in achieving encapsulants with both high-temperature capability and satisfactory properties. Material compositions other than epoxy, such as polyimide (PI), bismaleimide (BMI), and cyanate ester (CE), are potential encapsulants for high-temperature (250 °C) operation, although their CTE needs to be tailored to limit internal stress. Fillers are reported to be efficient in reducing the CTE. In addition, fillers may also have a beneficial impact on the thermal stability of silicone-based encapsulants, whose high-temperature capability is limited by their thermal instability. [ABSTRACT FROM PUBLISHER]

In this paper, we present a complete 700-2,600 MHz RF SiP module for micro base station. This RF SiP design integrates transmitter, receiver, feedback module, ADC/DAC and CLK module. The module consists of two multi-layer organic substrates that are vertically stacked using BGA interconnections. With the integration of 33 chips and about 600 passive components, this RF SiP module retains small form factor and measures 5.25 cm × 5.25 cm × 0.7 cm. The RF input signal transmission path insertion loss is less than 0.34 dB and the return loss is less than −14 dB at 2.6 GHz. Full load thermal simulation result indicates that each chip junction temperature is below 100 °C. We summarize the RF SiP module design, assembly and simulated thermal characteristics. The proposed RF SiP can generally be characterized by small size, low cost and short development cycle. [ABSTRACT FROM AUTHOR]

Thin-film microstrip transmission lines fabricated using a Ti adhesion layer followed by layered Cu, Pt, and Au films are measured to determine tradeoffs between manufacturability issues and microwave performance. Since Ti metal has approximately 25 times the resistance of Cu, and currents in a microstrip line flow mainly at the interface with the substrate where the Ti is located, there is the possibility of increased RF signal losses with this structure. It is found that Ti adhesion layers of $\le 200$ -nm thickness cause minimal loss through 40 GHz on DuPont 9K7 low-temperature cofired ceramic substrates, so there is no significant electrical penalty for employing a metal stackup optimized for mechanical durability. These measurements, together with analysis and simulations suggest this will hold in general as long as the thinner, higher resistance adhesion metal is well below one skin depth in thickness at the operating frequency. [ABSTRACT FROM PUBLISHER]

A numerical model is presented for the portion of the flip-chip joining process where liquid-state solder bumps on the substrate and on the device merge (wet) to form full interconnections. An excellent agreement is demonstrated between calculations and experimental data for the accompanying reduction as a function of time in the device-substrate gap height resulting from the wetting process. The model is based on the detailed description of the random wetting transition of every interconnection in large devices, parametrized by a single parameter describing the wetting dynamics of the solder (including, for instance, the retarding effect of oxidation). This allows the model to be used to systematically study the effect of a number of variables (thermal expansion and heating rates, substrate warpage, spatial distribution of solder bump volumes on the substrate and device, etc.) on the rate of occurrence of important defects that appear during the flip-chip wetting process, such as electrical open (nonwet) or short (bridge) defects. [ABSTRACT FROM PUBLISHER]