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It is shown that the variety of shapes of the input current versus dose curve observed in several ICs is due to circuit effects, depending on the architecture, the value of the currents and the bias conditions. When stages are cascaded, the degradation of the second stage may add or subtract current to the collector current of the input transistor. The variations of the collector currents can be evaluated using the variations of the supply current. It is then possible to model the compensation effects using basic equations and study the impact of irradiation conditions. In some cases, the effect of biasing the circuit during irradiation is to reduce the compensation mechanism leading to an stronger increase in the input current. When a peak shaped degradation curve is recorded, annealing may either induce an additional degradation or a recovery depending on which side of the peak irradiation has brought the circuit. Index Terms--Annealing, bipolar transistors, circuit effects, dose rate, integrated circuits (ICs), total dose.

Electron holography is applied to visualize and directly measure the two-dimensional distribution of the local potential in a high-performance SiGe heterojunction bipolar transistor. The self-assigned base-link construction is investigated and electron holographic measurements of the whole transistor to secondary ion mass spectrometric (SIMS) data are compared.

The demonstration of a hybrid Darlington bipolar junction transistor (BJT) with a high current gain and a power handling capability substantially higher than the power level of previously reported SiC Darlington BJTs, were reported. Also, for the first time, the Darlington characteristic up to an ambient temperature of 150 degree Celsius as well as inductively loaded half-bridge inverter switching characteristic were demonstrated.

An attempt is made to examine the electrothermal consequences of downscaling bipolar transistors, reducing the emitter resistance and implementing substrate modification with the help of electrical measurements, numerical simulations and analytical calculations. These thermal effects set a maximum current for the safe operating region of the device that can be extremely low for devices isolated on all sides by dielectrics.

An attempt was made to demonstrate systematically the temperature-dependent dc characteristics of InGaP-GaAs heterojunction bipolar transistors with and without sulfur treatment. The series resistance of base-emitter junction of studied device can be effectively reduced because of the use of sulfur passivation.

The optimization of AlInAs-GaInAs heterojunction bipolar transistors (HEMTs) for low-noise applications is investigated. An ensemble Monte Carlo simulation is used to study the influence of three important technological parameters on the noise level.

A novel bipolar transistor for extracellular recording the electrical activity of biological cells is presented, and the electrical behavior compared with the field-effect transistor (FET). Electrical coupling is examined between single cells separated from the heart of adults rats (cardiac myocytes) and both types of transistors. To initiate a local extracellular voltage, the cells are periodically stimulated by a patch pipette in voltage clamp and current clamp mode. The local extracellular voltage is measured by the planar integrated electronic sensors: the bipolar and the FET. The small signal transistor currents correspond to the local extracellular voltage. The two types of sensor transistors used here were developed and manufactured in the laboratory of our institute. The manufacturing process and the interfaces between myocytes and transistors are described. The recordings are interpreted by way of simulation based on the point-contact model and the single cardiac myocyte model. Index Terms--Bipolar transistor, cardiac myocyte, electrical coupling, extracellular recording, field-effect transistor, point-contact model.

The sensitivity of SOI technologies to transient irradiations (both dose rate and heavy ions) is analyzed as a function of the technology architecture with experiments and simulations. Two main parameters are considered. First, the thickness of the silicon film, which determines the fully or partially depleted state of SOI devices. This parameter strongly influences the parasitic bipolar, which amplifies the radiation-generated charge. In particular, fully depleted devices show a low bipolar gain due to a high-impact ionization. Secondly, the doping profile in the drain region, which varies with process optimization. The trend is to use shallow junctions to reduce short-channel effects in partially depleted devices. Shallow-drain junctions in partially depleted devices contribute to increases in drain-region sensitivity. As a result, fully depleted architectures are more adapted to reduce the radiation sensitivity of future SOI technologies, because it both reduces the bipolar amplification and the sensitivity of the drain region. Index Terms--Critical charge, cross section, current gain, device simulation, doping profile, dose rate, fully depleted, heavy ion, impact ionization, lightly doped drain, linear energy transfer, MOS transistor, parasitic bipolar transistor, partially depleted, radiation, shallow junction, SOI, SRAM, transient response.

This paper presents the first investigation of the physical origins of the observed variable proton tolerance in multiple SiGe HBT BICMOS technology generations. We use the combination of an extensive set of newly measured proton data on distinct SiGe HBT BiCMOS technology generations, detailed calibrated 2-D MEDICI simulations for both the SiGe HBT and Si CMOS devices, as well as reverse-bias emitter-base and forward-bias electrical stress data to aid the analysis. We find that the scaling-induced increase in the emitter-base electric field under the spacer oxide in the SiGe HBT is primarily responsible for the degraded radiation tolerance with technology scaling, while the decrease in shallow-trench thickness is largely responsible for the improved nFET radiation tolerance with technology scaling. Index Terms--BiCMOS, bipolar transistor, SBT, proton radiation, shallow trench isolation, SiGe, silicon-germanium.

The single-event upset (SEU) responses of three D flip-flop circuits, including two unhardened, and one current-sharing hardened (CSH) circuit, are examined using device and circuit simulation. The circuit that implements the conventional D flip-flop logic using standard bipolar NAND gates shows much better SEU performance than the other two. Cross coupling at transistor level in the storage cell of the other two circuits increases their vulnerability to SEU. The observed differences are explained by analyzing the differential output of the emitter coupled pair being hit. These results suggest a potential path for achieving sufficient SEU tolerance in high-speed SiGe heterojunction bipolar transistor (HBT) digital logic for many space applications. Index Terms--Charge collection, circuit modeling, current-mode logic, heterojunction bipolar transistor (HBT), SiGe, single event effects.

Enhancement and suppression of radiation-induced current-gain degradation in bipolar transistors has been observed after pre-irradiation infrared (IR) illumination under reverse and forward emitter-base bias, respectively. The effect of the IR illumination decreases during isochronal anneal and almost completely disappears at 100[degrees]C. A qualitative physical model has been proposed to explain the experimental results. The effect can be caused by an IR-light-induced transition between the neutral and dipole configurations of the precursor defects without changing the net electric charge. Possible applications of the effects are discussed. Index Terms--Bipolar transistor, infrared illumination, radiation response, defect precursors.

The parasitic bipolar transistor of NMOS/SOI transistors is a key element to determine the single-event upset (SEU) sensitivity. Parasitic bipolar transistor response has been investigated through transient current measurements induced by high energy heavy ions and three-dimensional (3-D) simulations. Experimental results reported allow to estimate the parasitic current gain as a function of the heavy ion location in the MOS transistor. Index Terms--Heavy ion, parasitic bipolar transistor, SOI transistor, transient current measurement.

We present the first systematic experimental and modeling results of noise corner frequency (fC) and noise corner frequency to cutoff frequency ratio ([f.sub.C]/[f.sub.T]) for SiGe heterojunction bipolar transistors (HBTs) in a commercial SiGe RF technology. The [f.sub.C] and [f.sub.C] / [f.sub.T] ratio are investigated as a function of operating collector current density, SiGe profile, breakdown voltage, and transistor geometry. We demonstrate that both the [f.sub.C] and [f.sub.C]/[f.sub.T] ratio can be significantly reduced by careful SiGe profile optimization. A comparison of the [f.sub.C] and [f.sub.C]/[f.sub.T] ratio for high breakdown and standard breakdown voltage devices is made. Geometrical scaling data show that the SiGe HBT with [A.sub.E] = 0.5 x 2.5 [micro][m.sup.2] has the lowest [f.sub.C] and [f.sub.C]/[f.sub.T] ratio compared to other device geometries. An fc reduction of nearly 50% can be achieved by choosing this device as the unit cell in RF integrated-circuit design. Index Terms--Breakdown voltage, corner frequency, cutoff frequency, device modeling, flicker noise, heterojunction bipolar transistor (HBT), low-frequency noise, phase noise, RF integrated circuit (RFIC), SiGe.

A newly developed electrothermal calculation method is implemented to estimate the power loss and working temperature of insulated gate bipolar transistor (IGBT) devices. Based on the measurement of the IGBT's characteristics, the exact estimation of power loss considering the junction temperature is introduced. Then, the thermal network is used to calculate the working temperature. The comparison between experimental and calculation results shows that this method is effective as a designing step with only the time-domain voltage and current data obtained from simulation results. Index Terms--Insulated gate bipolar transistor, junction temperature, power loss.

The parasitic bipolar amplification of silicon on insulator (SOI) devices is analyzed as a function of the technology integration from 0.8 [micro]m down to 0.1 [micro]m. Experiments and simulations show that the bipolar gain does not increase with technology downscaling. The body tie efficiency, to reduce the bipolar amplification, is measured on both transistors and circuits. Implications on the dose rate hardness are deduced on registers with and without body ties as a function of the SOI technology integration. Index Terms--Parasitic bipolar transistor, silicon on insulator (SOI) technologies, transient irradiation.

This paper investigates the impact of proton irradiation on the 1/f noise in ultra-high-voltage chemical-vapor deposition SiGe heterojunction bipolar transistors. The relative degradation of 1/f noise shows a strong dependence on device geometry. Both the geometry dependence and the bias dependence of 1/f noise change significantly after exposure to 2 x [10.sup.13] p/[cm.sup.2] protons. An expression describing the 1/f noise is derived and used to explain the experimental observations. Index Terms--1/f noise, proton irradiation, SiGe heterojunction bipolar transistor (HBT).

The effects of 63-MeV proton irradiation on SiGe: C heterojunction bipolar transistors (HBTs) are reported for the first time. The dc characteristics and neutral base recombination of these SiGe: C HBTs are investigated for proton fluences up to 5 x [10.sup.13] p/[cm.sup.2]. A comparison is made with SiGe HBTs fabricated in the same technology. Despite the fact that these SiGe: C HBTs degrade significantly during proton exposure, there is no indication that the carbon doping has any significant impact on the radiation response. Index Terms--Neutral base recombination, proton irradiation, SiGe: C heterojunction bipolar transistor (HBTs).

The effect of dose rate on radiation-induced current gain degradation was quantified for radiation-hardened poly-Si emitter hpn bipolar transistors over the range of 0.005 to 294 rad(Si)/s. Degradation increases sharply with decreasing dose rate and saturates near 0.005 rad(Si)/s. The amount of degradation enhancement at low dose rates decreases monotonically with total dose. In addition, the effect of ambient temperature on radiation-induced gain degradation at 294 rad(Si)/s was investigated over the range of 25 to 240 [degrees] C. Degradation is enhanced with increasing temperature while simultaneously being moderated by in situ annealing, such that, for a given total dose, an optimum irradiation temperature for maximum degradation results. The optimum irradiation temperature decreases logarithmically with total dose and, for a given dose, is smaller than optimum temperatures reported previously for pnp devices. High dose rate irradiation at elevated temperatures is less effective at simulating low dose rate degradation for the hpn transistor than for the pnp transistors. However, additional degradation of the hpn device at elevated temperatures is easily obtained using overtest. Differences in the radiation responses of the device types are attributed to the relative effects of oxide trapped charge on gain degradation. High dose rate irradiation near 125 [degrees] C is found to be suitable for the hardness assurance testing of these devices provided a design margin of at least two is employed.

A Kelvin contact resistance test structure has been developed for accurate measurement of highly-doped, shallow [n.sup.+] and [p.sup.+] implantations, which are self-aligned to the contact window. Here the structure has been integrated, without additional processing, in a 30 GHz washed-emitter-base n-p-n bipolar process, for the purpose of monitoring the emitter contact resistance. Diffusion taps to the emitter have been made with the phosphorus collector-plug implantation. Phosphorus evaporation from the contact window during the anneal step and the low sheet resistance of the collector-plug implantation, together with the overall design of the test structure, assure a very accurate determination of the emitter contact resistance even in situations where complete junction isolation of the diffusion taps is not directly possible. Results are presented for the optimization of the emitter anneal cycle with respect to the emitter contact resistance.

Communication systems require linear power amplifiers with high efficiency and very low intermodulation distortion. AlGaAs/GaAs heterojunction bipolar transistors (HBT's) were found to have very low intermodulation distortion in power operation. Two-tone tests were carried out on both common-emitter (CE) and common-base (CB) power HBT's. At 7 GHz, the CE HBT showed -20 dBc I[M.sub.3] (third-order intermodulation ratio) and 12% power added efficiency (PAE) per tone at the 1 dB gain compression point; I[M.sub.3] dropped to -30 dBc at 1.5 dB output power backoff. The CE HBT has lower intermodulation distortion than CB HBT. Load pull data were collected to aid the understanding of the intermodulation. Parameters of the Gummel-Poon model (as used in SPICE) were derived for HBT's based on dc data and small-signal S parameters at various bias points. The accuracy and validity of the model were confirmed by comparison to experimental two-tone results. SPICE predicts that the emitter and base resistances linearize the HBT and reduce the third-order intermodulation distortion. The excellent third-order intermodulation performance of the CE HBT makes it a very attractive choice for linear power amplifiers.

The primary degradation in modern bipolar transistors that are subjected to ionizing radiation is a reduction in current gain. There are many factors that influence the total-dose response of bipolar transistors, including emitter bias, transistor polarity, emitter technology, emitter geometry, base design, and dose rate. The effects of each of these factors are investigated. Physical mechanisms consistent with the observed effects are described.

Single-event-induced failure of the Lambda Advanced Analog AMF2805S DC/DC Converter has been traced to burnout of an n-p-n transistor in the MOSFET drive stage. The failures were observed during testing while in inhibit mode only. Modifications to prevent burnout of the drive stage were successfully employed. A discussion of the failure mechanism and consequences for DC/DC converter testing are presented.

A new wideband second generation current controlled conveyor (CCCII) is introduced. The proposed circuit exhibits an intrinsic resistance at port X that is negative. It can also be connected to implement negative controlled resistances that can be either grounded or floating. Comparisons between these implementations with OTA-based ones and conveyor-based ones underline their superiority. SPICE simulation results are given for the proposed CCCII implemented in bipolar technology with the ALA200 transistor arrays from ATT. The simulation results, in good accordance with the theory, underline the high performance achieved by the proposed structure. With [+ or -] 1.5 V supplies, the circuit exhibits bandwidths higher than 40 MHz and a total power consumption of only 1 mW for a bias current [I.sub.o] of 50 [micro]A. For [+ or -] 2.5 V these bandwidths become higher than 240 MHz. Index Terms--Bipolar transistors, current conveyors, current mode circuits, filters, negative resistances, oscillators.

An efficient technique of extracting the small-signal model parameters of the heterojunction bipolar transistor (HBT) is proposed in this paper. The relation between the extrinsic and intrinsic model parameters, which can be employed to drastically reduce the search space, is studied in depth. For the first time, the HBT transistor is characterized by describing S-parameters with a set of complex exponentials using the generalized pencil-of-function method. The reliable initial values of some extrinsic elements can be determined from the set of complex exponentials. This novel approach can yield a good fit between measured and simulated S-parameters. Index Terms--A1GaAs/GaAs, generalized pencil-of-function method, HBT, small-signal model.

It is well known that [C.sub.bc] is the dominant nonlinear element in heterojunction bipolar transistors (HBTs). To study its behavior, an analytical nonlinear HBT equivalent-circuit model has been developed. The present model includes the effect of the ionized donor charge in the depleted collector region compensated by the injected mobile charge. The model-based simulation shows that, at a small-signal range, the third-order intermodulation (IM3) of the normal HBT has the normal 3:1 gain slope generated by the nonlinearity of [C.sub.bc]. At a large-signal level, the load line passes through some regions with constant [C.sub.bc] because its collector is fully depleted by the injected free carriers, and the growth rate of the IM3 is decreased. The punch-through collector HBT has constant [C.sub.bc] during the whole RF cycle, and the IM3, which is generated by [g.sub.m] nonlinearity, has the normal 3:1 gain slope for the all input signal level. Therefore, the IM3 level is significantly lower for the punch-through HBT at a low-power level, but the IM3s of both devices are comparable at a high-power level. The experiment supports our proposed model. Index Terms--Base-collector capacitance, heterojunction bipolar transistors, intermodulation distortion, linearity.

Insulated gate devices, such as metal oxide semiconductor field effect transistors (MOSFETs) or insulated gate bipolar transistors (IGBTs), are increasingly used in high-voltage power converters where a request for fast power switches is growing. Series connection of devices is a viable approach to manage voltages higher than the blocking voltage of the single device. The main problem in such an application is to guarantee the voltage balance across the devices both in steady-state and during the switching transients. In this paper a novel approach is presented, which is used to equalize the voltage sharing during the switching transients. The main advantages of the proposed method consist in avoiding the traditional use of the snubber capacitors, in the output power side, and in working on the gate side. The application of the proposed gate drive technique is firstly discussed and compared with different solutions, hence, validated by experimental tests applied to the control of series connected devices. Finally, a comparison is performed between the transient behaviors of two different configurations: a single switch with high-voltage blocking capability, and in alternative a series of two devices which together ensure the voltage blocking capability of the single switch. The better performances of the latter configuration, working with the proposed control circuit, over the former have been experimentally demonstrated. Index Terms--Active clamp, driving circuit, insulated gate bipolar transistor, MOSFET, series connection.

Low dose rate (LDR) cobalt-60 (0.1 rad(Si)/s) gamma irradiated Silicon Germanium (SiGe) Heterojunction Bipolar Transistors (HBTs) were studied. Comparisons were made with devices irradiated with 300 rad(Si)/s gamma radiation to verify if LDR radiation is a serious radiation hardness assurance (RHA) issue. Almost no LDR degradation was observed in this technology up to 50 krad(Si). The assumption of the presence of two competing mechanisms is justified by experimental results. At low total dose ([is less than or equal to] 20 krad), an anomalous base current decrease was observed which is attributed to self-annealing of deep-level traps to shallower levels. An increase ia base current at larger total doses is attributed to radiation induced generation-recombination (G/R) center generation. Experiments on gate-assisted lateral PNP transistors and 2D numerical simulations using MEDICI were used to confirm these assertions.

In this paper a pencil-and-paper optimized design for current mode logic (CML) and emitter coupled logic (ECL) gates is proposed. The approaches are based on simple models which show errors lower than 20% as compared with Spice simulations. The optimization is performed in terms of bias currents, which give the minimum propagation delay, and it is demonstrated that at the cost of a 10% increase in propagation delay we can reduce the power dissipation by 40%. Strategies to optimize the transistor area of the CML gates are also discussed. A comparison between the optimized CML and ECL is made. It shows the advantage of the CML gate with respect to the ECL in terms of propagation delay. However, this feature of CML is paid for in terms of power dissipation. The simple models and the design strategies are validated by using both a traditional and a high-speed bipolar process, which have transition frequencies equal to 6 and 20 GHz, respectively. Index Terms--Bipolar transistor circuits, bipolar transistor logic devices, current mode logic, digital circuits, digital integrated circuits, emitter coupled logic, high-speed integrated circuits, switching circuits.