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As the relationship between energy and information loss and reversible gates was revealed, much interest in reversible gate design arose, and as quantum-dot cellular automata (QCA) gained attention as a next-generation nano circuit design technology, various reversible gates based on QCA emerged. The proposed study optimizes the performance and design costs of existing QCA-based reversible gates including TR, RUG, PQR, and URG. According to most indicators, the proposed circuits showed significant improvement rates and outperformed existing studies. In particular, the proposed optimal TR, RUG, PQR, and URG showed performance improvements of 266%, 265%, 300%, and 144% in CostAD, respectively, compared with the best existing circuit. This shows outstanding improvement and superiority in terms of area and delay, which are the most important factors in the performance of nano-scale circuits that are becoming extremely miniaturized. Additionally, the exceptionally high-output polarization of the proposed circuits is an important indicator of the circuit's expansion and connection and increases the circuit's reliability. [ABSTRACT FROM AUTHOR]

The need for low power consumption in highly integrated systems-on-chip (SoCs), such as IoT-based smoke detection systems, has made frequent power-ups and power-downs a common practice. Although the device performance degradation caused by such frequent power-ups and power-downs is ignored in most circuit studies, in high-precision bandgap voltage references, the degradation of particular devices can result in a reference voltage shift. This work investigates the effects of frequent power-ups and power-downs on a simple bandgap reference circuit and demonstrates that the effects are real and non-negligible. Aging simulations based on simple bandgap reference circuits are performed to analyze the causes of device performance degradation and circuit output voltage shifts. The simulation results show that frequent power-ups and power-downs induce the negative bias temperature instability (NBTI) effect, a phenomenon that causes performance degradation in devices, such as threshold voltage degradation, under negative bias and high temperature conditions. Further, gate voltage waveforms of these devices were extracted for aging tests and the results of the tests in 14 nm FinFET and the NBTI aging model were used to infer the threshold voltage shift after 10 years at 125 °C. A circuit modification is proposed to mitigate the degradation of device performance and reference voltage shift. This work indicates that NBTI stresses introduced by frequent power-ups and power-downs need to be considered in circuit design. [ABSTRACT FROM AUTHOR]

Background and Objectives: Quantum-dot Cellular Automata technology is a new method for digital circuits and systems designs. This method can be attractive for researchers due to its special features such as power consumption, high calculation speed and small dimensions. Methods: This paper tries to design a three-bits counter with minimum area and delay among the other circuits. As the circuit dimensions are reduced, the area and consequently, the delay are decreased, too. Therefore, this paper tries to design a three-bits counter with minimum dimensions and delay. The proposed counter contains 96 cells and is designed in three layers. It has the least area and delay compared to the priors. Results: The circuit simulation illustrates 0.08 µm2 of area occupation and one clock cycle delay. In comparison with the best previous design, which includes 110 cells, the cells number, area and delay are decreased by 12.72%, 27.27% and 33.33%, respectively. Also, the cost of the circuit has been improved by 54.32%. The power analysis of the design shows 13% reduction in the total energy dissipation of the circuit compared to the best prior work. The circuit reliability versus temperature variations has been simulated and the results represent suitable stability. The fault tolerance of the circuit which is occurred by the displacement faults represents normal operation of the circuit. Conclusion: As the counter is an element which is implemented in several digital systems, its area reduction causes the whole system area to be reduced. Also, the circuit delay has been decreased significantly which means that the circuit can be employed by high speed systems. [ABSTRACT FROM AUTHOR]

With the development of semiconductor technology, the size of transistors continues to shrink. In complex radiation environments in aerospace and other fields, small-sized circuits are more prone to soft error (SE). Currently, single-node upset (SNU), double-node upset (DNU) and triple-node upset (TNU) caused by SE are relatively common. TNU’s solution is not yet fully mature. A novel and low-cost TNU self-recoverable latch (named NLCTNURL) was designed which is resistant to harsh radiation effects. When analyzing circuit resiliency, a double-exponential current source is used to simulate the flipping behavior of a node’s stored value when an error occurs. Simulation results show that the latch has full TNU self-recovery. A comparative analysis was conducted on seven latches related to TNU. Besides, a comprehensive index combining delay, power, area and self-recovery—DPAN index was proposed, and all eight types of latches from the perspectives of delay, power, area, and DPAN index were analyzed and compared. The simulation results show that compared with the latches LCTNURL and TNURL which can also achieve TNU self-recoverable, NLCTNURL is reduced by 68.23% and 57.46% respectively from the perspective of delay. From the perspective of power, NLCTNURL is reduced by 72.84% and 74.19%, respectively. From the area perspective, NLCTNURL is reduced by about 28.57% and 53.13%, respectively. From the DPAN index perspective, NLCTNURL is reduced by about 93.12% and 97.31%. The simulation results show that the delay and power stability of the circuit are very high no matter in different temperatures or operating voltages.

As the relationship between energy and information loss and reversible gates was revealed, much interest in reversible gate design arose, and as quantum-dot cellular automata (QCA) gained attention as a next-generation nano circuit design technology, various reversible gates based on QCA emerged. The proposed study optimizes the performance and design costs of existing QCA-based reversible gates including TR, RUG, PQR, and URG. According to most indicators, the proposed circuits showed significant improvement rates and outperformed existing studies. In particular, the proposed optimal TR, RUG, PQR, and URG showed performance improvements of 266%, 265%, 300%, and 144% in CostAD, respectively, compared with the best existing circuit. This shows outstanding improvement and superiority in terms of area and delay, which are the most important factors in the performance of nano-scale circuits that are becoming extremely miniaturized. Additionally, the exceptionally high-output polarization of the proposed circuits is an important indicator of the circuit’s expansion and connection and increases the circuit’s reliability.

The integration density of electronic systems is limited by the reliability of the integrated circuits. To guarantee the overall performance, the integrated circuit reliability must be modeled and analyzed at the early design stage. This paper reviews some of the most important intrinsic aging mechanisms of MOSFETs and elaborates the physical mechanism of the coupling between aging effects. Then the progress in reliability modeling under static and dynamic operational voltages is reviewed. It is found that although these models can accurately predict the degradation in short term, they are with large errors for the long-term degradation prediction. Besides, for the circuit-level reliability modeling and simulation approach, there are still problems to be solved. This article aims to provide guidance for researchers and practitioners in integrated circuit field, and highlight the challenges for reliability research. It is of great significance to the optimization of the reliability of integrated circuits.

Transistor scaling steadily approaches fundamental limits. Sustaining circuit reliability becomes an overwhelming challenge for foundries and their manufacturing processes. Therefore, early and rapid characterization of degradation effects impacting the circuits’ transistors becomes essential. Such degradation effects are caused by design-time variation due to manufacturing variability and/or run-time variation due to transistor aging. In this work, we are the first to employ brain-inspired HDC for circuit reliability. HDC is quickly emerging as an attractive light-weight machine-learning solution. Nowadays, it is mainly applied to bio-signal processing or language recognition. We bring the research of HDC to the next level by demonstrating how it can be applied to address the challenges in circuit reliability. This has far-reaching consequences due to the large savings achieved by 1) reducing the amount of training data and hence the development cycle, 2) removing the need to send the data to the cloud for model training, and 3) speeding up significantly the characterization and classification tasks due to the fast edge-inference. We demonstrate the viability of HDC using SRAM and other circuits as examples. HDC outperforms traditional machine learning methods, such as support vector machine or random forest, in accuracy and requires up to 20x fewer training samples. For a given budget of samples, HDC achieves a 4x smaller error. Our implementation and analysis are based on industrial $14 \;\mathrm{n}\mathrm{m}$ 14 n m FinFET fully calibrated with Intel measurements with respect to both transistor electrical characteristics as well as manufacturing variability. Open Source: Our framework including the algorithm implementation is available for the community to explore other algorithms and circuits at https://github.com/ML-CAD/HDC-Circuit-Reliability. [ABSTRACT FROM AUTHOR]

In aerospace environments, high reliability and low power consumption of chips are essential. To greatly reduce power consumption, the latches of a chip need to enter the power down operation. In this operation, employing non-volatile (NV) latches can retain circuit states. Moreover, a latch can be hit by a radiative particle in the aerospace environment, which can cause a severe soft error in the worst case. This paper presents a NV-latch based on resistive random-access memories (ReRAMs) for NV and robust applications. The proposed NV-latch is radiation-hardened with low overhead and can restore values after power down operation. Simulation results demonstrate that the proposed NV-latch can completely provide radiation hardening capability against single-event upsets (SEUs) and can restore values after power down operation. The proposed NV-latch can reduce the number of transistors in the storage cells by 50% on average compared with the other similar solutions. [ABSTRACT FROM AUTHOR]

As CMOS devices become smaller, aging-induced and process variations become major issues for circuit reliability. In this paper, a statistical gate sizing method is proposed to improve the lifetime reliability of manufactured chips in the presence of process variations and aging effects. To this end, we propose a canonical first order delay model to estimate the delay degradation of a gate under negative bias temperature instability and process variations considering spatial correlations. Using the proposed gate delay model, a statistical static timing analysis method is introduced to compute the circuit delay considering the joint effect of process variation and negative bias temperature instability. To guarantee that the circuit meets the required timing constraints, we propose an incremental gate sizing technique. This technique first computes the criticality of each gate defined as the probability that a gate lies on the critical path due to negative bias temperature instability and process variations. Then, a group of gates with the highest ranking according to criticality is chosen for a gate sizing-based timing optimization. It is worth nothing that, by using the proposed statistical gate delay model, we can compute the criticality of each gate incrementally. Experimental results based on ISCAS’85 benchmark circuits show that the proposed method can improve the lifetime reliability defined as $1.1(\mu + 3\sigma)$ of the initial delay distribution of the circuit at the expense of 8.64% area overhead. In comparison with the path-based method, the proposed approach is much faster, especially for larger circuits, which makes it a viable solution to optimize the lifetime reliability of very large-scale circuits used in industry. [ABSTRACT FROM AUTHOR]

The energy-efficient circuits, though important in IoT and biomedical applications, are vulnerable to soft errors due to their low voltages and small node capacitances. This paper presents an energy-efficient low-area double-node-upset-hardened latch (EEDHL). The proposed latch enhances the radiation hardness by employing a restorer circuit based on a Muller C-element and a memory element. The post-layout simulations show that the EEDHL improves the area–energy–delay product (AEDP) by ∼ 80% compared to the newly reported double-node-upset-resilient latch (DNURL) in STMicroelectronics 65-nm CMOS technology. Synopsys TCAD mixed-mode simulations in 32-nm CMOS technology framework are also used to validate the proposed DNU-hardened latch. The proposed EEDHL effectively mitigates the DNU at the strike with a linear energy transfer (LET) equal to 160 MeV ⋅ cm 2 /mg in 32-nm CMOS technology. [ABSTRACT FROM AUTHOR]

Aggressive technology scaling makes modern advanced SRAMs more and more vulnerable to soft errors such as single-node upsets (SNUs) and double-node upsets (DNUs). This paper proposes two SRAM cells; the first one is called Quadruple Cross-Coupled SRAM (QCCS) and the second one is called Sextuple Cross-Coupled SRAM (SCCS). The QCCS cell comprises four cross-coupled input-split inverters to keep stored values, and provides self-recoverability from SNUs at low cost. To improve reliability, the SCCS cell uses six cross-coupled input-split inverters to construct a large error-interceptive feedback loop and hence robustly keep stored values. The SCCS cell can self-recover from all possible SNUs and one part of DNUs; for remaining DNUs, a node-separation mechanism is used to avoid their occurrence. Simulation results demonstrate the robustness of the proposed cells. Moreover, compared with the state-of-the-art hardened cells, i.e., NASA13T, RHBD12T, We-Quatro, Zhang14T, QUCCE12T, DNUSRM, QCCM10T, QCCM12T, S4P8N, and S8P4N, the QCCS cell reduces read access time by 17%, write access time by 19%, power dissipation by 4% and silicon area overhead by 10% on average, while the SCCS cell reduces read access time by 44% as well as write access time by 13% on average at the cost of moderate increase in power dissipation and silicon area overhead. [ABSTRACT FROM AUTHOR]

The impact of Electromigration (EM) on the Bit-Error-Rate (BER) of signal interconnect paths was experimentally examined. An array-based test-vehicle for tracking Bit-Error-Rate (BER) degradation of signal interconnects subject to Direct-Current (DC) EM stress was implemented in a 16nm FinFET process. A unit interconnect path comprises five identical interconnect stages where each wire is driven by inverter based buffers. Accelerated EM stress testing is achieved entirely on-chip using metal heaters located directly above the devices-under-test (DUTs) and separate stress circuits driving both ends of the wire. The proposed test structure features a ring-based Voltage-Controlled-Oscillator (VCO), a bit-pattern generator and local BER sampling monitors which enable bitwise tracking of ‘0’ and ‘1’ errors separately, further simplifying the overall test-setup and allowing for high precision characterization of EM induced resistance shifts using only digital circuits. Measurement data collected from the 16nm prototype reveals unique insights into EM induced signal path degradation that was not available prior to this work. Our experimental studies suggest that monitoring the BER of an interconnect path could be used as a new metric for capturing EM induced resistance shifts in a real system, in lieu of the conventional approach which focuses on monitoring standalone wire resistances. Supplemental simulations showcasing the projected degradation in the interconnect path operating frequency as a function of stress time constructed from resistance traces sampled from identical wires implemented in the same process reaffirm the measurement trends. [ABSTRACT FROM AUTHOR]

With the aggressive scaling of feature size, Negative Bias Temperature Instability (NBTI) and Process Variation (PV) have become major issues for circuit reliability and yield. In this paper, we analyze the variation of gate delay by jointly considering NBTI and PV effects. Using Gaussian Process Regression (GPR) learning interface, a Statistical Gate Delay Extraction (SGDE) framework is proposed. Typical types of logic gates are simulated with commercial 28 nm technology for verifying the performance of SGDE in the experiment. Compared to the golden data, the results show that our proposed approach achieves minimal loss of accuracy with significant runtime speed-up. [ABSTRACT FROM AUTHOR]

Very large scale integration (VLSI)‐based neuromorphic systems have been evolving quickly in recent years. These systems have been used in complex cognitive tasks such as image classification and pattern recognition. A neuromorphic encoder is an essential component in a neuromorphic system, which converts sensory data into spike trains. The advancement in CMOS technology nodes leads to various reliability issues. Bias temperature instability (BTI) and hot carrier injection (HCI) are major reliability issues in analog/mixed VLSI circuits. This paper implements a temporal neuromorphic encoder, and a corresponding mathematical model is derived for image processing applications. The relationship between an input image pixel value and output of the encoder, that is, interspike interval (ISI), is found to be exponential. The impact of BTI and HCI on the temporal neuromorphic encoder is analyzed. The degradation analysis revealed a loss of encoding functionality for which three mitigation techniques are discussed. Finally, a reliability‐aware neuromorphic encoder is proposed to minimize the effect of degradation over its lifetime. The power consumption of conventional and proposed reliability‐aware neuromorphic encoders is also presented. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Computer-Aided Design & Computer Graphics / Jisuanji Fuzhu Sheji Yu Tuxingxue Xuebao is the property of Gai Kan Bian Wei Hui and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

NBTI degradation of FinFET devices is stochastic due to the inevitable variations in manufacturing processes. The stochastic behavior of NBTI degradation is modeled with different ΔV TH distributions. Various leading semiconductor industries report different ΔV TH distributions like Gamma, Normal, and Dispersive Skellam (DS) to model the NBTI induced variability. In this work, different NBTI induced variability models from the literature are used to investigate the impact on circuit performance. The combined effect of time-zero and various NBTI induced variability distributions on SRAM read and write metrics is discussed in detail. NBTI degradation in SRAM depends on the stored data pattern. Hence, we also report the impact of stored data patterns on the SRAM metric. To further analyze the impact of ΔV TH distributions on SRAM metrics, the correlation between SRAM metrics is studied. • A close agreement between various reported ΔV TH distributions due to NBTI and generated distributions is obtained. • The impact of different ΔV TH distributions on SRAM static and dynamic metrics at FinFET technology is investigated. • This work also investigates the impact of stored data patterns with different NBTI induced variability on SRAM metrics. • The correlation between static and dynamic metrics is also studied for time-zero and after NBTI degradation. [ABSTRACT FROM AUTHOR]

This work presents measured data showcasing neutron-radiation-induced single-event transient (SET) pulse widths in distinct standard logic gate types, together with a detailed analysis on the choice of design parameters impacting the corresponding sampled pulsewidth distributions. The SET pulsewidth distributions are obtained from a high-density, array-based characterization vehicle, implemented in 65-nm planar CMOS and 16-nm FinFET processes, featuring a tunable, high-resolution pulse shrinking chain together with a closely embedded sampling circuit to avoid width distortion effects. The proposed macro uses standard logic gate chains in varying lengths, threshold voltages ($V_{\mathrm {TH}}$), and transistor width flavors as the devices under test (DUTs). The measured irradiation data for a range of operating voltages from nominal down to near-threshold reveal the relative impact of the chosen design parameters such as VDD, $V_{\mathrm {TH}}$ , device width, and the logic chain length and their interplay, impacting the overall soft error susceptibility and the sampled pulsewidth distributions among the different standard gate types. [ABSTRACT FROM AUTHOR]

In aerospace environments, high reliability and low power consumption of chips are essential. To greatly reduce power consumption, the latches of a chip need to enter the power down operation. In this operation, employing non-volatile (NV) latches can retain circuit states. Moreover, a latch can be hit by a radiative particle in the aerospace environment, which can cause a severe soft error in the worst case. This paper presents a NV-latch based on resistive random-access memories (ReRAMs) for NV and robust applications. The proposed NV-latch is radiation-hardened with low overhead and can restore values after power down operation. Simulation results demonstrate that the proposed NV-latch can completely provide radiation hardening capability against single-event upsets (SEUs) and can restore values after power down operation. The proposed NV-latch can reduce the number of transistors in the storage cells by 50% on average compared with the other similar solutions.

Water uptake in porous low-k dielectrics has become a significant challenge for both back-end-of-line integration and circuit reliability. The influence of absorbed water on the mechanical properties of plasma-enhanced chemical-vapor-deposited organosilicate glasses (SiCOH) was investigated with nanoindentation. The roles of physisorbed (α-bonded) and chemisorbed (β-bonded) water were examined separately through annealing at different temperatures. Nanoindentation measurements were performed on dehydrated organosilicate glass during exposure to varying humidity conditions. The elastic modulus and hardness for as-deposited SiCOH are intimately linked to the nature and concentration of the absorbed water in the dielectric. Under mild-annealing conditions, the water-related film mechanical property changes were shown to be reversible. The mechanical properties of UV-cured SiCOH were also shown to depend on absorbed water, but to a lesser extent because UV curing depopulates the hydrophilic chemical groups in SiCOH. High-load indentation tests showed that in-diffusion of water in the film/substrate interface can degrade the hardness of SiCOH/Si film stacks significantly, while not significantly changing the elastic modulus. [ABSTRACT FROM AUTHOR]

Theoretically, normally‐off silicon carbide (SiC) junction field‐effect transistors (JFETs) do not require a negative gate voltage supply because they are in an off‐state when the gate–source voltage is 0 V. However, most gate drivers for normally‐off SiC JFETs require not only a positive power supply for turning on the JFET but also a negative power supply for turning it off and maintaining a negative gate–source voltage to suppress a false turn‐on power loss caused by crosstalk during fast switching. Therefore, modifications of gate drivers increase complications and costs. In this study, a normally‐off SiC JFET gate driver, which can be realized using a simple circuit configuration with a single power supply, is proposed. To minimize undesirable crosstalk, the gate‐source voltage of the JFET is driven to a negative value and retained in the state for a long period of time. © 2020 Institute of Electrical Engineers of Japan. Published by Wiley Periodicals LLC. [ABSTRACT FROM AUTHOR]

To meet the requirements of both high reliability and low power in low-orbit aerospace applications, this article first presents a single-event Double-Upset (SEDU) self-Recoverable and single-event Transient (SET) Pulse Filterable (DURTPF) latch design with low power. The DURTPF latch mainly consists of eight mutually feeding-back C-elements (CEs) and an SET pulse filterable Schmitt-trigger (ST). To make an ST behave not only as a pulse filterable ST but also as an error interceptive CE, an input-split ST is created, leading to an enhanced-version of the DURTPF latch, namely DURTPF-EV. The DURTPF-EV latch mainly consists of seven mutually feeding-back CEs including an input-split ST. Simulation results demonstrate both the SEDU self-recoverability and SET pulse filterability of the proposed latches at the cost of moderate silicon area. Using the clock gating technology, the DURTPF latch reduces power dissipation by about 63% on average compared with the state-of-the-art SEDU self-recoverable latch designs that are not SET-pulse filterable. Moreover, the DURTPF-EV latch is more cost-effective and its reliability is also enhanced, making it more suitable for low power and low-orbit aerospace applications. [ABSTRACT FROM AUTHOR]

Bias Temperature Instability (BTI) is one of the most crucial reliability issues in modern CMOS technology. It leads to shift in device parameters, which eventually affect circuit performance. SRAM is a widely used circuit which occupies a considerable area in microprocessors. Hence it is important to understand the impact of BTI on performance/stability of SRAM. As device degradation due to BTI depends on gate activity, SRAM performance strongly depends on the data stored in the cell. In this paper, the gate activity is incorporated by activity factor 'α' which takes into account the various data patterns stored in the cell. Although many studies have reported the impact of BTI on SRAM performance, none focused on the worst degradation scenario. Our analysis with varying activity factor 'α' provides an opportunity to identify the data pattern for worst case degradation. Shift in threshold voltage due to BTI is modelled according to continuous and non-continuous applied gate bias, using physics-based compact model. Process variability is incorporated using Monte Carlo (MC) simulations and worst-case degradation at distribution tail is identified. In this paper, we consolidate various SRAM performance metrics from literature over the last three decades and demonstrate the impact of BTI and process variability with activity factor 'α' on these metrics. [ABSTRACT FROM AUTHOR]

As technology scales down, circuits are more prone to incur in faults and fault detection is necessary to ensure the system reliability. However, fault‐detection circuits are also vulnerable to stuck‐at faults due to, for example, manufacturing defects or ageing; a fault can cause an incorrect output in the fault‐detection scheme; so concurrent fault detection is, therefore, needed. Cyclic redundancy checks (CRCs) are widely used to detect errors in many applications, for example, they are used in communication to detect errors on transmitted frames. In this study, an efficient method to implement concurrent fault detection for parallel CRC computation is proposed. The scheme relies on using a serial CRC computation circuit that is used to periodically check the results obtained from the main module to detect the faults. This introduces a lower circuit overhead than existing schemes. All CRC encoders and decoders that implement the CRC computation in parallel can employ the proposed scheme to detect faults. [ABSTRACT FROM AUTHOR]

This article presents neutron radiation-induced soft error rate (SER) statistics and detailed analysis thereof, revealing a multitude of circuit parameters impacting the soft-error susceptibility of standard combinational logic in advanced CMOS nodes. A high-density array-based soft-error characterization vehicle is presented, featuring standard logic gate chains of varying lengths. Neutron irradiation data obtained from gate variants employing devices with distinct channel widths and threshold voltage flavors is analyzed at multiple supply voltages, ranging from nominal down to near-threshold. Supplemented with first-order simulations, measured SER cross-section results obtained from test structures implemented in a 65-nm planar CMOS technology node reveal the complex interplay between factors, such as supply voltage, node capacitance, restore current (IRESTORE), gate topology, and logic chain length responsible in contributing toward the collective soft error susceptibility of a standard gate type, which constitutes the main focus of this article. In addition, the easy process portability of the proposed macro is demonstrated through implementation in a 16-nm FinFET process. [ABSTRACT FROM AUTHOR]

Variation in CMOS device parameters due to reliability issues like Bias Temperature Instability (BTI) and Hot Carrier Injection (HCI), etc., has posed serious performance concerns in various digital and analog/mixed-signal circuit designs, which include neuromorphic circuits. CMOS-based neuromorphic circuits, also known as silicon neurons (SiNs), are designed to emulate the electrophysiological behavior of biological neurons. Neuromorphic systems are used to learn and adapt in various applications like image processing and classification, wearable/implantable systems, robotics, etc. that require high performance. It is therefore, important to analyze neuromorphic circuits performance over their lifetime. This is achieved by identifying the specific transistors affecting circuit performance and to come up with workable ways to solve these problems. In this work, we have investigated the combined effect of NBTI and HCI on two types of Integrate-and-Fire (I&F) SiNs, Axon-Hillock (AH) and Simplified Leaky Integrate-and-Fire (SLIF) circuits, using key performance parameters. Novel reliability-aware AH and SLIF circuits are proposed to mitigate the reliability issues. The proposed reliability-aware designs show negligible deviations in the performance parameters after degradation. The time-zero process variability analysis is also carried out for the proposed reliability-aware SiNs. The power consumption of existing and proposed reliability-aware neuron circuits is analyzed and compared. • This work analyzes impact of reliability (BTI and HCI) and time-zero variability on key performance parameters of two spike-event neuron circuits, Axon-Hillock (AH) and Simplified Leaky Integrate and Fire (SLIF) silicon neuron circuits. • The study identifies transistors responsible for performance degradation in both conventional AH and conventional SLIF circuits. • Reliability-aware silicon neuron circuits are proposed for minimizing the effects of degradation and to dissipate power more efficiently than conventional neuron circuits. • The proposed reliability-aware design, consisting of diode-connected transistors, is most effective in lowering transistor degradation. • The study demonstrates the importance of considering reliability in neuromorphic circuit designs, enabling the development of resilient and accurate neuromorphic systems. [ABSTRACT FROM AUTHOR]

Soft errors such as single-node upset (SNU) and multiple-node upset (MNU) have become a major problem for SRAMs in aircraft and terrestrial applications. In this letter, a novel low-cost and write enhancement soft-error-aware-14T (LWS14T) SRAM cell is proposed to provide sufficient protection against soft errors. The obtained observations demonstrate that the LWS14T can recover not only from SNUs but also from MNUs irrespective of the upset polarity. Furthermore, compared to considered RHBD cells, the LWS14T has reduced the cost in terms of power and delay. Also, the LWS14T gives the better critical charge, better stability, and better writability. [ABSTRACT FROM AUTHOR]

All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit’s performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too.

In the past years, the conformal coating on the printed circuit board has been widely used because it offers several advantages in terms of protection and reliability of electronic circuits. However, the coating is a dielectric material, which can impact on the performance of radio-frequency components such as microstrip filters. Hence, the coating characterisation from the dielectric point of view is essential in order to design filters that meet prefixed requirements. Although the dielectric properties of commercial conformal coatings are well known, specific analyses on the effect of the coating on devices performance for space applications are not present in the literature and the coating manufactures do not often provide an appropriate characterisation of dielectric properties, making the analysis and the design of the microstrip filters difficult. The authors discuss numerical and experimental results regarding the performance of a coupled microstrip filter and show that the presence of CV-1152 coating causes a significant shift of the S-parameters. Moreover, a new configuration of the filter based on a fractal shape is proposed, which is characterised by more compact size and an optimised bandwidth.

boost circuit has been widely used in photovoltaic generation system and electrolytic capacitor is one of the most vulnerable components in the circuit. Equivalent series resistance (ESR) is an important index to reflect the reliability of capacitor. Real-time online monitoring and evaluation of ESR parameter has great significance to improve the reliability of boost circuit. In this study, a non-invasive online method to monitor and evaluate output capacitor's ESR in boost converter in continuous conduction mode is proposed. The ESR is calculated by sampling two specific periods of output voltage in a switching cycle. The calculation method is verified with the boost circuit model. The experimental results demonstrate the effectiveness of this method.

This article presents an energy-efficient triple-node-upset (TNU)-tolerant latch in a subthreshold/near-threshold regime. The proposed latch provides the TNU tolerance using two restorer circuits (RCs) to hold the correct state and a three-input clocked combinational majority circuit (CMC). The $RC$ is based on pull-up and pull-down paths, controlled by different susceptible nodes, results in better radiation hardness. We validated the proposed latch in the STMicroelectronics 65-nm CMOS technology. The postlayout parasitic extracted simulations show that, by employing the proposed latch, an average improvement of ~42% in an area-energy-delay product (AEDP) is obtained over the recently reported TNU-hardened latch (TNUHL) at a supply voltage of 0.4 V. We also validated the proposed TNUHL in a 32-nm CMOS technology node using technology computer-aided-design (TCAD) mixed-mode simulations. In the 32-nm technology, our latch can provide a TNU tolerance up to a value of linear energy transfer (LET) equal to 190 Mev-cm2/mg. The HSPICE postlayout simulations and the TCAD mixed-mode simulation results clearly show that the proposed latch effectively tolerates TNU. [ABSTRACT FROM AUTHOR]

A novel reliability-aware clock distribution network clock distribution network in a 3-D I/O interface packaging integrating memristor ratioed logic (MRL) is presented. An evolutionary algorithm has been employed to obtain the optimal reliability tradeoffs and the placement of the intertier clock delivery network. To improve the signal integrity, to increase the power efficiency, and to decrease the clock noise, through-silicon vias transfer the clock along with the power/ground links in a symmetric-centroid arrangement. The proposed reliability-aware 3-D packaging clock distribution network (CDN) can significantly decrease the clock skew/jitter and propagation delay, increase the energy efficiency, and improve the signal quality of the whole aged system. The proposed on-chip 3-D CDN architecture is analyzed and designed using a 65-nm CMOS technology at 1.0 V. The results show that the reliability and power efficiency of the proposed CDN with optimization has been significantly improved for a 15-year aged circuit. Moreover, the clock latency and the total power consumption of the proposed MRL-based CDN are improved around 10% and 22%, respectively, under process, voltage, and temperature variations. [ABSTRACT FROM AUTHOR]

With technology scaling, the susceptibility of circuits to different reliability degradations is steadily increasing. Aging in transistors due to bias temperature instability (BTI) and voltage fluctuation in the power delivery network of circuits due to IR-drops are the most prominent. In this paper, we are reporting for the first time that there are interdependences between voltage fluctuation and BTI aging that are nonnegligible. Modeling and investigating the joint impact of voltage fluctuation and BTI aging on the delay of circuits, while remaining compatible with the existing standard design flow, is indispensable in order to answer the vital question, “what is an efficient (i.e., small, yet sufficient) timing guardband to sustain the reliability of circuit for the projected lifetime?” This is, concisely, the key goal of this paper. Achieving that would not be possible without employing a physics-based BTI model that precisely describes the underlying generation and recovery mechanisms of defects under arbitrary stress waveforms. For this purpose, our model is validated against varied semiconductor measurements covering a wide range of voltage, temperature, frequency, and duty cycle conditions. To bring reliability awareness to existing EDA tool flows, we create standard cell libraries that contain the delay information of cells under the joint impact of aging and IR-drop. Our libraries can be directly deployed within the standard design flow because they are compatible with existing commercial tools (e.g., Synopsys and Cadence). Hence, designers can leverage the mature algorithms of these tools to accurately estimate the required timing guardbands for any circuit despite its complexity. Our investigation demonstrates that considering aging and IR-drop effects independently, as done in the state of the art, leads to employing insufficient and thus unreliable guardbands because of the nonnegligible (on average 15% and up to 25%) underestimations. Importantly, considering interdependences between aging and IR-drop does not only allow correct guardband estimations, but it also results in employing more efficient guardbands. [ABSTRACT FROM AUTHOR]

Intensive scaling of Integrated Circuits is a crucial factor for achieving high performance and astronomical packing density. However, this scaling is pushing planar MOSFET to its physical limitations. Nowadays, FinFET emerges as a promising alternative technology for planar MOSFET, due to their better efficiency. Nevertheless, this inevitably leads to a rising concern on the reliability of FinFET as the circuit lifetime reliability cannot be neglected due to this accelerated scaling of Integrated Circuits. This paper is considered as the first work that: 1) detects which CMOS technology, planar MOSFET or FinFET, is more robust against Bias Temperature Instability (BTI) aging degradation for the advanced nodes such as 16 nm; 2) precisely computes the effect of BTI on 16 nm FinFET using an adequate BTI Reaction Diffusion model that takes into consideration the effects of finite oxide thickness, and the influence of polysilicon; 3) investigates the efficiency in terms of power consumption and area for the predominant circuit level techniques that could be implemented to overcome the negative impact of BTI for FinFET technology. This research clearly indicates that FinFET technology is more robust against BTI aging degradation than planar MOSFET as the delay percentage for FinFET technology is lower than planar MOSFET technology by 26%. • FinFET is more robust against BTI than planar MOSFET as the delay percentage for FinFET is lower than planar MOSFET • BTI aging degradation does not have negative impact on power for both FinFET and planar MOSFET technologies • It's a tradeoff between overhead area and leakage power as MOSFET has lower overhead area, and FinFET has lower leakage power [ABSTRACT FROM AUTHOR]

In the past years, the conformal coating on the printed circuit board has been widely used because it offers several advantages in terms of protection and reliability of electronic circuits. However, the coating is a dielectric material, which can impact on the performance of radio-frequency components such as microstrip filters. Hence, the coating characterisation from the dielectric point of view is essential in order to design filters that meet prefixed requirements. Although the dielectric properties of commercial conformal coatings are well known, specific analyses on the effect of the coating on devices performance for space applications are not present in the literature and the coating manufactures do not often provide an appropriate characterisation of dielectric properties, making the analysis and the design of the microstrip filters difficult. The authors discuss numerical and experimental results regarding the performance of a coupled microstrip filter and show that the presence of CV-1152 coating causes a significant shift of the S-parameters. Moreover, a new configuration of the filter based on a fractal shape is proposed, which is characterised by more compact size and an optimised bandwidth. [ABSTRACT FROM AUTHOR]

High‐speed backplane connectors are extensively used in digital baseband communication circuits. Connector degradation may lead to deterioration of the integrity of digital signals and is one of the major causes of low communication quality. In this study, an accelerated test was used to produce degraded connector samples. Based on the degradation characteristics of the connector electrical contact surface, the differential transmission method was applied to enhance signal integrity in such degraded electrical contact circuits. Referring to the Gigabit Ethernet standard, the differential signal waveforms and eye diagrams of high‐speed channels with un‐degraded and degraded connectors were studied. Improvement of the circuit reliability by differential transmission was demonstrated from the perspectives of both experimental investigations and analysis using probability calculations. [ABSTRACT FROM AUTHOR]

In nanometric integrated circuits, reliability has become one of the main design measures. This makes the reliability evaluation process an inevitable part in the circuit design flow. In this paper, a probabilistic method has been developed for reliability evaluation of combinational logic circuits. At the core of the proposed method, correct and incorrect probabilities for binary logic values (0 and 1) of a circuit’s gate are derived using probability transfer matrix and the correct and incorrect probabilities of gate’s inputs. An efficient approach has been proposed to handle the reconvergent fanouts problem using correlation coefficients concept. Both accuracy and scalability of the proposed method have been illustrated by various simulations on ISCAS 85 and LGSynth91 benchmark circuits. The results have shown a less than 2% average error for reliability estimation comparing Monte Carlo simulation. Comparing to state-of-the-art methods the proposed approach has a better performance in reliability estimation and algorithm runtime. [ABSTRACT FROM AUTHOR]

boost circuit has been widely used in photovoltaic generation system and electrolytic capacitor is one of the most vulnerable components in the circuit. Equivalent series resistance (ESR) is an important index to reflect the reliability of capacitor. Real-time online monitoring and evaluation of ESR parameter has great significance to improve the reliability of boost circuit. In this study, a non-invasive online method to monitor and evaluate output capacitor's ESR in boost converter in continuous conduction mode is proposed. The ESR is calculated by sampling two specific periods of output voltage in a switching cycle. The calculation method is verified with the boost circuit model. The experimental results demonstrate the effectiveness of this method. [ABSTRACT FROM AUTHOR]

This brief presents a double-node upset (DNU) self-recoverable latch design for high performance and low power application. The latch is mainly constructed from eight mutually feeding back C-elements and any node pair of the latch is DNU self-recoverable. Using a high speed transmission path and a clock gating technique, the latch has high performance and low power dissipation. Simulation results demonstrate the DNU self-recoverability of the latch and also show that the delay-power-area product of the latch is improved approximately by 81.80% on average, compared with the latest DNU self-recoverable latch designs. [ABSTRACT FROM AUTHOR]

Emerging nanoscale computing structure quantum‐dot cellular automata (QCA) is evolving as a possible replacement for complementary metal–oxide–semiconductor technology in near future. Being a new technology, it is prone to various types of fabrication‐related faults and process variations. So, QCA‐based circuits are prone to errors, and therefore pose significant reliability‐related issues. Hence, there is an emerging need to design fault‐tolerant QCA‐based circuits to mitigate the reliability issues. This study first presents QCA‐based new designs of 2‐input Exclusive‐OR gate and 1 bit full adder using conventional design approach without redundant QCA cells. Then, the fault tolerance has been implemented in these designs by introducing redundant QCA cells. The proposed circuits exhibit significant improvements in fault‐tolerant capability against cell omission, misalignment, displacement, and extra cell deposition defects. The proposed fault‐tolerant designs have been compared with existing designs in terms of generalised design metrics of QCA circuits. Energy dissipation results have been computed for the proposed fault‐tolerant circuits using accurate QCAPro power estimator tool. Influence of temperature variations on the polarisation of the proposed fault‐tolerant circuits has also been investigated. The functionality of the proposed circuits has been verified with QCADesigner version 2.0.3 tool. [ABSTRACT FROM AUTHOR]

Maximizing the return on investment of a photovoltaic array requires a power electronics converter with the longest possible operational life. This paper is aimed at presenting a heatsink optimization approach to enhance the survival probability of a high-efficiency 1 kW DC/DC converter, specifically designed for PV applications. A main feature of the enhancement is that it takes into account the meteorological characteristics of the intended installation site: a coastal area with high humidity and cloudiness throughout the year. As a first step, the converter reliability is estimated according to the FIDES procedure, yielding a mean time between failures MTBF = 98.15 FIT. The numerical results pinpoint the diodes as the most failure-prone components, and temperature as the dominant stressor, clearly suggesting that the performance can be improved by resorting to better heatsinks. As a second step, a heatsink optimization problem is established, involving three objective functions: minimization of heatsink thermal resistance and weight, and maximization of the cooling system performance index, The problem is solved using a genetic algorithm, which yields MTBF = 74.09 FIT. The approach takes advantage of the computer tools currently available: mathematical toolboxes to implement the optimization algorithm, user-friendly reliability prediction software, and software packages capable of simulating the thermal behavior of heatsinks with good accuracy. [ABSTRACT FROM AUTHOR]

The article presented a laboratory station for diagnosing the digital circuits and the test results on the basis of a selected example. The idea of a response compression technique, which is called an analysis of signatures, was demonstrated. The main element of the station includes 8-bit programme of an analyser of signatures, which was developed by the authors, and implemented in the LabVIEW environment with the use of NI 6008 data analysis module. The programme operation was tested on the selected digital circuit, and the obtained results were provided in the article. [ABSTRACT FROM AUTHOR]

Introduction of new conduction mechanism called junctionless in MOSFETs takes us to another direction in device fabrication. Moving from inversion to junctionless devices in nanoscale regime proves a good alternative for low-power applications and overcomes the barrier of lightly doped channels. 6T-SRAM circuits, the first to arrive in the market long ago, still occupy its area in modern-day ICs too. In this work, four topologies of 6T-SRAM namely Flex-V th , Flex-PG, PG-SN, and FinFETs are generated based on inversion type independent double-gate as well as common double-gate devices. For the first time, the same four topologies are also generated using junctionless devices. In nanoscale range, the reliability of circuits is given paramount importance since they are easily affected by radiation. This 6T-SRAM's radiation sensitivity is studied and from our simulation results, the common double-gate based 6T-SRAM shows good performance over the independent double-gate based 6T-SRAM in both inversion and junctionless type. [ABSTRACT FROM AUTHOR]

With the downscaling of CMOS devices, dynamic variability induced by negative bias temperature instability (NBTI) has become a critical issue. In addition to the time-dependent device-to-device variation (DDV) of NBTI degradation, the cycle-to-cycle variation (CCV) originated from random trap occupation is found non-negligible and should be added into the total dynamic variation. This paper summarizes our recent studies on NBTI-induced dynamic variability, focusing on the CCV effect, with more details on the statistical modeling, circuit reliability simulation methodologies and experimental results. By adding the random trap occupation into consideration, a statistical model for total dynamic variation (DDV + CCV) is proposed. The effective occupancy probability p eff is introduced as a key parameter for modeling and circuit reliability simulation. With the statistical trap response (STR) method and modified on-the-fly method, the proposed model is validated by the experimental evidence under both DC and AC NBTI. According to the model and experimental results, circuit reliability simulation framework is proposed for both long-term quasi-static and short-term transient performance evaluation with the additional impact of CCV. Two representative digital circuit units, ring oscillator (RO) and SRAM cell, are simulated under different conditions, indicating it necessary to consider the evident influence of the CCV in accurate circuit reliability evaluation. The results are helpful for the reliability/variability-aware circuit design in nanoscale technology. [ABSTRACT FROM AUTHOR]

In this study a careful analysis of the device and the circuit level variability and reliability are presented. Planar 20 nm System on Chip (SoC), 16 nm FinFET (16FF) and 10 nm FinFET (10FF) devices are studied to understand the time-zero process variability and Bias Temperature Instability (BTI) stress induced (time dependent) threshold voltage (V T ) variations to evaluate the device degradation. Moreover, to understand the circuit level variability, the 6-Transistor (6T) SRAM performance is assessed in terms of the static noise margin (SNM) degradation under the influence of BTI stress. Finally, the product level SRAM performance is studied in terms of the minimum SRAM operating voltage (Vmin) degradation. [ABSTRACT FROM AUTHOR]

A series-connected current source converter (CSC) based configuration has recently been proposed for offshore wind energy conversion systems. A big challenge exists for such a system that its maximum insulation level is the full transmission voltage due to its monopolar operation. This introduces significant burden to the system in terms of cost, reliability, and flexibility. To solve this issue, a bipolar operation giving a half insulation requirement is proposed and investigated in this paper. However, a unique challenge exists for the CSC-based system when operating under bipolar mode, that is, the dc-link current control. There are two equivalent paths for the dc-link current, which introduces a concern for proper operation of the bipolar system. Accordingly, an optimized dc-link current control is developed in this study. In summary, the bipolar system with the help of the optimized dc-link current control features lower insulation requirement, higher reliability, higher efficiency, and higher flexibility. Finally, both simulation and experimental results are provided. [ABSTRACT FROM AUTHOR]