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In this article, we provide a comprehensive evaluation of width modulation capabilities of both nanosheet (NS) and forksheet (FS) devices, going from device level to a block level implementation. The main innovation introduced by the FS consists of a dielectric wall added between the p- and nMOS transistors. Leveraging this feature, FS shows approximately the same current behavior as NS, considered a state-of-the-art reference, but reduced parasitic capacitance thanks to its fewer but wider stacked sheets. At block level, an area reduction up to 12% is observed with FS, alongside a 13% power reduction and 10% frequency increase. Following the device comparison, the potential of sheet width modulation as additional power, performance, and area (PPA) optimization technique during synthesis and place and route (PNR) is investigated. A description of the specific steps required to enable this knob in a conventional electronic design automation (EDA) framework is provided. As demonstrated by the obtained experimental results, the same frequency of the single-width implementation can be achieved using mixed libraries with lower power consumption (13% and 16% for NS and FS, respectively), leading to improved energy efficiency. Furthermore, it is shown how designs implemented using FS benefit more from this type of optimization than the ones using NS, with a 12%–15% energy reduction compared to the 8.5%–14% obtained with NS. [ABSTRACT FROM AUTHOR]

Carbon nanotube field effect transistors (CNFETs) have potential applications in future logic technology as they display good electrostatic control and excellent transport properties. However, contact resistance and leakage currents could limit scaling of CNFETs. Non-equilibrium Green’s function (NEGF) simulation investigates that coupling between contact metal and CNT impacts both contact resistance and leakage current. The physical mechanisms underlying the effects are analyzed. A model with calibrated metal coupling strength from experimental data projects ION-IOFF design space to understand the trade-off between shrinking contact and extension lengths. For CNT with diameter of 1 nm, both contact and extension lengths greater than 8 nm are a good compromise between ION and IOFF for digital logic in advanced technology nodes. [ABSTRACT FROM AUTHOR]

We propose and demonstrate, with hardware, the first experimental technique to measure a vertical component of FinFET source resistance. Forward bias is applied to the well-to-source p-n junction, and the forward voltage at constant current density, ${V}_{{\text {fb}}}$ , is measured as a function of source-current, ${I}_{\text {ds}}$. The source-current, ${I}_{\text {ds}}$ , is varied by variation of ${V}_{\text {gs}}$ , and an effective vertical resistance is calculated, ${R}_{\text {ve}} =$ dVfb/dIds. Significant self-heating effects of the p-n junction are observed, and we demonstrate a technique to correct ${V}_{\text {fb}}$ for the local rise in temperature. We find that our technique gives well-behaved results for vertical source resistance. Quantitative ${R}_{\text {ve}}$ values are found to be consistent with technology characterization of (linear region) total device resistance. [ABSTRACT FROM AUTHOR]

The 10/7nm node has been introduced by all major semiconductor manufacturers (Intel, TSMC, and Samsung Electronics). This article looks at the power-performance benefit of the 10/7nm node as compared to the previous node (14nm). Specifically, we track the power-performance in high performance space, using Intel's Core-i7 (Intel's highest performance consumer microprocessor that uses the highest performance CMOS technology node) manufactured in Intel's 10nm. The paper first looks at the scaling of the device power-performance from the Intel 14++nm node to Intel 10nm, using 3D TCAD simulation with dimensions obtained from actual product cross-sections, and also scaling of the interconnect capacitance node-to-node. Next, the paper does a comparison of industry 10/7nm node technologies (from Intel, TSMC, and Samsung Electronics). The paper argues that for Intel, in the 10nm nodes, the total chip power at constant frequency (energy-per-operation) has scaled by a much lower amount vs. the 14++ node, as compared to the 14++ vs. the previous (22 nm) node. The lack of power scaling can be traced to a reduction in current per device perimeter (caused by the increased device parasitic resistance and the reduced device and fin pitch) and to an increase in capacitance per fin (caused by an increase in the FinFET height). Proper scaling of the device is critical for chip power scaling (energy-per-operation) at upcoming nodes, especially as it applies to high performance microprocessors and for the data analyzed here this is not the case.

Nanosheet field-effect transistors (NSFETs) have emerged as a novel device replacement for sub-7nm CMOS technology nodes. However, due to smaller fin thickness (Tfin = 5nm), NSFETs are more vulnerable to the process-induced variations. Among various types of process-induced variations, Line edge roughness (LER) is becoming a significant concern for multi-gate field-effect transistors (MugFETs) with smaller feature sizes. In this article, we have reported and compared the impact of LER on the electrical characteristics of NSFETs and nanowire field-effect transistors (NWFETs) for the sub-7nm technology node. We have generated a 3-D LER profile using 2-D Auto Covariance Function (ACVF) that considers two degrees of freedom for a realistic roughness analysis at advanced CMOS technology nodes. For a complete study of 3-D LER effect in NSFET, we have considered roughness along the nanosheet's sidewalls as well as top and bottom surfaces. We have shown using 3D TCAD simulations that the sidewall roughness in NSFETs contributes to a negligible mismatch in threshold voltage and ON current. The mismatch performance of NSFET is compared with that of the NWFET for sub-7nm technology node. NSFET appears to be more immune to mismatch in ON current than NWFETs considered in this work. On the other hand, as compared with NSFET, owing to its superior gate all-around control, the NWFET achieves lower mismatch in drain induced barrier lowering (DIBL) and subthreshold slope (SS) in presence of LER. In addition to this, FETs with different channel doping modes such as inversion (IM) and Junction less (JL) mode have been compared for their matching performance against 3-D LER. It can be concluded from the results that IM FETs are more immune to 3-D LER as compared to JL FETs.

SRAM bitcell area reduction, lower SRAM parasitic resistance, and higher drive strength are necessary to continue with technology scaling. Nanosheet (NSH) technology improves SRAM cell write-ability by having 50 mV more write trip point (WTP) than FinFET (FF) SRAM due to reduced bit line (BL) resistance (due to wider metal CD) and more drive current strength (more than 15%) than FF for the same leakage. However, due to higher bitcell area (20% larger), BL, and word line (WL) parasitic capacitance than FF, NSH SRAM would not compete with FF SRAM in terms of the read delay (26% more delay) and energy at the 3-nm technology node. PFET to NFET (PN) spacing, composed of gate cut, gate extension, and Fin pitch in an SRAM bitcell, is critical for SRAM cell height because it can take ~46% of the 111 SRAM total cell height. The forksheet (FSH), achieving extremely scaled PN space in SRAM bitcell due to device structure with limited additional processing complexity, reduces the SRAM bitcell area. As a result, BL and WL parasitics reduce and improve the SRAM read delay and stability. FSH SRAM saves 6% area benefit and achieves 24% lesser read delay than FF high density (HD) SRAM. [ABSTRACT FROM AUTHOR]

This paper tracks the scaling of total chip power at constant frequency (i.e., energy-per-operation) through the last few CMOS nodes. The focus is on high-performance microprocessors. To evaluate the progression of chip power, Intel’s Core-i7 (Intel’s highest performance consumer microprocessor manufactured in the highest performance CMOS technology node) was used as the benchmark. Core-i7 has been manufactured for eight generations starting in the 45-nm node and continuing through the 14++ node. This paper argues that in the more recent nodes, the total chip power at constant frequency (energy-per-operation) has scaled much less than that of the earlier CMOS nodes. The early 14-nm technology exhibited particularly poor power scaling, and in fact, the technology was improved by increasing the device current and relaxation of the contacted gate pitch in 14++. Early product data in 10 nm points to issue in dropping the chip power (at constant frequency) relative to the previous node (14++), which may challenge the power-performance justification for scaling to the 10 nm node and beyond. Improving chip power scaling (energy-per-operation) in upcoming nodes is critical as a key part of the value proposition for continued CMOS scaling, especially as applied to high-performance microprocessors.

Routing closure and design-for-manufacturability (DFM) challenges exacerbate nonrecurring engineering (NRE) costs, a steep barrier to entry for advanced sub-20-nm CMOS nodes, making low-volume fabrication of integrated circuits (ICs) almost intangible. For ICs in which the cost of design dominates the fabrication, we seek to trade some amount of chip area to lower NRE costs. To this end, we consider designing logic cell layouts for easier routing and DFM closure. We accustom a layout simplification and reuse approach to build standard cell libraries such that good pin access and layout regularity are ensured for all cells. Using a commercial 14-/16-nm technology, we developed two 100-cell logic cell libraries that are, respectively, 9 and 10.5 metal tracks tall. Our routing experiments on multiple designs show that taller cells can endure 20% higher placement density while reducing the number of design rule check (DRC) violations by four orders of magnitude compared with a commercial 7.5 track library. Silicon measurements show that taller cells can enable faster design closure in ICs with stringent performance requirements at the cost of a marginal power overhead. Finally, our logic cell design approach can make advanced CMOS nodes more affordable for low-volume design. [ABSTRACT FROM AUTHOR]

This paper explains the hidden positive feedback in a two-stage fully differential amplifier through external feedback resistors and possible DC latch-up during the amplifier start-up. The biasing current selection among the cascade branches has been explained intuitively, with reference to previous literature. To avoid the latch-up problem, irrespective of the transistor bias currents, a novel hysteresis-based start-up circuit is proposed. An 87 dB, 250 MHz unity gain bandwidth amplifier has been developed in 65 nm CMOS Technology and post-layout simulations demonstrate no start-up failures out of 1000 Monte-Carlo (6-Sigma) simulations. The circuit draws 126 μ A from a 1.2 V supply and occupies the 2184 μ m2 area. [ABSTRACT FROM AUTHOR]

Abstract This paper introduces a 9-bit time-based capacitance-to-digital converter (T-CDC). This T-CDC adopts a new design methodology for parasitic cancellation with a simple calibration technique. In T-CDCs, the input sensor capacitance is first converted into a delay pulse using a capacitance-to-time converter (CTC) circuit; then this delay signal is converted into a digital code through a time-to-digital converter (TDC) circuit. A prototype of the proposed T-CDC is implemented in UMC 0.13 μm CMOS technology. This T-CDC consumes 8.42 μW and achieves a maximum SNR of 45.14 dB with a conversion time of 1 μs that corresponds to a figure of merit (FoM) of 16.4 fJ/Conv. [ABSTRACT FROM AUTHOR]

Scaling transistors and following Moore’s law have served the industry well for more than 50 years in providing integrated circuits that are denser, cheaper, higher performance, and lower power. And despite occasional reports of its demise, Moore’s law is alive and well. But progress in scaling CMOS has not come easily. We’ve had to continually invent and introduce new materials and new device structures to deliver the performance, power, and cost improvements expected of each new technology generation. This article describes trends in CMOS scaling over the past decade and discusses some of the new device options and technology directions being explored to continue scaling into the future. [ABSTRACT FROM AUTHOR]

In this paper, we present an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors (VFETs) and lateral GAA transistors (LFETs) using 5-nm node design rules. Optimizations of the nanowire (NW) diameter and the gate length are also conducted to enhance the SRAM performance. Device VT retargeting has been proposed for improving the minimum operating voltage ( V\min ) of SRAMs. The isoperformance and isoyield have been performed to assess and determine the benefits provided by LFET and VFET architectures, respectively. Our results show that the VFET bitcells are denser than the LFET bitcells by 20%–30%. The SRAM read stability (read static noise margin) is significantly improved using the NW channel. For a $6\sigma $ yield target and an isoarea of SRAM bitcells, V\min of the VFET bitcell is 80 mV lower than LFET designs. Applying the proposed VT retargeting technique can allow the VFET 122 bitcell to operate at 0.57 V without using assist circuits. A standby leakage below 10 pA/cell can be achieved for both architectures. At isoperformance, the standby leakage of VFET bitcells is $2.6\times $ lower than LFET bitcells. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the impact of a single discrete charge trapped at the top oxide interface on the performance of scaled nMOS FinFET transistors. The charge-trapping-induced gate voltage shift is simulated as a function of the device scaling and for several regimes of conduction-from subthreshold to ON-state. Contrary to what is expected for planar MOSFETs, we show that the trap impact decreases with scaling down the FinFET size and the applied gate voltage. By comparing drift-diffusion with nonequilibrium Green functions simulations, we show that quantum effects in the charge distribution and transport can reduce or amplify the impact of discrete traps in simulation of reliability resilience of scaled FinFETs. [ABSTRACT FROM AUTHOR]

The ballistic injection velocity is examined in state-of-the-art Si extremely thin SOI MOSFETs using ballistic quantum simulations and a virtual source (VS) compact model. The results indicate that the device performs at around 50%–60% of its ballistic limit and that the ballistic injection velocity at the top of the potential barrier (ToB), as obtained by numerical simulation, can be significantly lower than its counterpart extracted at the VS. This occurs because, at high drain bias, the ToB moves under the influence of gate bias toward the source contact, where additional mobile charge resides that are not directly induced by the gate contact but by the source contact. This effect becomes increasingly important as channel length shrinks and is affected by several factors, including the details of the source design. The accurate estimation of a physically meaning “injection velocity” under ballistic limit could be therefore very difficult in very short channel MOSFETs. [ABSTRACT FROM AUTHOR]

Heavy-ion experiments on spatially isolated inverters and densely populated inverters demonstrate the effects of transistor density on single-event (SE) transients in bulk CMOS. Increased transistor density reduces SE cross section dramatically while having little impact on transient pulse width. [ABSTRACT FROM PUBLISHER]

Because of its different current injection mechanism, a tunnel field-effect transistor (TFET) can achieve a sub-60-mV/decade subthreshold swing at room temperature, which makes it very attractive in replacing a metal–oxide–semiconductor field-effect transistor, particularly for low-power applications. It is well known that some specific TFET structures show a good drain current ID saturation in the output characteristics, whereas other structures do not. A detailed investigation, through extensive device simulations, of the role of the channel on the drain-potential dependence of double-gate TFET characteristics is presented in this paper for the first time. It is found that a good saturation of ID is observed only for devices in which a thin silicon body is used. A relatively thick silicon body or gate-drain underlaps result in the penetration of the drain electric field through the channel, which does not allow the drain current to saturate, even at higher drain voltages. [ABSTRACT FROM AUTHOR]

In this paper, Zirconium dioxide nanoparticle has been synthesized using wet chemical methods at room temperature. The structural characterization (SEM / X-ray Diffraction) of the nanoscaled Zirconium Dioxide is discussed in this paper. The particle size of the ZrO2 is observed in the range of 50-100 nm. It is expected that both the nanoscaling and the high dielectric constant of ZrO2 would be an advantage while fabricating a FET. The conventional dielectric SiO2 used for gate, with a dielectric constant of >3.9, obviously cannot survive the challenge of an End of Oxide Thickness (EOT ≤ 1 nm). The synthesized ZrO2 in the nanoscale is subjected for impedance analysis (results are presented here) and is found to have a dielectric constant of 23. Due to the high-κ value, it is expected to be superior than SiO2 as a gate material. [ABSTRACT FROM AUTHOR]

A simple semiempirical model ID ( VGS, VDS) for short-channel MOSFETs applicable in all regions of device operation is presented. The model is based on the so-called "top-of-the-barrier-transport" model, and we refer to it as the "virtual source" (VS) model. The simplicity of the model comes from the fact that only ten parameters are used. Of these parameters, six are directly obtainable from standard device measurements: 1) gate capacitance in strong inversion conditions (typically at maximum voltage VGS = Vdd); 2) subthreshold swing; 3) drain-induced barrier lowering (DIBL) coefficient; 4) current in weak inversion (typically Ioff at VGS = 0 V) and at high VDS; 5) total resistance at VDS = 0 V and VGS = Vdd and 6), effective channel length. Three fitted physical parameters are as follows: 1) carrier low-field effective mobility; 2) parasitic source/drain resistance, 3) the saturation region carrier velocity at the so-called virtual source. Lastly, a constrained saturation-transition-region empirical parameter is also fitted. The modeled current versus voltage characteristics and their derivatives are continuous from weak to strong inversion and from the linear to saturation regimes of operation. Remarkable agreement with published state-of-the-art planar short-channel strained devices is demonstrated using physically meaningful values of the fitted physical parameters. Moreover, the model allows for good physical insight in device performance properties, such as extraction of the VSV, which is a parameter of critical technological importance that allows for continued MOSFET performance scaling. The simplicity of the model and the fact that it only uses physically meaningful parameters provides an easy way for technology benchmarking and performance projection. [ABSTRACT FROM AUTHOR]

Self-Aligned Quadruple Patterning (SAQP) is used in advanced CMOS-FET technologies to enable the formation of arrays of fins at sub-40 nm pitches. As these technology nodes keep scaling down and the fins get taller for performance improvement, the patterns become denser and present very high aspect ratio (HAR). The scaling trends make the fin pattern more subject to mechanical instabilities during the processing steps. We describe in this paper a specific mechanical fin bending mode linked to the SAQP scheme targeting 24 nm pitch, the HAR and the formation and recess steps of the isolating oxide. We investigated the evolution of fin bending throughout the fin and isolation formation. We observed fins start bending at the FCVD deposition step exhibiting rotation angles up to 3 degrees. The bending was then worsened along the subsequent process steps causing mechanical failure after fin reveal where up to 7–8° of bending angles were observed. After having studied the influence of the key process steps, we can report a path to mitigate this phenomenon. Finally, we propose a simple mechanical analysis to validate quantitatively the root cause and extrapolate the mechanical robustness of this system for further scaling nodes where fin pitch is reduced. [ABSTRACT FROM AUTHOR]

Abstract: CMOS scaling entails various undesirable phenomena such as short-channel effect (SCE), parameter fluctuation, and tunneling leakage. To deal with these issues, various device structures are proposed. For better short channel behavior and performance enhancement, we have proposed and fabricated a few novel MOSFET structures. For further scaling of DRAMs, a capacitor less cell structure with a vertical channel and a surrounding gate is proposed and realized. The currently dominant poly-silicon floating gate structures suffer from several limitations, and flash memories based on silicon-oxide–nitride-oxide–silicon (SONOS) structures have emerged as a strong contender. For NAND application, an arch gate structure is proposed and fabricated. A vertical channel double-bit cell (DBC) structure is introduced to increase integration density. [Copyright &y& Elsevier]

Abstract: Basic trends in scaling CMOS technologies are reviewed briefly putting emphasis on advantages and limitations to designing readout ASIC. Scaling of noise performance in deep submicron MOSFETs is discussed in context of application in front-end circuits. A comparison of noise performance in deep submicron MOS transistors and in bipolar transistors is presented. Scaling of matching performance is reviewed and impacts on designing analogue circuits are discussed. Design challenges for mixed-signal ASICs related to analogue modelling, substrate coupling of digital noise, speed vs. power optimisation are reviewed briefly. Radiation effects in deep submicron CMOS technologies are reviewed and radiation hardening strategy towards Super LHC applications is discussed. [Copyright &y& Elsevier]

A state-of-the-art Monte Carlo simulator is applied to the investigation of the radio-frequency performance of bulk and ultrathin-body single-gate SOl MOSFETs that are designed according to the prescriptions of the 2005 ITRS for analog and mixed-signal applications. We provide an analysis of the signal-delay buildup along the channel and an investigation of the scaling properties of the parameters of the ac equivalent circuit, the transition frequency, and the 3-dB bandwidth of the voltage gain in common-source configuration. A comparison with a standard drift-diffusion approach is presented in order to discuss the main differences between the two transport models in terms of high-frequency ac analysis. [ABSTRACT FROM AUTHOR]

State-of-the-art device simulation is applied to the analysis of possible scaling strategies for the future CMOS technology, adopting the ultrathin silicon body (UTB) double-gate (DG) MOSFET and considering the main figures of merit (FOM) for the high-performance N-MOS transistor. The results of our analysis confirm the potentials of UTB-DG MOSFETs. In particular, the possibility to control the short-channel effects by thinning the silicon layer is fully exploited allowing to adopt almost undoped silicon channel, leading to reduced transversal field. As a consequence, the impact of surface roughness at the Si-oxide interface and the gate tunneling leakage current are substantially reduced compared to the case of highly doped bulk MOSFETs. According to our results, thanks to the suppression of gate leakage current, scaling of the UTB-DG MOSFET down to the 32 nm technology node appears possible adopting -based gate dielectrics. In spite of the improved mobility at given inversion charge density, the simulated on-currents are substantially lower than those required by the 2005 ITRS for the 45 and 32 nm nodes . Nonetheless, thanks to relaxed scaling of the oxide thickness, hence to reduced gate capacitance, the requirements in terms of intrinsic delay and power-delay product can be satisfied. The issue of variability is analyzed by evaluating the dependence of the key FOM on the variation of critical dimensions such as the thickness of the gate oxide and of the silicon layer. [ABSTRACT FROM PUBLISHER]

Abstract: We review and discuss the latest developments and technology options for 45nm node and below, with scaled planar bulk MOSFETs and MuGFETs as emerging devices. One of the main metal gate (MG) candidates for scaled CMOS technologies are fully silicided (FUSI) gates. In this work, by means of a selective and controlled poly etch-back integration process, dual work-function Ni-based FUSI/HfSiON CMOS circuits with record ring oscillator performance (high-VT) are reported (17ps at VDD=1.1V and 20pA/μm Ioff), meeting the ITRS 45nm node requirement for low-power (LP) CMOS. Compatibility of FUSI and other MG with known stress boosters like stressed CESL (contact-etch-stop-layer with high intrinsic stress) or embedded SiGe in the pMOS S/D regions is validated. To obtain MuGFET devices that are competitive, as compared to conventional planar bulk devices, and that meet the stringent drive and leakage current requirements for the 32nm node and beyond, higher channel mobilities are required. Results obtained by several strain engineering methods are presented here. [Copyright &y& Elsevier]

We address some of the plasma issues encountered for ultimate silicon gate patterning that should be fixed in order to establish the long term viability of plasma processes in integrated circuits manufacturing. For sub-100-nm gate dimensions, one of the main issues is to precisely control the shape of the etched feature. This requires a detailed knowledge of the various physico-chemical mechanisms involved in plasma etching and deposition. [Copyright &y& Elsevier]

Due to its low cost and flexibility for custom design, monolithic CMOS technology is being increasingly employed in charge preamplifiers across a broad range of applications, including both scientific research and commercial products. The associated detectors have capacitances ranging from a few tens of fF to several hundred pF. Applications call for pulse shaping from tens of ns to tens of μs, and constrain the available power per channel from tens of μW to tens of mW. At the same time a new technology generation, with changed device parameters, appears every 2 years or so. The optimum design of the front-end circuitry is examined taking into account submicron device characteristics, weak inversion operation, the reset system, and power supply scaling. Experimental results from recent prototypes will be presented. We will also discuss the evolution of preamplifier topologies and anticipated performance limits as CMOS technology scales down to the 0.1 μm/1.0 V generation in 2006. [Copyright &y& Elsevier]

A new architecture to multiply signals with time‐mode representations is proposed. The exponential relationship between voltage and time in an RC circuit is utilised to implement the time‐mode logarithmic and exponential functions needed to realise a time‐mode analogue of the translinear principle. The addition of time‐mode variables is achieved through the natural progression of time equal to the sum of the input times. By combining these two techniques, an analogue multiplier can be implemented almost exclusively with passive circuits and digital primitives. Therefore, the circuit performance could benefit from CMOS scaling trends. The architecture is described, and simulation results are presented for an operational circuit implementing this approach. [ABSTRACT FROM AUTHOR]