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This article presents a 1.2-V, 1.8-Gb/s/pin 16-Tb NAND flash memory multi-chip package incorporating 16 dies of 1-Tb NAND flash memory and the third-generation F-chip. The proposed third-generation F-chip is developed to meet the performance requirements of a high-capacity storage device that adopts a PCIe Gen four-host interface for higher data throughput. It is implemented with dual bi-directional transceiver architecture and signal retiming scheme to maximize the valid data window opening on solid-state drive (SSD) channels. Also, it facilitates training between F-chip and NAND using an on-chip delay-locked loop whose locking is proposed in strobe-based NAND systems to achieve sufficient signal integrity (SI) of the in-package channel at a speed of 1.8 Gb/s/pin. Embedded built-in self-test evaluates un-selected paths and determines if re-training is required without losing data throughput performance. This work achieves a 35% improvement in the I/O operational speed performance and a 23% reduction in the I/O power consumption in comparison with the previous generations.

The exponential data size growth in high-speed networks is a key motivator for nonvolatile memory development. To support this demand, higher density NAND is required: with a smaller cell size and higher interface speed. Generally, scaling down NAND technology requires addressing several common issues: 1) As the number of WL stack layers increases, the cell-string current is reduced due to the increased resistance in a cell string, 2) Deterioration of cell-to-cell interference, due to the reduction of cell pitch, 3) Support of higher IO bandwidth for faster data transfer speed [1]. Another challenge of this work was to minimize the die size because the peripheral circuit area is comparable to that of the cell array. Hence, we integrated the peripheral circuits below the cell array as introduced in [2]. Also, to cope with lower metal-contact height, a novel structure for the capacitor device was used to maximize capacitance per unit area.

A 1.2 V, 1.8 Gb/s/pin 16Tb-NAND flash memory multi-chip package incorporating with 16-dies of 1-Tb NAND flash memory and the 3rd generation F-Chip is proposed. The proposed F-Chip is developed to meet the performance requirements of high capacity storage devices that adopts PCIe Gen 4 host interface for faster data throughput. It is implemented with Toggle 4.0 standard on dual bi-directional transceiver architecture to achieve maximum valid data window on SSD channels. Also, it facilitates training between F-chip and NAND using on chip DLL and BIST to achieve sufficient signal integrity on in-package channel for 1.8Gb/s/pin. This work achieves a 35% improvement in the I/O operational speed performance and a 23% reduction in the I/O power consumption in comparison with the previous generations.

3D NAND flash memory has enhanced its areal density by more than 50% per year by virtue of the aggressive development of 3D WL stacking technology for the recent three consecutive years [1]–[3]. Also storage market still requires more bits for diverse digital applications. [4]

A 64-word-line-stacked 512-Gb 3-b/cell 3-D NAND flash memory is presented. After briefly examining the challenges that occur to a stack, several technologies are suggested to resolve the issues. For performance enhancement, a novel program method hiding two-page data loading time is presented. This paper also discusses an electrical annealing improving reliability characteristic by removing holes in shallow traps. In addition, a valley tracking read for reducing timing overhead at a read retry is introduced by fast finding optimal read levels. Finally, a high-speed self-test mode for IO operation is presented. The chip, designed with the fourth generation of V-NAND technology, achieved an areal density of 3.98 Gb/mm2 and operated up to 1 Gb/s at 1.2 V.

A 48 WL stacked 256-Gb V-NAND flash memory with a 3 b MLC technology is presented. Several vertical scale-down effects such as deteriorated WL loading and variations are discussed. To enhance performance, reverse read scheme and variable-pulse scheme are presented to cope with nonuniform WL characteristics. For improved performance, dual state machine architecture is proposed to achieve optimal timing for BL and WL, respectively. Also, to maintain robust IO driver strength against PVT variations, an embedded ZQ calibration technique with temperature compensation is introduced. The chip, fabricated in a third generation of V-NAND technology, achieved a density of 2.6 Gb/mm2 with 53.2 MB/s of program throughput.

Data storage is one of the hottest discussion topics in today’s connected world. The amount of data growth is expected to be exponential, while budget and space remain constricted. Since the transformation of storage device from planar NAND to 3D V-NAND [1], the areal density of semiconductor storage devices has continuously evolved and has surpassed the density of magnetic hard drives. By providing the largest storage capacity in the smallest footprint, 3D V-NAND has been leading the data center revolution in recent years. However, 3D-technology scaling faces several technical challenges [2]. (1) As the number of WL stacks increases the channel-hole etch process becomes a limit, since the total WL-mold height increases. (2) Interference between cells increases since the distance between WLs becomes smaller. (3) Faster data transfer speeds are required to support higher IO bandwidth.

Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as shorter tPROG, lower power consumption and higher endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, we succeed in developing 128 Gb 3b/cell Vertical NAND with 32 stack WL layers for the first time, which is the smallest 128 Gb NAND Flash. The die size is 68.9 mm $^{2}$ , program time is 700 us and I/O rate is 1 Gb/s.

Since the first demonstration of a production quality three-dimensional (3D) stacked-word-line NAND Flash memory [1], the 3b/cell 3D NAND Flash memory has seen areal density increases of more than 50% per year due to the aggressive development of 3D-wordline-stacking technology. This trend has been consistent for the last three consecutive years [2-4], however the storage market still requires higher density for diverse digital applications. A 4b/cell technology is one promising solution to increase bit density [5]. In this paper, we propose a 4b/cell 3D NAND Flash memory with a 12MB/s program throughput. The chip achieves a 5.63Gb/mm2 areal density, which is a 41.5% improvement as compared to a 3b/cell NAND Flash memory in the same 3D-NAND technology [4].

In the past few years, various 3D NAND Flash memories have been demonstrated, from device feasibility to chip implementation, to overcome scaling challenges in conventional planar NAND Flash [1-3]. The difficulties include shrinking the NAND cell and increasing manufacturing costs due to quadruple patterning and extreme ultraviolet lithography, motivating the development of the next-generation node beyond 16nm-class NAND Flash [4]. In this paper, as a new 3D memory device with lower manufacturing cost and superior device scalability, we present a true 3D 128Gb 2b/cell vertical-NAND (V-NAND) Flash. The chip accomplishes 50MB/s write throughput with 3K endurance for typical embedded applications such as mobile and personal computer. Also, extended endurance of 35K is achieved with 33MB/s of write throughput for data center and enterprise SSD applications.

A 1.2 V 1.33Gb/s/pin 8Tb NAND flash memory multi-chip package incorporating 16-die stacked 512-Gb NAND flash memories and F-Chip is presented. To meet the performance requirements of storage devices for higher capacity and faster data throughput, the 2nd generation F-Chip is developed. The F-Chip presents a dual bi-directional transceiver architecture including data retiming and training techniques to adaptively improve signal integrity. Besides, the F-Chip supports 1.2 V I/O for low power storage applications. This work, as a result, shows 33% improvement of eye-opening performances and 41% reduction of I/O power consumption compared to the previous generation.

The advent of emerging technologies such as cloud computing, big data, the internet of things and mobile computing is producing a tremendous amount of data. In the era of big data, storage devices with versatile characteristics are required for ultra-fast processing, higher capacity storage, lower cost, and lower power operation. SSDs employing 3D NAND are a promising to meet these requirements. Since the introduction of 3D NAND technology to marketplace in 2014 [1], the memory array size has nearly doubled every year [2,3]. To continue scaling 3D NAND array density, it is essential to scale down vertically to minimize total mold height. However, vertical scaling results in critical problems such as increasing WL capacitance and non-uniformity of stacked WLs due to variation in the channel hole diameter. To tackle these issues, this work proposes schemes for programming speed improvement and power reduction, and on-chip processing algorithms for error correction.

Today's explosive demand for data transfer is accelerating the development of non-volatile memory with even larger capacity and cheaper cost. Since the introduction of 3D technology in 2014 [1], V-NAND is believed to be a successful alternative to planar NAND and is quickly displacing planar NAND in the SSD market, due to its performance, reliability, and cost competitiveness. V-NAND has also eliminated the cell-to-cell interference problem by forming an atomic layer for charge trapping [2], which enables further technology scaling. However, the etching technology required for creating a channel hole cannot keep up with the market-driven WL stack requirement. Therefore, total mold height reduction is unavoidable and this creates several problems. 1) reduced mold height increases resistance and capacitance for WLs due to the thinner layers being used. 2) channel hole critical dimension (CD) variation becomes problematic because the additional mold stack height aggravates uniformity, thereby producing WL resistance variation. Consequently, read and program performance degradation is inevitable, furthermore their optimization becomes more challenging.

NAND flash memory is widely used as a cost-effective storage with high performance [1–2]. This paper presents a 128Gb multi-level cell (MLC) NAND flash memory with a 150 cells/string structure in 14nm CMOS that can be used as a cost-effective storage device. This paper also introduces several approaches to compensate for reliability and performance degradations caused by the 14nm transistors and the 150 cells/string structure. A technique was developed to suppress the background pattern dependency (BPD) by applying a low voltage to upper word lines (WLs) - the drain side(SSL side) WLs with respect to the location of the selected WL - during the verify sequence. Two techniques are also used to improve the program performance: equilibrium pulse scheme and smart start bias control scheme (SBC) in the MSB page. In addition, the first cycle recovery (FCR) of read enable (RE) and the bi-directional data strobe (DQS) is used to achieve a high speed I/O rate. As a result, a 640µs program time and a 800MB/s I/O rate is achieved.

Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die size to lower cost and to improve performance. However, the previously used node-shrinking methodology is facing challenges due to increased cell-to-cell interference and patterning difficulties caused by decreasing dimension. To overcome these limitations, 3D-stacking technology has been developed. As a result of long and focused research in 3D stacking technology, 128Gb 2b/cell device with 24 stack WL layers was announced in 2014 [1].

A 1.8-V 2-Gb NAND flash memory has been successfully developed on a 90-nm CMOS STI process technology, resulting in a 141-mm/sup 2/ die size and a 0.044-/spl mu/m/sup 2/ effective cell. For the higher level integration, critical layers are patterned with KrF photolithography. The device has three notable differences from previous generations. 1) The cells are organized in a single (16K+512) column and 128K row array by adopting a one-sided row decoder in order to minimize the die size. 2) The bitline precharge level is set to 0.9 V in order to increase on-cell current. 3) During the program operations, the string select line, which connects the NAND cell strings to the bitlines, is biased with sub-V/sub CC/ in order to avoid program disturbance issues.

A 1.8-V, 1-Gb NAND flash memory is fabricated with 0.12-/spl mu/m CMOS STI process technology. For higher integration, a 32-cell NAND structure, which enables row decoder layout in one block pitch, is applied for the first time. Resulting cell and die sizes are 0.076 /spl mu/m/sup 2/ and 129.6 mm/sup 2/, respectively. A pseudo-4-phase charge pump circuit can generate up to 20 V even under the supply voltage of 1.6 V. A newly applied cache program function and expanded page size of (2 k + 64) byte lead to program throughput of 7 MB/s. The page copy-back function is provided for on-chip garbage collection. The read throughput of 27 MB/s is achieved by simply expanding I/O width and page size. A measured disturbance free-window of 3.5 V at 1.5 V-V/sub DD/ is obtained.

In this paper, the mechanism of write disturbance, a unique phenomenon in high density ReRAM, is experimentally identified and quantified using fabricated test array. Based on the analysis, disturbance-suppressed ReRAM write algorithm is proposed to prove the feasibility of future high-capacity and high-performance ReRAM memory for NAND applications. By appropriately controlling WL and BL bias, surge current that causes write disturbance is successfully suppressed so that the overall cell distribution was narrowed down by more than 70%.

In this work, we present a 3D 128Gb 2bit/cell vertical-AND (V-NAND) Flash product. The use of barrier-engineered materials and gate all-around structure in the 3D V-NAND cell exhibits advantages over 1xnm planar NAND, such as small Vth shift due to small cell coupling and narrow natural Vth distribution. Also, a negative counter-pulse scheme realizes a tightly programmed cell distribution. In order to reduce the effect of a large WL coupling, a glitch-canceling discharge scheme and a pre-offset control scheme is implemented. Furthermore, an external high-voltage supply scheme along with the proper protection scheme for a high-voltage failure is used to achieve low power consumption. The chip accomplishes 50MB/s write throughput with 3K endurance for typical embedded applications. Also, extended endurance of 35K is achieved with 36MB/s of write throughput for data center and enterprise SSD applications. And 2nd generation of 3D V-NAND opens up a whole new world at SSD endurance, density and battery life for portables.

The separated shorted-anode LIGBT (SSA-LIGBT), which suppresses effectively the negative differential resistance regime, is investigated by performing 2-dimensional numerical simulation. In order to suppress the negative differential resistance regime, the SSA-LIGBT increases the pinch resistance by employing the highly resistive n-drift region as an electron conduction path instead of the lowly resistive n buffer region of the conventional SA-LIGBT. The SSA-LIGBT shows the remarkably decreased forward voltage drop when compared with the conventional SA-LIGBT and shows the one-order faster turn-off time than that of the LIGBT.

A new dual-gate shorted-anode SOI (silicon-on-insulator) LIGBT (lateral insulated gate bipolar transistor), which suppresses the snapback effectively with gates signal of the same polarity, is proposed and verified by numerical simulation. The suppression of the snapback in I–V characteristics is obtained by initiating the hole injection by employing the dual gate and FOC (floating ohmic contact) in the new device. The proposed device eliminates the snapback completely and has a low forward voltage drop compared with conventional SA-LIGBT (shorted anode lateral insulated gate bipolar transistor). Snapback of SA-LIGBT occurs at anode voltage 11 V, but in case of the proposed device, the snapback phenomenon is completely eliminated. Also, by employing the FOC, the drive signals of two gates are of an identical polarity. Therefore the proposed device requires no additional power supply, which is a necessity for driving conventional dual-gate SA-LIGBT.

A vertical Insulated Gate Bipolar Transistor, entitled CB-IGBT(Carrier-inducing Barrier-controlled IGBT) has been proposed and verified by a two-dimensional numerical simulation. The structure of the proposed device is almost identical with that of the conventional IGBT, except for the anode structure in which the p-barrier region and n+ anode region are employed. In the CB-IGBT, the potential barrier height at the junction between the p-barrier region and n-drift region is controlled by the amount of carriers, so that the trade-off relation between the on-state voltage drop and the switching speed is decoupled efficiently. The switching speed of CB-IGBT is so much enhanced with a negligible increase of the on-state voltage drop, since electrons stored in the n-drift region can be extracted rapidly into the n+ anode via p-barrier region during turn-off process.

Analysis of the breakdown voltage in the p+n junction with the field plate is presented for an optimum design. The breakdown voltage is analyzed by employing the approximated electric field and breakdown path in terms of the field plate parameters and the applied reverse bias. The optimum values for oxide thickness and the field plate width are derived by the use of the breakdown voltage. The calculated breakdown voltages agree well with the experimental data and two-dimensional numerical simulation result.

We propose and fabricate a new base resistance-controlled thyristor (BKT) employing a self-aligned corrugated p-base. The new device, entitled CB-BRT, suppresses the snap-back effectively and increases the maximum controllable current. Experimental results show that the snap-back of the CB-BRT is reduced significantly when compared with that of the conventional BRT. Also, the maximum controllable current of the CB-BRT increases as compared with the conventional BRT.

A new shorted-anode lateral insulated gate bipolar transistor (SA-LIGBT), entitled gradual hole injection dual gate LIGBT (GHI-LIGBT), is proposed and fabricated. The new device employs a dual gate and p/sup +/ injector in order to initiate the hole injection gradually from the anode electrode into the drift region so that the negative differential resistance (NDR) regime may be eliminated. The experimental results show that the NDR regime, which may cause undesirable device characteristics, is completely eliminated in the GHI-LIGBT, and the forward voltage drop is reduced by 1 V at the current density of 200 A/cm/sup 2/ in comparison with the conventional SA-LIGBT.

This paper compares design concepts of 63nm-8Gb and 90nm-4Gb multilevel cell (MLC) NAND flash memory. For 8Gb MLC NAND flash memory, locations of peripheral circuits and charge pumps are determined to optimize area and signal speed. Page buffer is simplified by reducing the number of transistors with minimal connections thereby resulting in smaller size. Performance is improved by using fast-read/write cycle and reduced signal paths. Furthermore, two-MAT-cell-array architecture is used for 2times read/write operations. Various techniques are used to suppress noisy effects such as common source line (CSL) noise and floating-gate-coupling noise

An 8 Gb multi-level NAND flash memory is fabricated in a 63 nm CMOS technology with shallow trench isolation. The cell and chip sizes are 0.02 /spl mu/m/sup 2/ and 133 mm/sup 2/, respectively. Performance improves to 4.4 MB/s by using the 2/spl times/ program mode and by decreasing the cycle time from 50 ns to 30 ns. This also improves the read throughput to 23 MB/s.

A 1.8 V 1 Gb flash memory uses a 0.12 /spl mu/m STI process technology. A charge pump operates at

A 4 Gb NAND flash memory with 2 b/cell uses 90 nm CMOS to achieve simultaneous data load during program operation with 1.6 MB/s program throughput. Fuse or pad-bonding switches it to a 2 Gb 1 b/cell NAND flash memory. The row decoder located in the middle of the cell array reduces W/L rise time and coupling noise. A program-after-erase technique and lowered floating poly thickness minimize cell Vth distribution.

A 1.8 V 2 Gb NAND flash memory is fabricated in a 90 nm process resulting in a 141 mm/sup 2/ die and a 0.044 /spl mu/m/sup 2/ effective cell. To achieve the high level of integration, critical layers are patterned with KF photolithography and phase-shift masks with proximity correction.