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This paper discusses the mixed-signal circuit design in a novel monolithic (sequential) 3D process. The goal of this work is to explore a novel multi-process sequential 3D technology with the state-of-art 3D interconnections density of 2 × 107 via/mm2 and we report our first impressions. The paper discusses the design of a 3-bit SAR and a 3-bit Flash ADCs, where we have partitioned digital and analog parts in a new under test shrink 65nm technology stacked over a 28nm FDSOI process. The 3D connection density of the applied process is almost on par with the horizontal connection densities within a tier. This fact will enable what we refer to as ‘Systems-in-Cube’ (SinC), i.e. fine-grained volume implementations where individual transistor of small functional blocks can be distributed across 3D tiers. We estimate an area reduction of about 40% compared to a pure 2D 28nm realization of the same circuits and 80% compared to an equivalent 2D 65nm implementation for a ‘balanced’ mixed signal design. Moreover, we also estimate that this would result in an overall price reduction for these circuits in a mature commercial sequential 3D process.

The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performance.

International audience; We fabricated and characterized 14nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078µm² Static Random Access Memory (SRAM) cells. Temporal and spatial variability as well as sensibility to temperature, supply voltage (VDD) and back bias (Vwell) are extracted. These data evidence that the 14nm SRAM is read-limited, which could be improved by a smart back-bias management [1]. In this work we demonstrate a 50mV Static Noise Margin (SNM) variability improvement (at VDD=0.8V) by back-biasing, without additional Bias Temperature Instability (BTI) stress. Such an assist technique can be eventually leveraged at fine-grain by 3D monolithic integration, owing to local back-planes.

For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty as well as the capability to route two additional row-wise signals on individual back-planes. Experimental data are extracted from a 14nm planar Fully-Depleted-Silicon-on-Insulator (FDSOI) $0.078\mu \mathrm{m}^{2}$ SRAM in order to properly model 3D top-tier cells. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/16% read/write access time improvement at $V_{DD}=0.8\mathrm{V}$ and a reduction of minimum operating voltage $V_{min}$ by 60mV at $6\sigma$ w.r.t. planar SRAMs.

Design of 3D ICs is mainly done in separated design environments for each tier, assuming that communication channels between tiers are user-defined and fixed at the beginning of the design process. Suitable for 3D stacking based on TSV or Hybrid Bonding technologies because of low granularity of these 3D interconnect elements, this methodology becomes less effective for 3D sequential technologies once trying to integrate Monolithic Inter-tier Vias (MIVs) with higher density (around 1.108 vias per mm2). In this paper, we describe a methodology to create a unified design environment for 3D sequential technology by merging Process Design Kits (PDKs) of different technologies attached to different tiers. Main advantage of this methodology is that designing a 3D circuit may no more require several design environments, thus simplifying simulations, verifications and layout finishing. As a proof of concept, we designed and taped-out a RISC-V processor with logic on memory architecture using LETI CoolCube 28nm FDSOI on top of ST 28nm FDSOI technology.

For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty, as well as the capability to route two additional row-wise signals on individual back planes. Experimental data are extracted from a 14 nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078 µm2 SRAM cell in order to properly model 3D top-tier cells. BTI measurements are done to ensure that the proposed assist do not provide additional stress. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/50% read/write access time improvement at VDD = 0.8 V and a reduction of minimum operating voltage Vmin by 60 mV (up to 92 mV with speed penalty) at 6σ w.r.t. planar SRAMs.

We propose an original Technology/Design Co-optimization of standard cells mixing devices of different threshold voltages (V T -flavors) within a cell. It is successfully applied with nMOS Low-V T (LVT) and pMOS Super-Low-V T (SLVT) in Ultra-Low-Voltage (ULV) Fully Depleted Silicon-On-Insulator (FDSOI) LETI standard cells using diffusion breaks. It enables adjusting the V T of pMOS subject to SiGe-channel-induced Local Layout Effect (LLE); leading experimentally to a 23% frequency gain on 22nm FDSOI technology for a 2-finger inverter Ring Oscillator (IVSX2 RO) vs. reference LVT at the same static leakage and V DD =0.4V supply voltage; which corresponds to the Minimum Energy Point (MEP). This solution is combined with Forward Body Biasing (FBB), which brings +253% frequency at V DD =0.4V and FBB=1.6V and improves the energy efficiency with a −13% minimum Energy Delay Product (EDP) along with a 50mV V DD reduction at the minimum EDP.

We have fabricated 3D-monolithic transistors on two tiers. We experimentally evidence the asymmetric double-gate (DG) behavior of a top-tier transistor, resulting in a better ON-state current (Ion) / OFF-state current (I off ) tradeoff than in single-gate (SG) mode. Moreover, a 3D-shared contact between a top and bottom electrode is experimentally demonstrated; paving the way for a local back gate, possibly connected with the top gate by a 3D-shared contact. Assuming such a construct, we have performed extensive layout and spice simulations of standard cells and SRAMs. We evidence that the back-gate overlap on the source and drain must be minimized to mitigate the parasitic capacitances. The best layout configurations of a loaded 1-finger inverter yields a 24% frequency gain at a given static power and V dd = 0.6V supply voltage, compared to SG, or to a static power divided by 5, compared to SG under Forward Body Bias (FBB). These performance boosts may be obtained without any area penalty and assuming a 20nm-thin BOX. Similarly, a 29% improvement of the read and write currents of 6T SRAMs is contemplated at V dd = 0.8V. Such new functionality provided by 3D-monolithic even enables making 4T SRAMs that are fully functional at V dd = 0.8V by improving their retention and, in turn, the maximum number of bitcells per column from 50 (SG) to 300 with a dynamic back-bias.

This study focuses on temperature deviation during operation of transistors inside a monolithic 3D standard cell built on two tiers. Early assessment of this topic is crucial to manage circuit design and requires both steady-state and transient thermal analysis at transistor level. A representative 3D standard cell in 14nm FDSOI technology is considered, using intermediate Back-End-Of-Line (iBEOL) and top tier BEOL. Steady-state and transient power dissipations in NMOS and PMOS are extracted from SPICE simulations with variables such as output load capacitance and operating temperature. 3D thermal simulations are then performed to assess the impact of design parameters such as routing densities, thicknesses of iBEOL and BEOL, their number of metal layers and packaging techniques. Steady-state and transient thermal simulations enable precise analysis to correlate temperature deviation of transistors with these parameters. Design guidelines are provided to limit the temperature deviation between top and bottom tier which can reach 7°Celsius during circuit operations in the worst case

Stacking N over CMOS devices using 3D Sequential CoolCube™ Integration has been shown promising for the scaling of 6T SRAMs. By transposing one pass-gate and one pull-down NMOS to the top layer, a cell footprint reduction of 27% could be obtained, leading to a 3D vias density over 108/mm2 achievable. In addition, we presented N-type devices fabricated below 630°C yielding quasi-equivalent performances as high temperature ones while fulfilling the PBTI and hot-carrier effects reliability requirements, comforting the viability of N over CMOS approach.

3D sequential integration known as Monolithic 3D (M3D) is considered as an alternative solution to CMOS scaling [1]. In this paper, we detail an innovative methodology migrating a 2D Process Design Kit (PDK) and its associated standard cells libraries to a M3D CoolCube™ design platform [2]. This methodology exhibits a significant migration runtime reduction almost regardless of the number of design rules and standard cells layout complexity (multi-patterning) in advanced CMOS nodes. This migration allows gate level evaluation through a Power Performance Area (PPA) analysis and is based on the following assumptions and targets: 1) same mask sequence and model cards on both level 2) identical process node, design rules and parameters on both levels 3) cell on cell approach.

In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.

3D VLSI with a CoolCube™ monolithic integration flow allows vertically stacking several layers of devices with a unique connecting via density above tens of million/mm2. This results in increased devices density and gains in power and performance thanks to wire-length reduction without the extra cost associated to transistor scaling. In addition to power saving, this true 3D integration opens perspectives in terms of heterogeneous integration. We will review the opportunities brought by CoolCube™ and will present the most advanced technological demonstration of 3D CMOS over CMOS CoolCube™ integration.

While the 3D sequential process is still under development, the electrical influence of specific process for the bottom tier needs to be studied. As another MOS transistor layer is fabricated on top of the bottom one, contamination risk and thermal stability issues appear, thus requiring adaptation of conductors/dielectrics for intermediate Back-End Of Line (iBEOL) processing. As materials differ from usual copper/low-k, it is necessary to study how standard cells electrical characteristics will be affected. We modeled different descriptions of iBEOL in 14nm FDSOI process and simulated standard cells characteristics. The average power consumption is almost the same while large cells with high drive timing degradation can be up to 20% in the worst case. This sensitivity analysis allowed us to identify which parameters (permittivity, resistivity) have the greatest impact depending on standard cell type and provide technology and design guidelines. Our goal here was to limit the performance degradation to around 5% maximum for the bottom tier standard cells.

This work highlights recent advances in 3D VLSI integration. A review of low temperature process modules development such as junctions, spacers and salicidation is presented. Finally, for the first time, a full CMOS over CMOS 3D VLSI integration on 300mm wafers is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain.

While Resistive RAM (RRAM) are seen as an alternative to NAND Flash, their variability and cycling understanding remain a major roadblock. Extensive characterizations of multi-kbits RRAM arrays during Forming, Set, Reset and cycling operations are presented allowing the quantification of the intrinsic variability factors. As a result, the fundamental variability limits of filament-based RRAM in the full resistance range are identified.

This paper aims at identifying the critical parameters for intermediate back end of line (BEOL) in 3DVLSI in order to benefit from higher circuit gain in performance. Thanks to circuit simulations in a 3D environment PDK, the capacitance is identified as the most critical parameter for IC performance of circuits using two intermetal levels. The critical wirelength upon which a gain in performance is obtained by the 3D stacking is evaluated as a function of BEOL flavor.

session 5: 3D Systems and Packaging; International audience; 3D VLSI with a CoolCube™ integration allows vertically stacking several layers of devices with a unique connecting via density above a million/mm 2 . This results in increased density with no extra cost associated to transistor scaling, while benefiting from gains in power and performance thanks to wire-length reduction. CoolCube™ technology leads to high performance top transistors with Thermal Budgets (TB) compatible with bottom MOSFET integrity. Key enablers are the dopant activation by Solid Phase Epitaxy (SPE) or nanosecond laser anneal, low temperature epitaxy, low k spacers and direct bonding. New data on the maximal TB bottom MOSFET can withstand (with high temperatures but short durations) offer new opportunities for top MOSFET process optimization.

Design of conventional 2D integrated circuits is becoming more and more challenging as we strive to keep on following Moore's law. Cost, thermal behavior, multiple patterning, increasing number of design rules, transistor characteristics, variability and back end properties coupled with a constant need for a higher integration of functions / peripherals are creating an increasingly complex equation to solve for designers. Moving to the next node and taking advantage of the technology are now far from being straightforward as time to market has never been so short for industry. In order to overcome or at least postpone the time when we'll have to face the "next node migration constraints", a possible solution could be staying at the same node and go 3D with possible benefits such as wire length reduction, power savings and increased operating frequency. Since more than ten years now, interconnect technologies like Through Silicon Via (TSV), High Density (HD)-TSV and Copper to Copper (Cu-Cu) have arisen to take advantage of this possible 3-dimensional physical implementation with proofs of concept [1] or more recently industrial products [2]. Main drawback of these technologies is that they are not shrinking at the same speed as transistors are, making them somehow power hungry; moreover the more they will shrink, the more precision will be needed for chip to chip alignment. To reach the highest possible standard cell and tier to tier interconnect densities required for cost-effective chips, 3D sequential integration process [3][4][5] (also known as Monolithic 3D or CoolCubeTM) is currently developed with main features being sequential fabrication of MOS layers and correlation of tier to tier interconnect size with process node allowing fine-grain 3D partitioning of designs. These particularities make it a durable opportunity to slow down next node design migration while still improving integration. To fully benefit from CoolCubeTM technology, a whole new way of designing circuits, from synthesis to place and route, will be required as some new challenges will arise. The point of this presentation is to show the possible use and limitations of the aforementioned technologies with a focus on Monolithic 3D and to give some insights about market expectations, challenges and available design techniques.

Monolithic or sequential 3D Integration is a powerful technological enabler for actual 3D IC design as the stacked layers can be connected at the transistor scale. This paper reviews the opportunities brought by M3DI and highlights the applications benefiting from this small 3D contact pitch. It also presents the technological challenges of this concept and offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.

Physical verification of an integrated circuit is a crucial step before manufacturing. In order to ensure the correctness of a design regarding the whole process flow, Design Rule Checking (DRC) is mandatory. As transistor size is reduced, the number of design rules to check increases exponentially. The increasing number of metal layers and heterogeneous integration possibilities are generating rules duplication, thus leading to a significant risk of mistakes, therefore being a relevant parameter to consider. This paper presents a new approach to write design rules using a high-level description language, offering noticeable modularity and reusability, available through a generic Design Rule Library (DRL) concept. This methodology fastens and simplifies DRC rules file writing by allowing substantial reduction of the number of lines to be hand written.

Compared with TSV-based 3D ICs, monolithic or sequential 3D ICs presnts “true” benefits of going to the vertical dimension as the stacked layers can be connected at the transistor scale. The high versatility of this technology is evidenced via several examples requiring small 3D contact pitch. Monolithic 3D is shown to enable substantial gain in area and performance as compared to planar technology without scaling the transistor technology node. This paper summarizes the technological challenges of this concept: it offers a general overview of the potential solutions to obtain a high performance low temperature top transistor while keeping bottom MOSFET integrity.

3D integration provides different technological approaches as new opportunities for design and architecture alternatives. Circuit integration can now be achieved by using various interconnection concepts such as Through Silicon Vias (TSV last), ReDistribution Layer (RDL), pillars, bumps and micro-bumps. The key challenge from the design kit point of view is now to make all these concepts accessible and easy to use for 3D IC design benchmarking, leading to a generic 3D platform offering various interconnection options for the end-user with on-demand customization of the 3D layout environment. The first section of this paper will give an overview of the LETI 3D technological offer through the Open 3D™ platform and present the context in terms of Process Design Kit (PDK) development. Second section will describe the approach and the proposed solution through a configurable PDK, a PDK generator software and the associated user-friendly interface. Finally, last section will focus on the 3D layout environment and methodology used to design a 3D demonstrator with some examples.

This paper presents the prototype of a 3D circuit in which a Wafer Level Packaged CMOS image sensor is vertically assembled with an image signal processor in a face-to-back integration scheme. The design flow used to hybrydize the two circuits will be fully described, up to physical implementation. The process technology carried out will be presented in a 200 mm environment. Finally, the 3D assembly will be successfully assessed, concretising the realism of a 3D technology for nomadic imaging systems.

Similar to transistors, the size of MEMS components is continuously shrinking, progressing from MicroElectroMechanical Systems to NanoElectroMechanical Systems (NEMS). Indeed, NEMS are emerging as a new field of interest because their submicron dimensions make them converge towards CMOS fabrication processes. They have specific advantages such as fast response time and high detection sensitivity when used as a resonant sensor [1]. From the application point of view, NEMS interact “naturally” with the nanoscale world and can sense unprecedented physical and biological phenomena, such as the mass of a single molecule, the force exerted by living cells or certain biochemical reactions. In the next five to ten years, NEMS should offer a real breakthrough for mass spectrometry or gas analysis applications because they can achieve similar resolution to conventional lab equipment but at a lower cost due to their compatibly with VLSI processes.

This paper reports on ultra-scaled single-crystal Si NEMS resonators (25–40nm thick) operating in the 10–100MHz frequency range. Their first monolithic integration at the front-end level with CMOS enables to extract the signal from background leading to possible implementation of direct/homodyne measurement, for high sensitivity sensing applications and portable systems.

Recent device developments and achievements have demonstrated that planar undoped channel Fully depleted SOI devices are becoming a serious alternative to Bulk technologies for 20nm node and below. We have proven this planar option to be easier to integrate than the non planar devices like FinFET. This paper gives an overview of the main advantages provided by this technology, as well as the key challenges that need to be addressed. Electrostatic integrity, drivability, within wafer variability and scalability are addressed through silicon data (down to 18nm gate length) and TCAD analyses. Solutions to the Multiple V T challenges and non logic devices (ESD, I/Os) are also reported.

We fabricated CMOS devices on Ultra-Thin Boby and Buried Oxide SOI wafers using a single mid-gap gate stack. Excellent global, local and intrinsic V T -variability performances are obtained (A VT =1.45mV.µm). This leads to 6T-SRAM cells with good characteristics down to V DD =0.5V supply voltage and with excellent Static Noise Margin (SNM) dispersion across the wafer (σ SNM DD =0.7V. We also demonstrate ultra-low leakage ( G = 30nm by source/back biasing thanks to a low gate current and Gate Induced Drain Lowering (GIDL).

The inefficiency of 5-methyl-7-hydroxy-1, 3, 4-triazaindolizine (Aza) os an antifoggant in a developer is caused by the desorption of Aza from the development centres by developing agents and bromide and is also influenced by the sulphite concentration and the pH of the bath. Nitrobenzimidazole (Nitro) is not desorbed completely under the same conditions. The adsorption on the specks measured with C14-labelled Aza, Nitro and benzimidazole, is not only influenced by the solubility product of the silver salts but also by other factors such as gelatin concentration and by the value of the acid dissociation constant. So with increasing pH the adsorption of Aza on the active centres diminishes and the adsorption of Nitro increases. In addition the Aza is in competition with the gelatin for the adsorption on the grains. The adsorption of Aza on the grains reduces the amount of adsorbed gelatin and this may cause the increase in sensitivity by Aza. Our results indicate on adsorption of hydroquinone on th...