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The correlation between the nanocrystal (NC) stored charge and cell programming (P) window was explored to study the relation between the NC density, dimension, and position and the cell [V.sub.T] variation. The results obtained from the 2-D TCAD simulations for the causes of the differences of NCM cells demonstrated that the difference is due to the localization of the charge into the NCs.

An effective 2-D self-consistent solution of Schrodinger-Poisson (SP) within the effective mass approximation was used to gain insight into the capacitance-voltage [C([V.sub.g])] features of cylindrical gate-all-around n- and p-channel Si nanowire MOS structures. The studies related to the density-of-states features of the Si channel from the capacitance-voltage characteristics at room temperature measurements are also presented.

The physics of autonomous refresh which demonstrated the mechanism of a spontaneous recovery of degraded binary states of the floating-body cell (FBC) is presented. The experiments with charge pumping current as output revealed that the autonomous refresh is possible on a single-cell basis.

An analytic model for undoped symmetric double-gate MOSFETs with small gate-oxide-thickness asymmetry by virtue of a perturbation approach is presented. The accurate analytic solution provided by the model could be used in compact models for digital and analog IC designs.

A comprehensive model to analyze the three-dimensional (3-D) source-drain (S/D) resistance of undoped double-gated FinFETs of wide and narrow S/D width is presented. The model could also be used to analyze the benefits and limitations of siliciding schemes to reduce the series resistance in FinFETs.

A study was conducted to analyze the influence of direct source-to-drain tunneling (DSDT) on dopant-segregated Schottky (DSS) source/drain double-gate MOSFET design. Findings suggest that the physical gate length can be scaled below three nm with little DSDT-induced performance degradation; the lower limit for source-to-drain contact spacing is projected to be approximately 11 nm.

A study was conducted to examine the program and retention transients of silicon nitride-based (SONOS/TANOS) nonvolatile memories using a new characterization technique and an improved model for charge injection and transport through ONO gate stacks. Results reveal that the carrier transport in the SiN layer affects the spatial distribution of the trapped charge and various aspects of program and retention transients.

A self-consistent and 3-dimensional (3-D) quantum simulator is described for Si-nanowire transistors based on the Wigner function model and multidimensional Schrodinger-Poisson algorithm. The studies have shown that the source-drain tunneling is a major phenomenon related to a scaling limit of nanowire devices, and the semiclassical simulation has measurably underestimated a minimum gate length.

The effects of top-cut stress liners for damascene gate MOSFETs are examined by stress simulation. The results have shown that high channel stress is induced for shorter gate lengths and hence high drive current n- and pFETs are achieved by using top-cut stress liners with dual metal/high-k gates and eSiGe for damascene gate devices.

The strain effect on electron and hole transport in -oriented FinFETs is studied. The hole mobility is enhanced while the electron mobility is reduced toward short-channel devices, which is attributed to the gate-length-dependent strain in FinFET device structures.

A new dual-material-gate-trench power MOSFET is described that has displayed improvement in its transconductance and breakdown voltage without any degradation in on-resistance. The improvement in peak transconductance and breakdown voltage is achieved in the new device when compared to the conventional trench MOSFET by using [N.sup.+] poly-Si as a lower gate material and [P.sup.+] poly-Si as an upper gate material.

The experimental ballistic ratio, injection velocity and carrier mean-free path evolutions with the transistor gate length, the inversion charge and the temperature are examined in n- and p-FDSOI devices. The evaluation of the device mean-free path and its evolution with both the inversion charge in the channel and the temperature is used for examining the mobility degradation with decreasing gate lengths, signifying the importance of Coulomb scattering on the mobility behavior.

A study is conducted to optimize the performance of the epitaxial structure of 130-nm gate-length InGaAs/InAlAs/InP high electron mobility transistors (HEMTs), under biased low-noise conditions. The results revealed that In is more critical to achieve optimization in the InP HEMT for high-frequency applications when compared to low noise.

The soft breakdown modes for hafnium oxynitride (HfON) gate dielectrics under stress are investigated. Large Joule heat damage generated under stress inducing the analog soft breakdown for thick hafnium oxynitride films is used to understand the breakdown of HfON gate dielectrics.

A capacitorless, asymmetric double gate DRAM (DG-DRAM) technology is developed. The problems in the dopant fluctuation effects and off-state leakage are reduced due to the thin body structure of its double gate.

The physical meaning of threshold voltage in organic field-effect transistors (OFETs) is understood by studying the threshold voltage dependence on gate-insulator thickness as well as active-layer thickness by using pentacene OFETs with and without a dipole interlayer between pentacene active layer and Si[O.sub.2] gate insulator. The model has accounted for both the large negative threshold voltage shift and the linear relation, which has disclosed the importance of interfacial electric field for studying organic devices.

The bias stressing voltage dependence of the negative bias temperature instability (NBTI) in p-channel field effect transistors with nominal SiON/HfSiON gate stacks is analyzed. Slow and slow plus fast trap values are very different and have shown that a unique set of A and [alpha] values cannot be used for describing all the traps, thus raising concerns about protocols used with NBTI data to determine the reliability lifetime.

The chemical composition of the surface protrusions is studied by using various analysis methods, which has shown that it consists of oxidized Si. Local electrical stress in gate dielectrics using conductive atomic force microscopy (C-AFM) has induced structural damage in the layers and a mechanism is proposed for explaining the correlation between the surface damage and the measured current during constant voltage stress.

A study of the Toffoli-Fredkin (TF) gate, a universal reversible logic gate capable of performing logic operations without dissipating energy is presented. The dynamics of the TF gate is realized by selectively driving spin resonances in the coupled spin system with an ac magnetic field.