Search

Cryptic invasions are difficult to distinguish and easily overlooked by conventional identification methods, creating false biodiversity information. Molecular markers represent the only reliable method to distinguish cryptic species to date but require individual tissue samples, which is time-inefficient and difficult during low abundance or early colonization. Newly developed Environmental DNA (eDNA) methods may provide a solution. We compared conventional methods (morphological, physicochemical) and molecular methods (DNA and eDNA) to distinguish two putative species of Pomacea, with the aim to develop an early taxon-specific detection method for effective invasive species management. Novel eDNA methods were assessed in semi-natural (mesocosm) and natural waterbodies across Taiwan for species identification. Morphological characters and physicochemical analysis of P. canaliculata and P. maculata shells demonstrated overlapping qualitative and quantitative measures, which were unable to differentiate species. However, DNA-based barcoding (COI gene) differentiated P. canaliculata, and P. maculata and revealed their distribution. Our eDNA analysis demonstrated overall detection rate of P. canaliculata was significantly higher than P. maculata. Importantly, we detected the active presence of P. maculata in Taiwan, although further studies investigation needed to differentiate pure and hybrids individuals. This pioneering eDNA study quickly and effectively detected P. canaliculata and P. maculata, which could revolutionize tracking two immensely invasive and economically destructive species.

Lutein (β,ε-carotene-3,3′-diol), a xanthophyll carotenoid, is found in high concentrations in the macula of the human retina. It has been recognized to exert potential effectiveness in antioxidative and anti-inflammatory properties. However, whether and how its modifications on varying types of plasmalemmal ionic currents occur in electrically excitable cells remain incompletely answered. The current hypothesis is that lutein produces any direct adjustments on ionic currents (e.g., hyperpolarization-activated cation current, Ih [or funny current, If]). In the present study, GH3-cell exposure to lutein resulted in a time-, state- and concentration-dependent reduction in Ih amplitude with an IC50 value of 4.1 μM. There was a hyperpolarizing shift along the voltage axis in the steady-state activation curve of Ih in the presence of this compound, despite being void of changes in the gating charge of the curve. Under continued exposure to lutein (3 μM), further addition of oxaliplatin (10 μM) or ivabradine (3 μM) could be effective at either reversing or further decreasing lutein-induced suppression of hyperpolarization-evoked Ih, respectively. The voltage-dependent anti-clockwise hysteresis of Ih responding to long-lasting inverted isosceles-triangular ramp concentration-dependently became diminished by adding this compound. However, the addition of 10 μM lutein caused a mild but significant suppression in the amplitude of erg-mediated or A-type K+ currents. Under current-clamp potential recordings, the sag potential evoked by long-lasting hyperpolarizing current stimulus was reduced under cell exposure to lutein. Altogether, findings from the current observations enabled us to reflect that during cell exposure to lutein used at pharmacologically achievable concentrations, lutein-perturbed inhibition of Ih would be an ionic mechanism underlying its changes in membrane excitability.

Collaborative design provides a strategic and operational means for the achievement of organisational competitiveness. The information technology (IT) industry in Taiwan can be seen as a progressive industry with some ongoing important developments. The main objective of this research is to study the impact of collaborative design on new product development by B2B e-commerce project in IT industry. A cross-case analysis of the themes relating to the research purpose was conducted. The insight of these questions is generated through multiple case studies. The cross-case analysis was adopted coding for patterns and relationships among the data using a qualitative analysis software tool –Nvivo. The results present the key factors in term of collaboration issues by e-supply chain integration perspective. Such findings underscore the importance of recognising collaborative design on new product development.

The impact of adjacent word-line's pass gate voltage interference on charge-trapping (CT) NAND Flash is extensively studied in this paper. From our previous work with a 38-nm half-pitch BE-SONOS NAND Flash device, we found that the threshold voltage significantly decreases with increasing pass gate voltage during reading. This observation is in contrary to the common belief that the CT NAND devices are immune to interference. In this paper, we further evaluate the pass gate voltage interference on 3-D CT NAND Flash, which is the most promising path for the future NAND Flash industry. Owing to the superior gate control ability in the double-gate architecture, the commonly observed pass gate voltage interference due to pitch scaling is suppressed. Stronger gate control ability also restrains the impact of field penetration in devices with narrow channel width. In 3-D CT NAND Flash, the thinner channel can also provide better gate control ability, which, in turn, results in smaller pass gate voltage interference.

3D NAND is usually designed with the charge-trapping (CT) device, arranged in a “junction-free” structure where the transistors are serially connected without a N+ diffusion junction in between them. This paper provides a physics-based quasi-2D model and several analytical equations that can readily simulate the surface potential variation inside the junction-free 3d NAND. It is clarified that the operation of junction-free 3D NAND is dominated by the continuity of surface potential derived by the Poisson equation. The neighbor WL pass-gate voltage (Vpass) and Vt interference effects are both the outcome of surface potential continuity that results in the “non-local” behavior of surface potential that can be affected be the neighbor and even far neighbor cells. It is not caused by the fringe field effect or capacitive coupling. From our simulation, the WL interference effect can be suppressed by using the extreme-thin body device (Tsi < = 6nm) because of shorter DIBL characteristic length that can confine the surface potential. We've studied the WL interference effect in a 32Gb 16-layer single-gate vertical-channel (SGVC) 3D NAND Flash test chip using the thin-body Tsi = 6nm device. It is found that the far-neighbor WL (n-2) cell also contributes to the WL interference effect as well. Experimental data show that we can use lower BL sensing voltage to suppress the WL interference. A practical WL iterating programming method can greatly cancel the WL interference effects and produce tight programmed Vt distribution for multi-level cell (MLC) operations.

We have successfully developed a 128Gb MLC (or 192Gb TLC) 3D NAND Flash using 16-layer SGVC architecture. The produced memory density is 1.6 Gb/mm2 for MLC or 2.4 Gb/mm2 for TLC (including CMOS peripheral area, spared BL's and blocks). Such memory density is comparable to 48-layer 3D NAND using the popular gate-all-around (GAA) structures. SGVC has the important advantage of much smaller cell size and pitch scaling capability which allows very high-density memory at much lower stacking layer number. SGVC possesses very robust read disturb immunity (>120M read) and long-retention (> 40 years at room temperature) at fresh state that can suppress the very frequent wear-leveling and refresh operations needed for other 3D NAND Flash devices and is very suitable for read-intensive memory. With further stacking/scaling, it is possible to realize low-cost 1Tb single-chip solution at merely 48 layers.

We present several efforts for arcing reduction during high aspect ratio etching. Strategies including pulsing etching adjustments, ex situ multi-cyclic etch approach, flush step incorporation, E-chuck voltage operation, cap material, etc. are explored. The details are discussed in the paper.

The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability problems are two well-known concerns regarding TFT devices. However, another important implication of using TFT devices is that the Vt variation induced by randomly distributed grain boundaries degrades the array performance. In this paper, an extensive TCAD simulation was conducted to systematically investigate how grain boundary generated traps affect NAND Flash devices. Minimizing the density of grain boundary traps is crucial for array performance. In addition, optimal gate control ability reduces the impact of grain boundaries. Thus, using double gate architecture in vertical gate 3-D NAND is favorable. Furthermore, when pitch is scaled in the future, device exhibiting smaller channel thickness should be used to increase the gate control.

Presumed ocular histoplasmosis syndrome (POHS) is rare in Taiwan. We report on a patient with a clinical picture resembling POHS who was successfully treated with intravitreal bevacizumab. A 42-year-old woman had blurred vision of her right eye. Ophthalmological examination revealed multiple juxtapapillary and peripheral punched-out chorioretinal scars. Fluorescein angiography and optic coherence tomography showed subfoveal choroidal neovascularization (CNV). She received three injections of intravitreal bevacizumab. The CNV regressed after treatment. Her visual acuity maintained 20/20 at 1 year follow-up. Taiwan is not an endemic area for histoplasmosis. Clinicians should be cautious in differential diagnosis of the clinical presentation of POHS or similar disease entities. Early identification and timely treatment with intravitreal bevacizumab may rescue the patient from vision loss.

We demonstrate a novel vertical channel 3D NAND Flash architecture — SGVC. SGVC device is a single-gate, flat-channel TFT charge-trapping device with ultra-thin body. Our novel array decoding method enables a tight-pitch (25nm HP) metal BL design to fulfill the large page size (16KB for one plane) for high-performance NAND product. The SGVC flat cell possesses excellent P/E window of ∼10V, small X/Y/Z adjacent-cell interferences, good self-boosting inhibit, and >10K P/E cycling endurance. Due to the advantage of flat cell that is insensitive to etching CD, SGVC device is tolerant to the non-ideal vertical etching and has shown excellent device uniformity from layer to layer. In sharp contract to GAA VC, SGVC suffers no penalty from field-enhancement effect, thus has shown very robust read-disturb immunity against long-term gate stressing. Due to (1) two physical bits per X-Y cell footprint, and (2) efficient array design with minimal overhead, SGVC architecture has 2 to 4 times memory density than GAA VC 3D NAND at the same stacking layer number.

The band structures and field patterns of two-dimensional (2D) triangular photonic crystals with hollow tellurium (Te) rods are calculated using the plane-wave method. Inner-rod and whole-rod rotations are considered to investigate how the rotational and structural symmetries affect E- and H-polarization modes. It is indicated that the H-polarization modes are strongly affected by the shape and interaction between the fields of the rods. In addition, the effect of rotational symmetry on H-polarization modes must be considered when whole rods are rotated. The E-polarization modes for both types of rotations are strongly related to the shape of the rods. Moreover, H-polarization modes determine the absolute photonic band gap (PBG) width when whole rods are rotated, while E-polarization modes determine the absolute PBG width when inner rods are rotated.

For the first time the programming sequence induced array back-pattern effect is studied in a fully integrated split-page 3D vertical gate (VG) NAND Flash test chip. It is found that when programming of WL's starts from the source side it shows a wider programmed Vt (PV) distribution. It is clarified that when many WL's are programmed in the NAND string, the array loading resistance greatly increases, leading to the Vth shift for the earlier-programmed cells which is called the back-pattern effect. Our model indicates that the major mechanism comes from the decreased virtual drain potential of the selected WL when drain-side other WL's are programmed. In order to overcome the back-pattern effect, we propose a “by-page” programming method, where every page is programmed from drain (BL) side toward source side. It shows great improvements in PV distribution.

Strabismus due to a lost rectus muscle is uncommon. Surgical treatment of the condition by means of scleral augmented myopexy of the vertical rectus muscles can reduce the potential for anterior segment ischemia by leaving the vascular supply intact. We report a successful use of expanded polytetrafluoroethylene in this procedure to correct long-term exotropia caused by a lost medial rectus muscle.

A 3D NAND test chip is fabricated to study hot-electron assisted programming. By modifying the local self-boosting method, channel potential is locally boosted, resulting in a large lateral electric field and in turn producing band-to-band tunneling generated hot-electron injection around the selected WL. The hot-electron assisted programming can greatly reduce the maximum programming bias and improve the programming speed. However, hot-electron programming also causes new program disturb modes, and the programming speed depends on the WL location. These are studied in detail.

We demonstrate an 8-layer 3D Vertical Gate NAND Flash with WL half pitch =37.5nm, BL half pitch=75nm, 64-WL NAND string with 63% array core efficiency. This is the first time that a 3D NAND Flash can be successfully scaled to below 3Xnm half pitch in one lateral dimension, thus an 8-layer stack device already provides a very cost effective technology with lower cost than the conventional sub-20nm 2D NAND. Our new VG architecture has two key features: (1) To improve the manufacturability a new layout that twists the even/odd BL's (and pages) in the opposite direction (split-page BL) is adopted. This allows the island-gate SSL devices [1] and metal interconnections be laid out in double pitch, creating much larger process window for BL pitch scaling; (2) A novel staircase BL contact formation method using binary sum of only M lithography and etching steps to achieve 2M contacts. This not only allows precise landing of the tight-pitch staircase contacts, but also minimizes the process steps and cost. We have successfully fabricated an 8-layer array using TFT BE-SONOS charge-trapping device. The array characteristics including reading, programming, inhibit, and block erase are demonstrated.

The design architecture for 3D vertical gate (VG) NAND Flash is discussed in detail. With the unique structure of 3D VG and its decoding method, we have developed several important design innovations to optimize this technology: (1) “Shift-BL scramble” to average the BL capacitances, providing uniform C BL 's for various memory layers; (2) Optimized read waveforms to suppress the hot-carrier induced read disturb in the page reading mode; (3) Novel reverse read with “multi-Vt sensing technique” for different memory layers to compensate the Vt variation due to the layer-to-layer process difference; (4) Program inhibit method and technique to minimize the “Z-directional” self-boosting program disturb in 3D stackable memory. Optimized chip-level performances with excellent memory window for SLC and MLC operations are demonstrated on a 2-layer 3D VG NAND chip.

Despite vertical stacking, the lateral scaling of 3D NAND Flash is critically important because otherwise >16 stacking layers are needed to be cost competitive to 20nm 2D NAND. In this work, we propose a 3D vertical gate (VG) NAND using a self-aligned independently controlled double gate (IDG) string select transistor (SSL) decoding method. The IDG SSL provides excellent program inhibit and read selection without any penalty of cell size increase, making our 3D VG NAND cell as scalable as conventional 2D NAND. We present the world's first < 50nm (37.5nm) half-pitch 3D NAND. The BL decoding and page operation methods are illustrated in detail. This highly pitch scalable VG with IDG SSL approach provides a very cost competitive 3D NAND.

The memory architecture of 3D vertical gate (3DVG) NAND Flash using plural island-gate SSL decoding method is discussed in detail. In order to provide a good array efficiency, 3DVG shares the wordlines (WL) in vertical direction, and BL's in lateral direction. In order to correctly decode the array, every channel BL has its own island-gate SSL device for the control. Meanwhile, many channel BL's are grouped together in one unit, and the staircase BL contacts are formed in order to decode various memory layers. Page operation is naturally defined by the selection of each island-gate SSL device. Due to the plural SSL devices, the 3DVG architecture inevitably has more pages when stacked layer number is increased, thus program inhibit stress is much larger than conventional 2D NAND. In this work, the program inhibit performances of 3DVG TFT NAND are discussed. Scaling capability down to 3Xnm node is also demonstrated.

For the first time the WL-WL pass-gate voltage (VPASS) interference for charge-trapping (CT) NAND Flash devices is studied experimentally. Using a 38nm half-pitch BE-SONOS NAND Flash device we find the threshold voltage decreases significantly with increasing VPASS during reading, contrary to the common believe that CT NAND devices are immune to the interference. We clarify that this extraordinary effect becomes significant for the scaled CT NAND Flash, where a lightly doped junction or junction-free device allows the fringing field caused by VPASS to penetrate into the selected cell and affects the inversion electron density. A small S/D junction recess or a non-cut ONO WL profile is suggested to minimize such effect. Moreover, we also find that the programming speed also decreases when a smaller VPASS PGM is applied. Based on our findings we suggest to use low-K spacer material between WL-WL in order to have better short-channel effect, lower interference and larger memory window for further scaling to sub-20 nm node.

As NAND Flash device scales down, the source/drain junction engineering becomes a key factor for improving the short-channel effect, self-boostiSg program inhibit window, and cell reliability. In this work, the impact of trap-layer above junction (cut-ONO or non-cut ONO), Source/Drain Si recess, and junction doping are studied extensively for the 38nm half-pitch BE-SONOS charge-trapping NAND Flash devices. Our results suggest that a non-cut ONO with junction-free device shows the best memory window and small endurance degradation

We report for the first time a fast initial charge loss (within 1 sec) in charge-trapping (CT) NAND devices. Using a fast-response pulse I–V system retention transients from μsec to sec are characterized and the correlation with programmed states Vt distribution in various NAND Flash test chips is examined. We clarify that the impacts of fast initial charge loss are: (1) it produces a programmed state Vt offset in the various program-verify (PV) levels, and (2) it broadens the Vt distribution thus threatens the MLC capability. Our findings suggest that both high-K/metal-gate and barrier engineered tunneling barrier approaches should be optimized in order to minimize the initial charge loss. We also propose a “refill” method to suppress this effect, and have successfully demonstrated tight Vt distributions in a BE-SONOS CT NAND test chip.

This work presents superb chip-level reliability of a BE-SONOS charge trapping NAND fabricated in both 75nm and 38nm half-pitches. Without any error correction (ECC) >100K P/E cycling endurance for SLC and >3K endurance for MLC are obtained using a novel non-cut SiN trapping layer. Key process integration strategies are discussed, including barrier and trapping layer engineering, p-well and junction doping optimization, gate-etching profile, and SSL/GSL processing. In addition to the overall good performance in programming/erasing and reliability, the non-cut SiN also demonstrated charge retention without any lateral spread - contrary to common misperception of charge migration in SiN [1,2]. We believe this is the first time the reliability and performance of a charge trapping NAND chip are demonstrated to match or surpass those for FG NAND.

This research article primarily investigates supply chain integration with an emphasis on the use of B2B ecommerce as an organizational strategic tool for improving supply chain performance. The balanced scorecard (BSC) approach was adopted to measure the impact of e-business strategy on supply chain integration. The related perspectives of BSC were discussed and coded to explore the influence of the critical factors of B2B e-commerce on supply chain integration. Six international companies were selected and analyzed. NVivo is a tool enabling qualitative data analysis software and it is used to conduct sophisticated data coding as well as supporting various ways to build theories and models. The result of our study are shown and these draw on various theoretical perspectives derived primarily from the synthesis of the multiple data would be used in the analysis of the findings from the empirical case study investigation.

Emerging Central Lab, Macronix International Co., Ltd. Science Park, Hsinchu 300, Taiwan, R.O.C. Phone: +886-3-5786688 E-mail: wcchien@mxic.com.tw Department of Materials Science and Engineering, National Chiao Tung University, Hsinchu 300, Taiwan, R.O.C. Institute of Electronics Engineering, National Tsing Hua University, Hsinchu, 300, Taiwan, R.O.C. Department of Materials Engineering, Tatung University, Taipei, 104, Taiwan, R.O.C.

For the first time a unipolar resistance memory with good performance and reliability is demonstrated. A short (20-50 ns) positive pulse switches the WOx film from low resistance state (LRS) to high resistance state (HRS), while a longer (200-500 ns) positive pulse switches the film from HRS to LRS. Negative pulses, on the other hand, do not produce reversible resistivity changes. Despite the low energy switching, both LRS and HRS are very stable, capable of withstanding 2,500 hours of baking at up to 150 degC- Furthermore, the WOx R-RAM can withstand > 1,000 cycles of LRS/HRS switching, and the device is also highly immune to read disturb. This unipolar device is promising for future 3D high-density NVM storage.

PURPOSE: To report a case of abnormal electrooculogram and abnormal electroretinogram after lightning-induced ocular injury. DESIGN: Interventional case report. METHODS: A 39-year-old man was struck on the left forehead by a bolt of lightning. After resuscitation, he regained consciousness. RESULTS: Ophthalmic examination disclosed a best-corrected visual acuity of right eye (RE): 20/25 and left eye (LE): 20/50, burned eyelashes, punctate keratitis, iridocyclitis, anterior subcapsular lens opacity, missing foveolar reflex, and macular pigment epithelial defect LE. Fluorescein angiography revealed only an area of punctate leaking in the left eye. Electrooculogram showed reduced amplitudes, in the left eye. Arden ratio was RE: 2.04 and LE: 1.52. The amplitudes of scotopic and photopic electroretinogram b-waves were reduced in the left eye. After uneventful cataract surgery in the left eye, the follow-up electrooculogram and electroretinogram still showed reduced amplitude in the left eye. CONCLUSION: Lightning is an uncommon cause of ocular injury. This is the first report of abnormal electro-oculogram and abnormal electroretinogram after lightning-induced ocular injury.

A complementary metal oxide semiconductor (CMOS)-compatible WO x based resistive memory has been developed. The WO x memory layer is made from rapid thermal oxidation of W plugs. The device performs excellent electrical properties. The switching speed is extremely fast (∼2 ns) and the programming voltage (8-cycle endurance. For multi-level cell (MLC) operation, it demonstrates 2-bit/cell storage with the endurance up to 10000 times. The rapid thermal oxidation (RTO) WO x resistance random access memory (RRAM) is very promising for both high-density and embedded memory applications.

The three-probe scheme for input impedance measurement was modified for measuring the S-parameters of a two-port device. The method is simple, low cost and can be easily scaled to millimetre-wave frequencies. The measured results were verified by an automatic network analyser. >

Integrated-circuit phase-lock oscillators are extremely difficult to develop above 60 GHz because of circuit losses. A viable alternative is to use a frequency doubler. A Q-to-W-band (40 to 80 GHz) frequency doubler has been developed using integrated-circuit suspended stripline. A conversion loss of less than 6.5 dB has been achieved with the output frequency at 80 GHz. This high efficiency was obtained by an innovative input and output matching circuit design. The advantages over a waveguide doubler include large reductions in size, weight and cost.