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The generation and evolution of defects in 4H-SiC p-n junctions due to carrier injection under forward bias are investigated by synchrotron white beam x-ray topography, electroluminescence imaging, and KOH etching. Low angle grain boundaries are observed to act as one of a number of possible nucleation sites of stacking faults.

The morphology and nucleation sites of stacking faults formed during the forward operation of 4H silicon carbide p-i-n diodes were investigated using optical emission microscopy (OEM) and transmission electron microscopy (TEM). Partial dislocations bounding the stacking faults are mostly aligned to the <11–20> directions with Burgers vectors of the 1/3<1–100> type. Arrays of dislocation half loops in the blocking layer serve as nucleation sites of double-rhombic stacking faults. The morphology of these stacking faults indicates that short basal plane segments associated with threading dislocations are the origin of rhombic stacking faults. All dislocations in a half-loop array have the same Burgers vector and nucleate on a single basal plane, which was evidenced by the merging of double-rhombic stacking faults. Most pre-existing basal plane dislocations within the blocking layer which are visible in OEM images dissociate to form stacking faults during the degradation. Basal plane dislocations aligned along the off-cut direction form rectangular stacking faults, while others break up into partial dislocation segments along the <11–20> directions, which are often wedge-shaped. Thus, all nucleation sites of the stacking faults correspond to pre-existing dislocation segments residing in basal planes. The morphology and evolution of double-rhombic stacking faults indicate that the p-i-n diode degradation cannot be driven by stress in the structure. © 2004 American Institute of Physics. [ABSTRACT FROM AUTHOR]

The electrical degradation of 4H–SiC PiN diodes has recently attracted much interest and is a critical material problem for high power applications. The degradation is caused by stacking faults observed as an increased forward voltage drop after forward injection operation. In this article we have combined electrical, optical, and structural techniques to study the formation and growth of the stacking faults causing degradation. We will show three different sources causing two different types of stacking fault properties. © 2004 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Research is done on the field-effect mobility (FEM) in polythiophene (PT) polymer field-effect transistors (PFETs) which increases with reduced channel lengths during high driving forces across the source and drain, which is contradictory to the decrease in mobility caused by short-channel effects in amorphous Si thin-film transistors. In conclusion, with increased longitudinal electric field, the correlation between FEM and gate bias is largely enhanced.

An examination is done to develop an analytic theory based on an earlier model of the admittance of a ballistic transit time diode terahertz oscillator with tunnel emission of electrons into a transit space. In conclusion, the appearance of slow-drifting electrons substantially increases space charge in the transit space and influences the static JV-characteristic but the high-frequency admittance is almost invariable.