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Typically, hardware implemented neural networks are trained before implementation. Extreme learning machine (ELM) is a noniterative training method for single-layer feed-forward (SLFF) neural networks well suited for hardware implementation. It provides fixed-time learning and simplifies retraining of a neural network once implemented, which is very important in applications demanding on-chip training. This study proposes the data flow of a software support tool in the design process of a hardware implementation of on-chip ELM learning for SLFF neural networks. The software tool allows the user to obtain the optimal definition of functional and hardware parameters for any application, and enables the user to interact throughout the design process. Combining in a transparent way for the user, simulation and Xilinx synthesis tools, the tool recommends the optimal configuration, generating, finally, a synthesizable IP-core. As application, the field-programmable gate array implementation for real-time detection of brain areas in electrode positioning during a deep brain stimulation surgery is described. The generated IP-core can execute a peak of 95 ELM trainings per second on a low-cost Spartan 6 device, making possible its real-time use in this application.

Extreme Learning Machine (ELM) on-chip learning is implemented on FPGA.Three hardware architectures are evaluated.Parametrical analysis of accuracy, resource occupation and performance is carried out. Display Omitted Extreme Learning Machine (ELM) proposes a non-iterative training method for Single Layer Feedforward Neural Networks that provides an effective solution for classification and prediction problems. Its hardware implementation is an important step towards fast, accurate and reconfigurable embedded systems based on neural networks, allowing to extend the range of applications where neural networks can be used, especially where frequent and fast training, or even real-time training, is required. This work proposes three hardware architectures for on-chip ELM training computation and implementation, a sequential and two parallel. All three are implemented parameterizably on FPGA as an IP (Intellectual Property) core. Results describe performance, accuracy, resources and power consumption. The analysis is conducted parametrically varying the number of hidden neurons, number of training patterns and internal bit-length, providing a guideline on required resources and level of performance that an FPGA based ELM training can provide.

A method is proposed for implementing Mealy FSMs logic circuits with embedded memory blocks. The method is based on encoding of the rows of FSM structure table and replacement of logical conditions. Example of design and results of investigations are given. Our approach allows diminishing the number of LUTs in the block of RLC due to splitting the initial set of logical conditions. Also it results in the decrease of used EMBs for around 15% of standard benchmarks.

The paper presents a new concept of the selection of prime implicants in a two-level logic minimization of Boolean functions. The method is based on the two-level minimization process of the Boolean functions, according to the Quine-McCluskey approach. Initially, the set of prime implicants for the logic function ought to be calculated. Next, the selection process is applied to achieve the minimal formula. Such an operation is a typical covering problem and in general case it has exponential computational complexity. In the paper we propose a new prime implicants selection method. An idea is based on the hypergraph theory. The prime implicants matrix (chart) is formed as a selection hypergraph. If the selection hyper-graph belongs to the Exact Transversal Hypergraph class ( xt-class ), the solution may be obtained in a polynomial time, which is not possible in a general case. The proposed method is illustrated by an example. All necessary steps will be shown in order to apply the proposed selection algorithm to minimize an exemplary Boolean function.

A design method is proposed for EMB-based Mealy FSM. The method is based on transformation of collections of output functions into state variables. Only two EMBs are necessary in the best case to implement the FSM logic circuit. The conditions of applying proposed method are given. An example of design is shown.

In the paper a method of using the Unified Modeling Language for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine di- agrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams, expressed in XML language, to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Ar- rays). The UML specification is used to generate an eective program in Hardware Description Languages (HDLs), especially Verilog.

In the paper a method of using the Unified Modeling Language diagrams for specification of digital systems, especially logic controllers, is presented. The proposed method is based mainly on the UML state machine diagrams and uses Hierarchical Concurrent Finite State Machines (HCFSMs) as a temporary model. The paper shows a way to transform the UML diagrams to the form that is acceptable by reconfigurable FPGAs (Field Programmable Gate Arrays). The UML specification is used to generate an effective program in Hardware Description Languages (HDLs), especially Verilog.

This paper concerns the application of titanium-nickel rings in modeling the cranium. After being fixed to the osseous margins, the ring’s expansion at the same time broadens and shortens the cranium vault. The rings formed from a straight superelastic wire, flattened to an ellipse, do not show the presence of a typical force plateau but rather a pseudoelastic loop during loading-unloading in the relationship between the force and the deflection. Based on the idea that superelasticity in more complex shape-springs may be induced by the precipitation hardening process, the further studies were carried out on alloys with higher nickel contents (51.06 at.% Ni). The rings that had been formed were welded and aged at an optimal temperature and time. The improved superelastic behavior during compression and unloading the rings was obtained by introducing small deformation by drawing the quenched wires before forming the rings and aging. Very positive clinical reshaping by long-term distraction with the superelastic ring-shaped springs was achieved in young children under one year and a less spectacular effect was observed in the group of older children.

The paper promotes to construct a synthesizable VHDL model from a graphical representation of Petri Net. The VHDL code provides a clear semantics of graphically designed reconfigurable logic controller and serves as reference model for eventual further optimization efforts. It is considered that automatically generated array structure of logic controller is optimized for synthesis by professional tools. The most useful aspect for presented purposes is the ability to execute a VHDL behavioral specification closely related with array-based implementation. Even if the final implementation is not optimized during the logic synthesis process, it is compact, easy to modify and efficient.

As long as resection of sagittal suture eliminates craniostenosis it leads to desired cranium broadening and shortening solely in the case of children under six months of age. In the majority of cases, especially in older children, boat-shaped cranium remains rather unchanged and its effective modeling requires extensive dissection and osteotomy of the whole cranium vault (e.g., frontal, occipital and parietal bones). Lauritzen's method is an alternative solution. It consists of distraction of cranium vault bones with the aid of steel springs. In order to simplify and improve the efficacy of treatment since 2002, the authors originated the application of titanium-nickel rings to model the cranium. After the sparing excision of cranium vault sutures in the shape of letter "H" the compressed ring is given in the sagittal axis oval shape and in this form it is fixed to osseous margins. The ring's expansion at the same time broadens and shortens the cranium vault. Material was analyzed from 7 children (range, 9 months to 4 years of age), who were treated in the years 2002-2006 because of sagittal craniostenosis. Observations made so far and good treatment results indicate purposefulness of discussed treatment continuation.

Statechart diagram and UML technique can be a vital part of early conceptual modeling. At the present time there is no much support in hardware design methodologies for reconfiguration features of reprogrammable devices. Authors try to bridge the gap between imprecise UML model and formal HDL description. The key concept in author's proposal is to describe the behavior of the digital controller by statechart diagrams and to map some parts of the behavior into reprogrammable logic by means of group of states which forms sequential automaton. The whole process is illustrated by the example with experimental results.

In the paper, the solution dedicated for FPGA devices of a synthesis of parallel multiplication systems with the alternative approach, called mutual exclusion , for results of partial products is presented. There are proposed a reducer with the factor 4:2 for parallel multipliers, based on Wallace tree structures, that are dedicated for 4-input and 1-output Look-Up Table (LUT) function generator used in FPGA devices. The elaboration refers to the solution for multiplying using FPGAs the numbers of 4 and 8 bits. However it can be enlarged up to 16 and 32 bits. The proposed solution gives the opportunity to use the probability of conditional significant partial products and faster service - fewer logic levels for special cases of multiplication related to the specific values of the sums of partial product bits.

A method for reducing the number of LUT elements in the circuit of FPGA-based Moore FSM is proposed. The method is based on using two sources of codes of pseudoequivalent states. It allows reducing the number of terms in systems of input memory functions up to this value for equivalent Mealy FSM. The system of microoperations is implemented using embedded memory blocks.

The method of partial reconfiguration of Compositional Microprogram Control Units implemented on FPGAs is proposed. The method is based on the swapping of the content of Control Memory while the rest of the system is not modified. Such approach permits to decrease the size of a bit-stream that is sent to the device. Therefore time needed for device configuration is shorter. Proposed solution is much more safe due to less errors that can occur during reconfiguration of FPGAs. An example of proposed method application is discussed. The researches conducted by authors have shown that proposed method permits to decrease the size of a bit-stream that is sent to the device in comparison with traditional method even up to 95%.

The method of decreasing of the amount of feedback signal in the compositional microprogram control unit is proposed. Main idea of the method is to use a part of microinstruction address for the code representation of operational linear chain. The proposed method does not require any new structural elements and has no influence on performance of digital system with compositional microprogram control unit. An example of proposed method application is given.

In the paper design method of Reprogrammable Logic Controllers oriented on partial reconfiguration is presented. The Controller is specified by Interpreted Petri net. The Petri net model is decomposed onto a set of State Machine (SM) subnets. Each subnet is modelled using Verilog, and then all subnets are implemented using Field Programmable Gate Arrays (FPGAs). The novel capability of the method is the opportunity for dynamic change of the FPGA configuration with a portion of the original bitstream. Such approach is necessary when a transmission channel for a new configuration is a bottleneck.

In the paper, a synthesis method of logic controllers for safety critical systems into field programmable logic is presented. The specification of the system in the form of symbolic, if-then or if-then-else conditional decision rules is used for directly mapping to netlist format, or transformed into a HDL format that is accepted by standard FPGA simulators and synthesis tools. In addition, models of Logic Controllers are verified using the well-developed Petri net theory, and then they are translated through automated processes into selected FPGA specification format.

In the paper a synthesis method of logic controllers for safety critical systems into field programmable logic is presented. The specification of the system in the form of symbolic, if-then or if-then-else conditional decision rules is used for directly mapping to netlist format, or transformed into a HDL format that is accepted by standard FPGA simulators and synthesis tools. In addition, models of Logic Controllers are verified using the well-developed Petri net theory, and then they are translated through automated processes into selected FPGA specification format.

This paper presents a framework that performs the programmable logic synthesis of rule-based descriptions of concurrent controllers. These descriptions can be obtained from several specification models of those controllers (for example, Control Interpreted Petri net, Grafcet or the IEC 1131-3 Sequential Function Chart). The internal description, in the form of symbolic conditional decision rules, is then transformed into a format that is accepted by standard FPLD and FPGA simulators and synthesisers, for example OrCAD or VHDL. The concurrent state machine model of the logic controller is verified using the well-developed Petri-net theory, and then it is translated through automated processes into a selected FPGA specification format, for example the Xilinx netlist format (XNF). This paper presents part of a broad project in the field of hardware/software co-design. The main purpose is to develop different implementations of controllers using a simple, standard and well-known design methodology like SFC (Grafcet) or Petri nets. The paper deals exclusively with the design of FPGA-based controllers.

An implemented design framework contains the Programmable Logic based synthesis of rule-based descriptions that are obtained from several specification models of Concurrent Controllers (for example: Control Interpreted Petri net, Grafcet or IEC 1131-3 Sequential Function Chart). The specification in the form of symbolic conditional decision rules is transformed into a format that is accepted by standard FPLD & FPGA simulators and synthesizers, for example OrCAD or VHDL. The Concurrent State Machine model of Logic Controller is verified using the well-developed Petri net theory, and then it is translated through automated processes into selected FPGA specification format, for example Xilinx netlist format (XNF).

The paper presents comparison between efficiency of an industrial FPGA design software tool Altera Quartus II and similar design software tool Synthagate by Syntezza company of an academic origin. The experiments were performed using a series of examples describing the Mealy finite state machines; one hot state encoding was used in all cases. Area (number of used logical blocks) was the main parameter used for the comparison. Influence of the way of FSM description (in VHDL language) on the quality of synthesis was studied. The obtained results show that Synthagate in almost all cases performs synthesis more efficiently and essentially quicker than Altera Quartus. Section I presents motivation of the research. Section II reminds the notion of FSM. Section III describes problems which had to be solved to provide correctness of experimental comparison. Section IV presents some details about state encoding way used in the experiments. In Section V, the experimental results are presented. Section VI describes the problems related to the comparison which still have to be solved. Section VII presents the conclusions from the experiments. Section VIII suggests possible reasons of the detected situation.

This work shows an FPGA implementation for the matrix inversion algebra operation. Usually, large matrix dimension is required for real-time signal processing applications, especially in case of complex adaptive systems. A hardware efficient matrix inversion procedure is described using QR decomposition of the original matrix and modified Gram-Schmidt method. This works attempts a direct VHDL description using few predefined packages and fixed point arithmetic for better optimization. New proposals for intermediate calculations are described, leading to efficient logic occupation together with better performance and accuracy in the vector space algebra. Results show that, for a relatively small device as Xilinx Spartan3 XC3S1000, a matrix size up to 23 × 23 can be implemented, having a matrix inversion computation time of 253μs. Accuracy results compared to floating point computation and an estimation of required clock cycles as a function of matrix size are analyzed.

In the paper the method of reduction of the memory size in the microprogrammed controllers with sharing codes is discussed. The idea is based on the modification of internal modules and connections of the device. Next, the reduction of the microinstruction length based on the hypergraph theory is performed, thus the total size of the memory is highly reduced.

Logic design of digital devices is a very important part of the Computer Science. It deals with design and testing of logic circuits for both data-path and control unit of a digital system. Design methods depend strongly on logic elements using for implementation of logic circuits. Different programmable logic devices are wide used for implementation of logic circuits. Nowadays, we witness the rapid growth of new and new chips, but there is a strong lack of new design methods. This book includes a variety of design and test methods targeted on different digital devices. It covers methods of digital system design, the development of theoretical base for construction and designing of the PLDbased devices, application of UML for digital design. A considerable part of the book is devoted to design methods oriented on implementing control units using FPGA and CPLD chips. Such important issues as design of reliable FSMs, automatic design of concurrent logic controllers, the models and methods for creating infrastructure IP services for the SoCs are also presented.The editors of the book hope that it will be interesting and useful for experts in Computer Science and Electronics, as well as for students, who are viewed as designers of future digital devices and systems.

In the paper the CAD system dedicated for modeling, verification, and synthesis of concurrent controllers modeled by interpreted Petri net is presented. Petri net model can be prepared as graph or as textual form. Controllers specified by Petri nets can be analyzed and implemented using method suitable for such model. For verification of Petri net another part of system is used. Moreover, the results of verification are decomposition of net into several communicating state machines (as finite state machines, FSMs). After verification it is possible to transform Petri net model into HDLs model (VHDL and Verilog) and alternatively into EDIF or XNF netlist format. Such prepared models are also simulated and synthesized using other academic or commercial CAD systems. The system has been developing at University of Zielona Gora. Development of new methods of modeling, verification and synthesis has been contributed to make an attempt the new integrated version of the system. In addition, using of Java environment gives opportunity to work out the system that is platform independent.

Paper presents the CAD system, referred to as PeNCAD, which supports the design of logic controllers. The system developed at the University of Zielona Gora allows designing concurrent logic controllers specified by means of Petri net. The designed control system is implemented in the reprogrammable FPGA structure. The further development of the system has been discussed in details regarding the application of the partial reconfiguration systems. The use of the partial reconfiguration FPGA-based systems in the process of logic controllers' design enables to increase their flexibility and functionality. Additional consequences come in the form of the decrease in hardware requirements needed for the implementation processes of the logic controller. The reconfiguration consists in replacing of the subnet associated with a macroplace. The Xilinx FPGA devices were used while carrying out the tests.

Dupuytren's contracture is a common condition leading to impairment of the function of the hand which affects from 2 to 12 % of the population, mainly males, and presents as progressive contracture of fingers caused by shortening of the palmar aponeurosis. The objective of the work was to present our own approach to managing Dupuytren's disease and evaluate treatment results in patients with hypertrophy of the palmar aponeurosis. Material and method 288 patients with Dupuytren's disease were treated at the Plastic Surgery Hospital in Polanica Zdroj over a period of 25 years (1977-2002). The present paper is a retrospective analysis of treatment results in 253 patients for whom complete medical documentation was available. All patients were operated in local anaesthesia in ischemia. A Bunnell flap skin incision was followed by a fasciectomy of the hypertrophied segment of the palmar aponeurosis. The skin wound was closed using V-Y plasty. Postoperative management involved hand elevation and early rehabilitation. Results Restoration of the full range of motion and total extension in the MP joint and the interphalangeal joints were achieved in 70% and 68% of patients, respectively. Of 145 patients who were professionally active, 132 were able to return to work. Finger amputation was necessary in 2 patients, one patient suffered from arthrodesis and two other developed skin necrosis which was removed with the wound closed by skin grafts. A follow-up examination 6 months after the operation revealed a recurrence in 8 patients and deterioration of hand dexterity with finger stiffness in 4. Conclusions A low complication rate and good treatment results are arguments in favour of the approach adopted at our hospital, i.e. surgery in local anaesthesia in ischemia with compressive bandaging, using a Bunnell flap skin incision followed by radical fasciectomy and V-Y plasty.

In the paper a new approach to simulation of modeled concurrent controllers is presented. In the case presented, a concurrent controller is modeled using Petri nets and HDL languages. A very important stage of digital circuits design is verification, because it saves time and money. Simulation is the simplest method of verification. In the literature a lot of approaches to circuit simulation are described, but a new technology gives new possibilities and it gives a new idea to use XML and Verilog to simulate concurrent controllers.

In the paper digital modelling and synthesis of automata in Hardware Description Languages is described. There is presented different kinds of automata and methods of realization using languages like VHDL and Verilog. Basic models for control units are: Finite State Machine (FSM), Algorithmic State Machine (ASM) and Linked State Machine (LSM). FSM, ASM and LSM can be represented graphically, which would help a designer to visualize and design in a more efficient way. On the other hand, a designer needs a fast and direct way to convert the considered designs into Hardware Description Language (HDL) codes for simulation and analysis it for synthesis and implementation.

In this paper implementation of WWW server in SoPC (System-on-Programmable-Chip ) is described. Reasons for implementing a WWW server in SoPC are explained. Moreover, the basis architecture of SoPC will be mentioned. The proposed system is divided into two parts. First part is software implemented for microprocessor, which consists of operating system, web server and additional functionalities. Second part is a control process that is implemented in FPGA structure. The software solution is based on the Nut/OS operating system and web server implemented in it. The dynamic reconfiguration is also discussed.© (2006) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.

In the paper modelling of FIR filters by means of Verilog and SystemVerilog is presented. Hardware/software co-design approach for such systems is applied in the presented design. As a final technology for a FIR filters system implementation, a FPSLIC device is considered. Filters system demonstrates example methods of communication between FPGA and AVR microcontroller in a FPSLIC structure, i.e. the communication through SRAM memory, addressing lines, data bus, interrupts. It also demonstrates how to serve peripheral elements in FPSLIC device by means of DPI interface. FIR filters model contains also interface which implements a FPSLIC cache logic and gives opportunity to a dynamical reconfiguration of FPGA in a FPSLIC structure.

The fast control unit of telecommunication system is represented as Mealy finite-state-machine. The method of hardware optimization in the logic circuit of such control unit is proposed. Method is based on matching of different codes to the equal microinstructions in the different subtables of direct structural table of Mealy finite-state-machine. An example of application of proposed method is given.

The main aim of this paper is to demonstrate a practical application of the Petri net decomposition algorithm based on finding deadlocks and traps. Obtained in such decomposition Concurrent Digital Systems represented by set of State Machine components are implemented using Programmable Logic. The experimental results have shown that presented approach may produce economical implementations of dedicated Application Specific Logic Controllers. Petri nets are considered as formal models as well as intermediate models for hardware descriptions in Verilog-HDL that are used for synthesis and final implementation into FPGAs.

In this paper, design of safety critical logic controller by means of programmable logic and microprocessor is described. The solution is based on duplicated Master-Slave architecture and results comparison from both pairs. The architecture was adapted to a FPGA device with embedded microprocessor -- in considered solution the Atmel FPSLIC was chosen. In design process tasks have been divided between hardware and software parts. The hardware part has been described in HDLs. The software for microprocessor has been written in its assembler or low-level C language. The process of verification that is based on simulation comparisons of solutions obtained in two different ways is also presented.

Hardware description languages (HDLs) allow creating bigger and bigger designs nowadays. The size of prototyped systems very often exceeds million gates. Therefore verification process of the designs takes several hours or even days. The solution for this problem can be solved by hardware acceleration of simulation.

In the paper, a structured synthesis method based on hierarchical Petri nets is presented. An implemented design framework contains the programmable logic synthesis of rule-based descriptions that are obtained from several specification models of concurrent controllers, especially in control interpreted Petri net format. The specification in the form of symbolic conditional decision rules is transformed into a format that is accepted by standard FPGA simulators and synthesizers, such as Xilinx Foundation Series. The concurrent state machine model of logic controller is verified using the well-developed Petri net theory, and then it is translated through automated processes into selected FPGA specification format, e.g. Xilinx netlist format (XNF). Proposed technique is illustrated by presenting a solution to the popular "drill station" problem. The methods are especially useful in designing of industrial application specific logic controller (ASLC) with FPGA.

The logic control program is usually specified by drawing the Petri net in terms of interface with the electro-mechanical devices and the environment of the system. In such case it is not immediately evident that the control system behaves in a satisfactory way. Industrial engineers prefer frequently a form of specification, like interpreted Petri Net, sequential function chart (SFC), Grafcet or Grafchart. On the other hand, some popular techniques are informal and do not provide means to validate the design. In the paper, modelling, analysis and synthesis of logic controller described by Petri nets is presented. Additional, the use of design/CPN system for modelling, testing and analysis of logic controllers described by means of coloured, interpreted Petri nets is shown. The proposed methods are especially useful in designing of industrial application specific logic controller (ASLC) with FPGA.

A new class of Petri nets, called coloured control interpreted Petri nets (CCIPN), is introduced. The advantages of CCIPN modelling for specification of logic controller programs are shown. We combine the coloured interpreted Petri nets (treated as an object) with the object-oriented controlled part. Apart from several papers we do not specify the coloured tokens as dynamically evaluated composite objects, but as a part of the object. The net is constructed from the simpler objects that are related with VHDL entities from the user-defined library. The formal objects that describe the controlled part (electro-mechanical system) are related with the coloured tokens in the Petri net. The linked coloured Petri nets that describe the objects are combined with a coloured Petri net specifying the logic controller. They are refined and combined into a complete Petri net system (total model). It may be simulated, verified and synthesized in a user-friendly VHDL environment, collaborating with our experimental design tools. Our technique is illustrated by presenting a solution to the popular "tank filling" problem. The proposed methods are especially useful in designing of industrial application specific logic controller with FPLD (FPGA and CPLD).