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To link to full-text access for this article, visit this link: http://dx.doi.org/10.1016/j.sysarc.2006.12.007 Byline: Myungsu Choi (a), Zachary Patitz (b), Byoungjae Jin (b), Feng Tao (b), Nohpill Park (b), Minsu Choi (c) Keywords: Quantum-dot cellular automata (QCA); Layout=timing problem; Global asynchrony local synchrony (GALS); Place and route; Floorplanning Abstract: The concept of clocking for QCA, referred to as the four-phase clocking, is widely used. However, inherited characteristics of QCA, such as the way to hold state, the way to synchronize data flows, and the way to power QCA cells, make the design of QCA circuits quite different from VLSI and introduce a variety of new design challenges and the most severe challenges are due to the fact that the overall timing of a QCA circuit is mainly dependent upon its layout. This fact is commonly referred to as the "layout=timing" problem. To circumvent the problem, a novel self-timed QCA circuit design methodology referred to as the Globally Asynchronous, Locally Synchronous (GALS) Design for QCA is proposed in this paper. The proposed technique can significantly reduce the layout-timing dependency from the global network of QCA devices in a circuit; therefore, considerably flexible QCA circuit design and floorplanning will be possible. Author Affiliation: (a) LG Electronics, Seoul, Republic of Korea (b) Department of Computer Science, Oklahoma State University, Stillwater, OK, USA (c) Department of Electrical and Computer Engineering, University of Missouri-Rolla, Rolla, MO, USA Article History: Received 19 May 2006; Revised 9 November 2006; Accepted 15 December 2006

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