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After decades of process scaling driven by Moore’s law, the silicon microelectronics world is now defined by length scales that are many times smaller than the dimensions of typical micro-optical components. This size mismatch poses an important challenge for those working to integrate photonics with complementary metal oxide semiconductor (CMOS) electronics technology. One promising solution is to fabricate optical systems at metal/dielectric interfaces, where electromagnetic modes called surface plasmon polaritons (SPPs) offer unique opportunities to confine and control light at length scales below 100 nm (refs 1, 2). Research groups working in the rapidly developing field of plasmonics have now demonstrated many passive components3, 4 that suggest the potential of SPPs for applications in sensing5 and optical communication6. Recently, active plasmonic devices based on III–V materials7, 8, 9 and organic materials10 have been reported. An electrical source of SPPs was recently demonstrated using organic semiconductors by Koller and colleagues11. Here we show that a silicon-based electrical source for SPPs can be fabricated using established low-temperature microtechnology processes that are compatible with back-end CMOS technology.

Our study is focused on Plasma Enhanced Chemical Vapor Deposition (PECVD) of silicon dioxide films at low temperatures (< 150 oC) using Inductively Coupled (IC) High-Density (HD) plasma source. We recently fabricated Thin Film Transistors (TFTs) with high-quality ICPECVD gate oxides, which exhibited a competitive performance. For better understanding of the influence of deposition parameters on both the deposition kinetics and oxide quality, we have modeled the Ar-SiH4-N2O plasma system with 173 chemical reactions. We simulated concentrations of 43 reactive species (such as e.g. SiHx radicals and SiHx+ (x=0-3) ions, polysilanes, SiO, SiN, SiH3O, SiH2O, HSiO, etc., as well as atomic hydrogen, nitrogen and oxygen) in plasma. We further used our simulations to qualitatively explain (in terms of concentrations of the reactive species) the influence of SiH4/N2O gas-flow ratio and total gas pressure on film electrical properties and deposition rate.

This paper presents a novel approach to make high-performance CMOS at low temperatures. Fully functional devices are manufactured using back-end compatible substrate temperatures after the deposition of the amorphous-silicon starting material. The amorphous silicon is pretextured to control the location of grain boundaries. Green-laser annealing is employed for crystallization and dopant activation. A high activation level of As and B impurities is obtained. The main grain boundaries are found at predictable positions, allowing transistor definition away from these boundaries. The realized thin-film transistors (TFTs) exhibit high field-effect carrier mobilities of 405 cm2/Vmiddots (NMOS) and 128 cm2/Vmiddots (PMOS). CMOS inverters and fully functional 51-stage ring oscillators were fabricated in this process and characterized. The process can be employed for large-area TFT electronics as well as a functional stack layer in 3-D integration.

The parasitic factors that strongly influence the measurement accuracy of Cross-Bridge Kelvin Resistor (CBKR) structures for low specific contact resistances (�?�c) have been extensively discussed during last few decades and the minimum of the �?�c value, which could be accurately extracted, was estimated. We fabricated a set of various metal-to-metal CBKR structures with different geometries, i.e., shapes and dimensions, to confirm this limit experimentally and to create a method for contact metal-tometal interface characterization. As a result, a model was developed to account for the actual current flow and a method for reliable 蚠 extraction was created. This method allowed to characterize metal-to-metal contact interface. It was found that in the case of ideal metal-to-metal contacts, the measured CBKR contact resistance was determined by the dimensions of the two-metal stack in the area of contact and sheet resistances of the metals used.

In order to measure silicide-to-silicon specific contact resistance rhoc, transmission line model (TLM) structures were proposed as attractive candidates for embedding in CMOS processes. We optimized TLM structures for nickel silicide and platinum silicide and evaluated them for various doping levels of n- and p-type Si. The measurement limitations and accuracy of the specific contact resistance extraction from the optimized TLM structures are discussed in this paper.

Non-volatile memory devices are realized using CVD and ALD of all active layers in a cluster tool. The floating gate consists of silicon nanocrystals. A high nanocrystal density was obtained through an enhanced nucleation rate by using disilane (Si2H6) as well as trisilane (Si3H8, known as Silcore®) as precursors for low-pressure chemical vapor deposition (instead of silane). The deposition temperature was 300–325 °C and the deposition pressure ranged between 0.1 and 10 mbar. To prevent oxidation of the nanocrystals, they were encapsulated directly after deposition with a 10-nm thick ALD-grown Al2O3 layer (blocking oxide). The deposition of Si-nanocrystals as a function of substrate temperature, precursor flow rate and total gas pressure was explored. Appreciable retention and endurance were measured on realized Al/TiN/Al2O3/Si-nanocrystal/SiO2/ Si(100) floating-gate capacitor structures.

We carried out the modeling of chemical reactions in a silane-containing remote Inductively Coupled Plasma Enhanced Chemical Vapor Deposition (ICPECVD) system, intended for deposition of silicon, silicon oxide, and silicon nitride layers. The required electron densities and Electron Energy Distribution Functions (EEDF) were taken from our earlier Langmuir-probe measurements. The EEDF exhibited a fraction (0.5%) of fast electrons in the energy range between 20 and 40 eV, strongly deviating from Maxwell–Boltzmann (MB) distribution. We considered 16 electron impact dissociation/ionization reactions and 26 secondary reactions for homogeneous propagation of plasma species. We noticed a significant difference (orders of magnitude) between the concentrations of the species obtained using experimental EEDFs and MB energy distributions, pointing to the importance of the fast electron tail. For silicon oxide films, a qualitative agreement between the radical densities in plasma at different total pressures and the deposition rate was observed.

Silicon dioxide films were deposited by means of remote inductively coupled plasma enhanced chemical vapor deposition (ICPECVD) in Ar-N2O-SiH4 plasma at 150 °C and pressures between 1 and 6 Pa. Chemical modeling of our plasma indicated an increased fraction of SiH3 radicals at 6 Pa (compared to SiH2, SiH, and Si species), while at 1 Pa their relative contribution on film growth should be much smaller. Layer growth from SiH3 radicals would result in better dielectric quality. We found that the films contained a high amount of positive charge and exhibited large leakage currents at 1 Pa, while films with lower positive charge and much lower leakage currents were grown at 6 Pa. The deposition rate was ~4.5 nm/min at 1-2 Pa and 3.5 nm/min at 6 Pa. The lower growth-rate at 6 Pa could be ascribed to the formation of denser films, as well as to the changing plasma and surface chemistry. These results were consistent with chemical modeling.

The traditional microchip processes, stores and communicates electrical information. Here we review an emerging class of microchips that have additional functionality through extra integrated components in the chip. In the final manufacturing stage, layers are added on top of the chip, with a specific property such as sensitivity to ionizing radiation. This paper reviews the technology underlying these monolithic microsystems, including the incorporation of new materials, the unconventional application of photoresist layers, and low-temperature technology for suspended membranes. The manufacturing of exemplary microsystems, such as the active pixel sensor and liquid-crystalon-silicon, is detailed. A new class of fully integrated radiation imaging systems is now technologically within reach.

We measured electron density and electron energy distribution function (EEDS) vertically through our reactor for a range of process conditions and for various gases. The EEDF of Ar plasma in the reactor could largely be described by the Maxwell-Boltzmann distribution function, but it also contained a fraction (~10-3) of electrons which were much faster (20-40 eV). At low pressures (6.8-11 µbar), the tail of fast electrons shifted to higher energies (Emax ~50 eV) as we measured more towards the chuck. This tail of fast electrons could be shifted to lower energies (Emax ~30 eV) when we increased pressure to 120 µbar or applied an external magnetic field of 9.5 µT. Addition of small amounts of N2 (1-10%) or N2O (5%) to Ar plasma lowered the total density of slow electrons (approx. by a factor two) but did not change the shape of the fast-electron tail of the EEDF. The ionization degree of Ar-plasma increased from 2.5 104 to 5 104 when an external magnetic field of 9.5 µT was applied.

In this work, amorphous silicon films with preformed a-Si lines were crystallized using a diode pumped solid state green laser irradiating at 532 nm. The possibility of controllable formation of grain boundaries was investigated. The crystallization processes in the rapidly melted silicon films were discussed. The influence of the crystallization parameters (i.e., energy density, scan velocity, etc.) and structure type (i.e., with and without preformed lines) on properties of the crystallized films was studied. The laser treatment with an energy density of 1.00 J/cm2 at a laser pulse overlapping of 90% provided the optimal crystallization process with predefined grain boundary location. X-ray diffraction (XRD), SEM and AFM microscopy have been used to characterize the crystallized silicon films.

the process, especially of the initial stage of the deposition. In this paper the first results obtained from in situ reflective highenergy electron diffraction (RHEED) measurements during the ALD of $Al_2O_3$ on Si(001), using $Al(CH_3)_3$ and $H_2O$ as precursors, are presented. The goal of this work is to show the feasibility of using a surface-sensitive analysis technique to study the surface chemistry during ALD. The results show the expected decrease in reflected intensity on deposition of aluminum atoms and a recovery of intensity, attributed to removal of methyl groups from the surface, on exposure to $H_2O$. Growth initiation by TMA exposure, and subsequent growth inhibition are observed. A discrete time model of ALD is used to analyze the measured decay in reflected intensity.

A study of low-pressure chemical vapor deposition LPCVD of GexSi1−x x 0.65 films was carried out. The films were deposited on thermally oxidized silicon wafers at deposition temperatures of 430–480°C. Pure GeH4 and SiH4 or Si2H6 gas sources were used. It has been found that the reactive sticking probability ratio between GeH4 and SiH4 varies between 11 and 3.5, depending on both the deposition temperature and film composition. An increase of germanium content from 40 to 60 atom % caused a sharp increase of deposition rate. The polycrystalline layers mainly contained 110- and 111-oriented grains. The 111-oriented grains were overgrown by the 110-oriented grains at 430°C after a film thickness of about 100 nm. Reducing the total pressure below 10 Pa led to a dominance of 111-oriented grains. A relative GeH4 depletion in the downstream direction influenced both the composition and crystallinity of the layers, and the deposition rate. To minimize the depletion effect, Si2H6 has been used instead of SiH4. No improvement has been obtained but the depletion from Si2H6 occurred instead of the depletion from GeH4. A proper mixture of SiH4, Si2H6, and GeH4 can be suggested to compensate the depletion effects. © 2006 The Electrochemical Society. DOI: 10.1149/1.2177006 All rights reserved.

A simulation study on a new rectifier concept is presented. This device basically consists of two gates with different workfunctions on top of a thin intrinsic or lowly doped silicon body. The workfunctions and layer thicknesses are chosen such that an electron plasma is formed on one side of the silicon body and a hole plasma on the other, i.e., a charge plasma p-n diode is formed in which no doping is required. Simulation results reveal a good rectifying behavior for well-chosen gate workfunctions and device dimensions. This concept could be applied for other semiconductor devices and materials as well in which doping is an issue.

The fabrication of electronic devices at relatively low temperatures (100-150°C) is becoming increasingly important. It is possible to fabricate devices on glass or polymer substrates at low temperatures, or one can add extra functionality to standard ICs through post-processing. In order to realize good devices, we need to fabricate high-electrical quality dielectrics and semiconductors, which is a challenge at such low temperatures. Plasma-enhanced chemical vapor deposition allows SiO2 films to deposit at temperatures of around 400°C and lower. It is an experimental fact, however, that a low deposition temperature results in a degradation of the film properties. This degradation can be minimized partly by using high-density remote plasma (HDRP) reactors, as these reactors are capable of operating at lower pressures, thereby reducing gas-phase nucleation. They can also maintain higher plasma densities, thus enabling a higher rate of electron-stimulated reactions.

The fabrication of electronic devices at relatively low temperatures (100-150°C) is becoming increasingly important. It is possible to fabricate devices on glass or polymer substrates at low temperatures, or one can add extra functionality to standard ICs through post-processing. In order to realize good devices, we need to fabricate high-electrical quality dielectrics and semiconductors, which is a challenge at such low temperatures. Plasma-enhanced chemical vapor deposition allows SiO2 films to deposit at temperatures of around 400°C and lower. It is an experimental fact, however, that a low deposition temperature results in a degradation of the film properties. This degradation can be minimized partly by using high-density remote plasma (HDRP) reactors, as these reactors are capable of operating at lower pressures, thereby reducing gas-phase nucleation. They can also maintain higher plasma densities, thus enabling a higher rate of electron-stimulated reactions.

Titanium nitride (TiN) films are formed in a batch reactor using titanium chloride (TiCl4) and ammonia (NH3) as precursors. The TiCl4 is flowed into the reactor in temporally separated pulses. The NH3 can also be flowed into the reactor in temporally spaced pulses which alternate with the TiCl4 pulses, or the NH3 can be flowed continuously into the reactor while the TiCl4 is introduced in pulses. The resulting TiN films exhibit low resistivity and good uniformity.

We present a new lateral Schottky-based rectifier called the charge-plasma diode realized on ultrathin silicon-on-insulator. The device utilizes the workfunction difference between two metal contacts, palladium and erbium, and the silicon body. We demonstrate that the proposed device provides a low and constant reverse leakage-current density of about 1 fA/μm with ON/OFF current ratios of around 107 at 1-V forward bias and room temperature. In the forward mode, a current swing of 88 mV/dec is obtained, which is reduced to 68 mV/dec by back-gate biasing.

The number of transistors in integrated circuits is exponentially increasing over time, as predicted by Gordon Moore in the 1960s (e.g. 781 million transistors in the current Intel Xeon processor). This leads to higher computing power at a reduced cost per function. However, the future scaling perspective encounters several limiting factors, such as: an increased interconnect resistance-capacitance (RC) delay, enormous power densities – the so-called “power wall��?, and exploding costs due to the high process complexity. Therefore, further functionality growth within conventional planar ICs would not be possible without compromising on performance or cost, requiring drastic changes in the production process. Three-dimensional (3-D) integration of ICs, as already foreseen in the same ‘60s but thus far kept in the periphery of semiconductor technology, is nowadays gaining attention as an alternative to further lateral downscaling. It is highly attractive for application in mobile computing devices, where various functionalities have to be added to a single die to keep the system’s dimensions small.

The performance of Si integrated circuits depends on the transistor drive current. The drive current of a MOS transistor is determined by the total device resistance, which consists of the channel resistance and the parasitic resistances associated with dopant diffusion areas and contacts. It is expected that the contact resistance between silicide and source/drain regions will significantly contribute to the total series resistance. The reduction of this contact resistance and the corresponding specific contact resistance is an important issue. Thus the ability to accurately obtain the specific silicide-to-silicon contact resistance is essential for contact processing. It therefore requires dedicated test structures and a reliable extraction method of this specific contact resistance.

Thin TiN films have many important applications in Integrated Circuit (IC) technology. In spite of its chemical inertness, it is reported that TiN can be oxidized when exposed to oxidants (O2, H2O, etc.). To avoid an undesired oxidation of the metal-nitride layers, a study on this process is necessary. In this work, we present our study on thermal atomic layer deposition (ALD) of TiN films followed by their dry oxidation in oxygen ambient. For both processes, in-situ monitoring by spectroscopic ellipsometry is carried out.

Thin TiN films have many important applications in Integrated Circuit (IC) technology. In spite of its chemical inertness, it is reported that TiN can be oxidized when exposed to oxidants (O2, H2O, etc.). To avoid an undesired oxidation of the metal-nitride layers, a study on this process is necessary. In this work, we present our study on thermal atomic layer deposition (ALD) of TiN films followed by their dry oxidation in oxygen ambient. For both processes, in-situ monitoring by spectroscopic ellipsometry is carried out.

MicroElectroMechanical Systems (MEMS) is an emerging class of microfabrication technology that can truly be anticipated as an enabling technology for future radio frequency (RF) communications. This work focuses on the material selection using the Ashby approach for the high-Q resonators that need to be monolithically post processed on top of CMOS chip conforming to the requirement of thermal budget, stress and plasma induced damages for post processing.

MicroElectroMechanical Systems (MEMS) is an emerging class of microfabrication technology that can truly be anticipated as an enabling technology for future radio frequency (RF) communications. This work focuses on the material selection using the Ashby approach for the high-Q resonators that need to be monolithically post processed on top of CMOS chip conforming to the requirement of thermal budget, stress and plasma induced damages for post processing.

In this work we are looking at the prospect of using poly-silicon based Thin Film Transistors (TFTs) as photodetectors for optical interconnects that can detect light effectively at 1100nm wavelength from silicon based Light Emitting Diodes (LEDs). These TFTs were fabricated from laser crystallized silicon and were characterized under darkness and illumination. The photosensitivities of these devices were limited due to the presence of aluminium as their gate electrode but have shown us the possibility of a new approach to photodetection.

In this work we are looking at the prospect of using poly-silicon based Thin Film Transistors (TFTs) as photodetectors for optical interconnects that can detect light effectively at 1100nm wavelength from silicon based Light Emitting Diodes (LEDs). These TFTs were fabricated from laser crystallized silicon and were characterized under darkness and illumination. The photosensitivities of these devices were limited due to the presence of aluminium as their gate electrode but have shown us the possibility of a new approach to photodetection.

After nearly forty-five years of scaling driven by Moore's Law, the silicon microelectronics world is now defined by length scales that are some ten times smaller than the dimensions of typical micro-optical components. This size mismatch poses an important challenge for those working to integrate photonics with CMOS technology. One promising solution is to move from optical components made with dielectric materials to metal-dielectric interfaces, where optical modes called surface plasmon polaritons (SPPs) offer unique opportunities to confine and control light [1]. Research groups working in the rapidly developing field of plasmonics have now demonstrated many passive components that suggest the potential of SPPs for applications in sensing and integrated optical communication. Recently, the first active plasmonic devices based on III-V materials [2] and organic materials [3] have been reported. Here we demonstrate that a silicon-based electrical source for SPPs can be fabricated using established microtechnology processes that are compatible with backend CMOS technology.

Phase Change Random Access Memory (PCRAM) is investigated as replacement for Flash. The memory concept is based on switching a chalcogenide from the crystalline (low ohmic) to the amorphous (high ohmic) state and vice versa. Basically two memory cell concepts exist: the Ovonic Unified Memory (OUM) and the line cell. Switching to the high ohmic or low ohmic state is done using Joule heating. A relatively short (~ns) electrical pulse with large amplitude is used to heat the crystalline phase to melt and quench into the amorphous state (RESET). A pulse with smaller amplitude heats the amorphous region above its crystallization temperature (lower than the melting temperature) and the material returns into the crystalline state (SET). In the OUM cell this will be at the electrode-phase change material contact, whereas for the line cell this will be at the position where the current density is the highest.

TiN is a material, which is increasingly used in IC technology as a diffusion barrier, gate material, current conductor, and antireflective coating. In MEMS, TiN is used as a heater for micro hotplates. The important applications of TiN are based on its well-known high thermodynamic stability, high corrosion resistance, low friction constant, relatively low electrical resistivity, and high mechanical hardness. Thin and ultra-thin TiN layers, realized by ALD technique, attract growing attention due to its high quality and possibility to control layer thickness on nanometer scale. To provoke the use of such ALD TiN in novel electron devices and establish new routes to material and device fabrication, modification of TiN properties at elevated temperatures in chemically reactive ambient (e.g. oxidizing and reducing ambient such as thermal-oxidation furnaces, oxygen- and hydrogen-containing plasmas) needs to be investigated.

TiN is a material, which is increasingly used in IC technology as a diffusion barrier, gate material, current conductor, and antireflective coating. In MEMS, TiN is used as a heater for micro hotplates. The important applications of TiN are based on its well-known high thermodynamic stability, high corrosion resistance, low friction constant, relatively low electrical resistivity, and high mechanical hardness. Thin and ultra-thin TiN layers, realized by ALD technique, attract growing attention due to its high quality and possibility to control layer thickness on nanometer scale. To provoke the use of such ALD TiN in novel electron devices and establish new routes to material and device fabrication, modification of TiN properties at elevated temperatures in chemically reactive ambient (e.g. oxidizing and reducing ambient such as thermal-oxidation furnaces, oxygen- and hydrogen-containing plasmas) needs to be investigated.

SiO2 gate dielectric layers (4–60 nm) were grown (0.6 nm/min) by plasma-enhanced chemical vapor deposition (PECVD) in strongly diluted silane plasmas at low substrate temperatures. In contrast to the well-accepted positive charge for thermally grown silicon dioxide, the net oxide charge was negative and a function of layer thickness. Our experiments suggested that the negative charge was created due to unavoidable oxidation of the silicon surface by plasma species, and the CVD component added a positive space charge to the deposited oxide. The net charge was negative under process conditions where plasma oxidation played a major role. Such conditions include low deposition rates and the growth of relatively thin layers.

By enforcing layer thickness variations of an amorphous silicon thin film, the location of grain boundaries after laser annealing can be controlled to great extend. This allowes the positioning of TFTs in between the main crystal boundaries, offering high mobility and low transistor-to-transistor variability. In this paper we present our latest results on this subject including improved NMOS and PMOS mobility, inverter characteristics, and fully functional 51-stage ring oscillators with oscilliation frequencies in MHz-range.

By enforcing layer thickness variations of an amorphous silicon thin film, the location of grain boundaries after laser annealing can be controlled to great extend. This allowes the positioning of TFTs in between the main crystal boundaries, offering high mobility and low transistor-to-transistor variability. In this paper we present our latest results on this subject including improved NMOS and PMOS mobility, inverter characteristics, and fully functional 51-stage ring oscillators with oscilliation frequencies in MHz-range.

Planar inter-digitated comb capacitor structures are an excellent tool for on-chip capacitance measurement and evaluation of properties of coating layers with varying composition. These comb structures are easily fabricated in a single step in the last metallization layer of a standard IC process. Capacitive coupling of these structures with a coating layer is modelled based on the electric field distribution to have a detailed understanding of contributing capacitance components. The coating composition is optimized to provide maximum spread in capacitance values of comb capacitor structures. This spread in measured capacitance values can be used to implement a physical uncloneable function (PUF). A PUF is a random function which can be evaluated only with the help of a physical system. We present an on-chip capacitive PUF for chip security and data storage in which the unlock key algorithm is generated from capacitors which are physically linked to the chip in an inseparable way. The strength of this key increases with the spread in capacitance values and measurement accuracy.

We present our investigations on the fabrication of ohmic and Schottky contacts of several metals on lowly doped bulk Si and SOI wafers. Through this paper we evaluate the fabrication of rectifying devices in which no doping is intentionally introduced.

We present our investigations on the fabrication of ohmic and Schottky contacts of several metals on lowly doped bulk Si and SOI wafers. Through this paper we evaluate the fabrication of rectifying devices in which no doping is intentionally introduced.

Barium strontium titanate with different compositions is deposited using wet-chemical processing on a glass planarization layer, on top of alumina substrates. Three samples were fabricated with BaxSr1-xTiO3 (BST) with the barium content x varying between 0.8 and 1. The poly-crystalline films are 530 ± 12 nm thick. The optimization in terms of permittivity and quality factor is explored for barium strontium titanate on alumina substrates. The trade-off between the permittivity and quality factor (at 1 GHz) is investigated. Our results show that wet-chemical processing on glass-planarized alumina results in a quality factor between 21–27 at 1 GHz and a tuning ratio from 1.8 to 2.0 at an electric field of 0.4 MV/cm.

Barium strontium titanate with different compositions is deposited using wet-chemical processing on a glass planarization layer, on top of alumina substrates. Three samples were fabricated with BaxSr1-xTiO3 (BST) with the barium content x varying between 0.8 and 1. The poly-crystalline films are 530 ± 12 nm thick. The optimization in terms of permittivity and quality factor is explored for barium strontium titanate on alumina substrates. The trade-off between the permittivity and quality factor (at 1 GHz) is investigated. Our results show that wet-chemical processing on glass-planarized alumina results in a quality factor between 21–27 at 1 GHz and a tuning ratio from 1.8 to 2.0 at an electric field of 0.4 MV/cm.

The ubiquitous deploying of wireless electronic devices due to pervasive computing results in the idea of Energy Scavenging, i.e., harvesting ambient energy from surroundings of the electronic devices [1]. As an approach to the most practical realization of such an energy scavenger, copper indium gallium selenium (CIGS) thin-film solar cells have attracted much attention due to the possibility to combine their reasonably high efficiency and low-temperature fabrication technology. The CIGS solar cells can be realized using CMOS compatible technology and are therefore suitable for CMOS post-processing and for their integration on a silicon chip as the energy scavenger.

In this work, we realize light emitting functional multilayer (Al2O3 / Si-nanocrystals (Si-NC)) stacks at low temperatures (300-325 °C) by a combination of ALD and CVD techniques. The multilayer structure was obtained by a sequential deposition of a 20 nm-thick ALD Al2O3 film, followed by LPCVD of a Si-NC layer, without vacuum break. A high nanocrystal density was achieved through an enhanced nucleation rate by using trisilane (Si3H8, known as Silcore®) as precursors for LPCVD of Si-NC layers. The photoluminescence and electroluminescence of the functional multilayer stacks were measured. A decrease of the Si-NC deposition time (i.e. smaller size of Si-NC’s) provided a gradual shift of the photoluminescence peak to higher photon energies, indicating exciton confinement in the nanocrystals.

Silicon dioxide films were deposited by means of remote inductively coupled plasma enhanced chemical vapor deposition (ICPECVD) in Ar-N2O-SiH4 plasma at 150 °C and pressures between 1 and 6 Pa. The gas phase contained 0.08% of SiH4 and 18% of N2O. We observed that, at a total pressure of 1 Pa, the oxide films were formed with a density equal to that of thermally grown oxide. The films had a low oxide charge. Deposition at higher pressures resulted in the formation of oxides having a lower density than the film deposited at 1 Pa, and a higher oxide charge. We measured a strong dependence of the oxide charge on the film thickness. The films deposited at 1 Pa further exhibited leakage currents at an electric field strength of 6.5 MV/cm which were comparable to the leakage currents known for thermally grown (1000°C) oxides. The film deposited at 2 Pa also exhibited a low leakage current, but the current increase was observed at lower electric fields compared to the 1 Pa film. The films deposited at 6 Pa exhibited significantly higher leakage currents.

The contact resistance between two materials is dependent on the intrinsic properties of the materials in contact and the presence and properties of an interfacial layer at the contact. This article presents the difference in contact resistance measurements with and without the presence of a process limiting interfacial layer. These measurements are performed using Cross Bridge Kelvin Resistor (CBKR) test structures on TiW- Phase Change Material (PCM) contacts.

The ubiquitous deploying of wireless electronic devices due to pervasive computing results in the idea of Energy Scavenging, i.e., harvesting ambient energy from surroundings of the electronic devices [1]. As an approach to the most practical realization of such an energy scavenger, copper indium gallium selenium (CIGS) thin-film solar cells have attracted much attention due to the possibility to combine their reasonably high efficiency and low-temperature fabrication technology. The CIGS solar cells can be realized using CMOS compatible technology and are therefore suitable for CMOS post-processing and for their integration on a silicon chip as the energy scavenger.

We propose a new device concept called charge plasma (CP) diode [1]. The diodes are with metal/silicided contacts of different workfunctions and thin intrinsic region in between. The workfunctions and layer thicknesses are chosen such that an electron plasma is formed on one side of the silicon body and a hole plasma on the other, i.e. a CP p-n diode is formed. The main advantages of these devices are low temperature budget and no dopant implantation is necessary in thin silicon layers [2,3,4]. We begin by discussing some important results from our silicon p-i-n diodes before moving on to the novel device concept of CP diodes.

We propose a new device concept called charge plasma (CP) diode [1]. The diodes are with metal/silicided contacts of different workfunctions and thin intrinsic region in between. The workfunctions and layer thicknesses are chosen such that an electron plasma is formed on one side of the silicon body and a hole plasma on the other, i.e. a CP p-n diode is formed. The main advantages of these devices are low temperature budget and no dopant implantation is necessary in thin silicon layers [2,3,4]. We begin by discussing some important results from our silicon p-i-n diodes before moving on to the novel device concept of CP diodes.

Silicon dioxide films were deposited by means of remote inductively coupled plasma enhanced chemical vapor deposition (ICPECVD) in Ar-N2O-SiH4 plasma at 150 °C and pressures between 1 and 6 Pa. The gas phase contained 0.08% of SiH4 and 18% of N2O. We observed that, at a total pressure of 1 Pa, the oxide films were formed with a density equal to that of thermally grown oxide. The films had a low oxide charge. Deposition at higher pressures resulted in the formation of oxides having a lower density than the film deposited at 1 Pa, and a higher oxide charge. We measured a strong dependence of the oxide charge on the film thickness. The films deposited at 1 Pa further exhibited leakage currents at an electric field strength of 6.5 MV/cm which were comparable to the leakage currents known for thermally grown (1000°C) oxides. The film deposited at 2 Pa also exhibited a low leakage current, but the current increase was observed at lower electric fields compared to the 1 Pa film. The films deposited at 6 Pa exhibited significantly higher leakage currents.

The contact resistance between two materials is dependent on the intrinsic properties of the materials in contact and the presence and properties of an interfacial layer at the contact. This article presents the difference in contact resistance measurements with and without the presence of a process limiting interfacial layer. These measurements are performed using Cross Bridge Kelvin Resistor (CBKR) test structures on TiW- Phase Change Material (PCM) contacts.

In this work, we realize light emitting functional multilayer (Al2O3 / Si-nanocrystals (Si-NC)) stacks at low temperatures (300-325 °C) by a combination of ALD and CVD techniques. The multilayer structure was obtained by a sequential deposition of a 20 nm-thick ALD Al2O3 film, followed by LPCVD of a Si-NC layer, without vacuum break. A high nanocrystal density was achieved through an enhanced nucleation rate by using trisilane (Si3H8, known as Silcore®) as precursors for LPCVD of Si-NC layers. The photoluminescence and electroluminescence of the functional multilayer stacks were measured. A decrease of the Si-NC deposition time (i.e. smaller size of Si-NC’s) provided a gradual shift of the photoluminescence peak to higher photon energies, indicating exciton confinement in the nanocrystals.

Optically active silicon nanocrystals can be incorporated in alumina (Al2O3) using low-temperature CMOS-compatible processing. Luminescence is tentatively attributed to exciton recombination in silicon nanocrystals and associated oxygen related surface states.

Optically active silicon nanocrystals can be incorporated in alumina (Al2O3) using low-temperature CMOS-compatible processing. Luminescence is tentatively attributed to exciton recombination in silicon nanocrystals and associated oxygen related surface states.