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The origin of a greater decrease in kink drain voltage $V_{kink}$ in floating body PD-SOI MOSFETs with gate lengths shorter than $0.35 ~\mu m$ is newly revealed. The $V_{kink}$ formula as a function of the internal body voltage and $I_{DS}$ is derived by combining the modified impact ionization multiplication factor with the body-source junction I-V equation. The parameters in this formula are extracted from the measured data of $I_{B}$ vs. $V_{BS}$ and ${- I}_{B}/I_{DS}$ vs. $V_{DS}$ in the body contacted devices. By calculating the formula using the extracted parameters, it is newly found that a decrease of the drain-source saturation voltage at a shorter channel is a primary cause for the short-channel effect on $V_{kink}$ reduction.

This paper presents the results of charge-pumping measurements of SOI MOSFETs. The aim of these measurements is to provide information on the density of interface traps at the front and back Si-SiO2 interface. Three-level charge-pumping is used to obtain energy distribution of interface traps at front-interface

his paper presents a complete study of the impactof mechanical stress on the performance of SOI MOSFETs.This investigation includes dc, analog and RF characteristics.Parameters of a small-signal equivalent circuit are also ex-tracted as a function of applied mechanical stress. Piezore-sistance coefficient is shown to be a key element in describingthe enhancement in the characteristics of the device due tomechanical stress.

In this paper, a SOI MOSFET is proposed using a P-N structure and an electrically hole-free region (EHFR-SOI). In this structure, to improve the electrical characteristics such as short channel effects, self-heating effects, and floating body effects, a Si3N4 layer is used on the source side of the SOI MOSFET with a P-N structure. The proposed technique converts the P-N structure to a N-P-N structure by creating an electrically hole-free region. So, by reducing the applied electric field to the carriers, a significant reduction in the electron temperature of the device will be created. Simulations and studies of the structure show that its thermal behavior is significantly improved. Also, the floating body effect, effective mobility, hot electron effect, and electric field in the structure are enhanced compared to a conventional SOI (C-SOI) structure. In addition, the gate-source and gate-drain capacitors have been improved, which indicates a higher switching speed of the structure. [ABSTRACT FROM AUTHOR]

This article proposes an optimized device structure using undoped Multi Bridge Channel (MBC) Silicon on Insulator (SOI) based MOSFET analyzed at sub 10 nm channel length. Two stacked channels, one with Gate All Around and the other with TriGate structure on SOI, have been implemented. The structure has its different characteristics examined using various high-k dielectrics, and Subthreshold Swing (SS), Gate Induced Drain Leakage (GIDL) are also reported. The behavior of device parameters like potential and IV characteristics have been reported upon effect of different gate oxides. Sentaurus Technology Computer Aided Design (TCAD) was used to analyse the device, which took into account Schrodinger and the Density Gradient Model. By using HfO2 as a dielectric, the double channel device produces about 63% more output current than when SiO2 is used. Ion/Ioff ratio has been controlled by the maximum k value. Circuitry has been further developed, by improvising this design into an inverter and an SRAM circuit, and testing the parameters using various dielectrics. There is a 40% improvement in read mode and 5% improvement in write mode while using k = 23 compare with k = 3.9. [ABSTRACT FROM AUTHOR]

U-channel ultra-thin body and buried oxide (U-UTBB) Silicon On Insulator (SOI) Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) present unique features which are simple, high-performance, area efficient, and compatible with CMOS technology. In this paper, we present the electrical characteristics of a U-UTBB SOI MOSFET with reforming the U-channel. This proposed symmetrical and planar device is initiated by removing two spacers around the recessed metal gate in the U-channel MOSFET. Hence, it causes to increase the overall channel length at the firm metal gate space along with saving area. As it has confirmed by two-dimensional and two-carrier device simulation results, the proposed structure which is termed Reformed U-UTBB (R-U-UTBB) fully depleted SOI MOSFET exhibits advantages in the device performance focusing on short channel effects (SCEs) factors including the sub-threshold slope, the drain induced barrier lowering (DIBL), and the threshold voltage roll-off. Leakage current and on-to-off current ratio are studied as well which all of them show the superiority of proposed structure compared with the U-UTBB FD SOI MOSFET and a conventional UTBB (C-UTBB) FD SOI MOSFET. In addition, the effects of process-induced variations have investigated by varying buried oxide thickness, top silicon thickness, channel thickness, substrate doping, and oxide thickness on threshold voltage, sub-threshold slope, and drain induced barrier lowering (DIBL). [ABSTRACT FROM AUTHOR]

In this work, we aim to design a silicon on insulator MOSFET in which the self-heating effect is fully removed. Within the proposed scheme, a T-shaped 4H-SiC region is embedded in the buried oxide layer, extended from the silicon drift region towards the substrate providing a heating pathway to improve the low thermal conductivity of the oxide. This T-shaped 4H-SiC part can absorb heat from the active region and transfer it to the substrate area. Therefore, heat dissipation rising from the high gate and drain bias in MOSFETs are reduced. Simulations show that in addition to the maximum lattice temperature that is brought from ~ 694 K to ~ 366 K, DC and AC characteristics of the device have also improved drastically. The proposed transistor demonstrates lower negative differential resistance, more carrier mobility, higher saturation current, higher DC Transconductance, less delay time, and higher cut-off frequency compared to conventional silicon on insulator MOSFET. These promising properties and competitive advantages propose the designed device as a reliable alternative for conventional MOSFETs in high power and RF applications. [ABSTRACT FROM AUTHOR]

This paper presents an efficient method to improve the heating effects in Nanoscale SOI MOSFET with the Vertical Gaussian Doping Profile in Drain and Source regions (D-S-G-SOI). Three different structures are investigated: uniform drain (C-SOI), Gaussian drain doping profile (D-G-SOI) SOI MOSFET, and drain-source region with Gaussian doping profile (D-S-G-SOI) and results are compared. Gaussian doping function parameters like standard variation (σ) are used in our study. The proposed structure has been compared with other structures in terms of the lattice temperature, sub-threshold slope, electric potential, electric field, DIBL, leakage current, and floating body (Kink effect). Our results show the excellent electrical and thermal performance of the proposed structure taken account of as a proper substitution for the conventional device. [ABSTRACT FROM AUTHOR]

The present endeavor attempts to develop an explicit threshold voltage model of linearly graded work function engineered Silicon-On-Insulator MOSFET considering the effects of localized charges trapped at front high-k gate stack/channel and buried oxide layer/channel interfaces. As the accumulation of such equivalent oxide charges modulate the flat band voltage and alter the threshold voltage characteristics of the device, the inclusion of such effects is inexorable while formulating its analytical model. Hence, analytical methodology based extensive study of the potential distribution and threshold voltage behavior of the device affected by positive/negative trapped charges is demonstrated here by varying the channel thickness, high-k dielectrics and drain bias with subsequent comparison with a fresh SOI MOSFET equivalent. All analytical corollaries are compared with relevant ATLAS simulated data to corroborate the eminence of the derived model. [ABSTRACT FROM AUTHOR]

In this paper, the diode characteristics of our newly proposed super-steep subthreshold slope “PN-body tied (PNBT) silicon-on-insulator field-effect transistor” are presented, and compared with conventional diodes. We report that the device possesses super-steep characteristics, low leakage current, and sharp turn-on characteristics, even in the ultralow voltage range (50 mV). These indicate that the PNBT diode can potentially be used in high-efficiency rectification for energy harvesting, particularly in situations where there is ultralow input power. In addition, the hysteresis characteristics and the slight shift of the voltage at zero current are confirmed as specific characteristics of PNBT diodes.

In this paper, n-channel and p-channel super-steep subthreshold slope (SS) PN-body tied (PNBT) silicon on insulator field-effect transistors (SOI-FETs) are demonstrated. The PNBT structure has a symmetrical source and drain structure. The devices show super-steep SS (< 1 mV/dec) characteristics while maintaining low off current (< 1 pA/ $\mu$ m) and high on/off ratio (up to 6 decades) with low drain voltage (Vd = ± 0.1 V), good output characteristics, and threshold voltage controllability. The devices have a body current and a hysteresis characteristic; however, these can be suppressed under proper device conditions. The operation mechanism of the PNBT SOI-FET is clarified by simulation, and an inherent thyristor on the PNBT structure plays a significant role. Both the p-channel and n-channel PNBT SOI-FET characteristics are discussed, and it is indicated that an ultralow power complementary metal-oxide-semiconductor can be realized by the PNBT SOI-FET.

For the first time, a leaky integrate-and-fire (LIF) neuron with both excitatory and inhibitory characteristics is demonstrated using a single MOSFET. No additional circuits such as comparator, reset circuit, or current-to-voltage converter as well as a membrane capacitor are needed, and thus the LIF neuron is realized with a footprint of 6 F2. Because of its gate terminal, neuron firing is selectively inhibited, which can improve the energy efficiency of the neuromorphic system by inducing sparse activity. Furthermore, the spiking property of the neuron can be controlled by the gate, which can provide additional room to enhance the classification accuracy. [ABSTRACT FROM AUTHOR]

A high resistivity PD‐SOI MOSFET equivalent circuit model including a parallel connection of intrinsic output capacitance and conductance with frequency‐dependent empirical equations is newly proposed to accurately simulate their abrupt change in the low‐frequency region. This new empirical model is superior to a conventional RC one, because equivalent circuit structure and parameter extraction process are simpler. Better agreements with measured Y22‐parameter are obtained for the new model than the conventional one. [ABSTRACT FROM AUTHOR]

Progress in the technology of submicron semiconductor device, which makes a short-channel and quantum effects, having equations of nonlinear modelling, leads to complicated and time-consuming calculations. In order to control these complexities and obtain the device characteristics according to device parameters, a faster method is needed. In this paper, a combinational algorithm is proposed for modelling a nano silicon-on-insulator metal–oxide–semiconductor field effect transistor (SOI MOSFET) characteristic. The proposed method shows the same device characteristics with lower input parameters. In this method, a combination of genetic algorithm (GA) and artificial neural network are used. Then quantum evolutionary algorithm (QEA) is employed instead of genetic algorithm (GA) for comparing and modifying algorithm. Results show that the algorithm's accuracy is 95% and 98% for test data of GA and QGA, respectively. Moreover, the reduction percentage of input parameters are 11% and 52% for GA and QEA, respectively. The simulation results represent that the implemented quantum genetic algorithm for prediction of device characteristics is more effective and accurate than GA. [ABSTRACT FROM AUTHOR]

A new compact model is introduced to determine the drain current of an experimental short-channel silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) analytically. The effective physical parameters of the experimental nanoscale SOI MOSFET were successfully extracted for the first time using an efficient search algorithm named particle swarm optimization (PSO) as a link between the analytical drain model and the experimental data. Seven important parameters, viz. the drain-induced barrier lowering, subthreshold swing, additional resistance at the source terminal, carrier velocity, low-field carrier mobility, and threshold voltage, were sought using the PSO algorithm to obtain the best fitness value. The results revealed that the application of this PSO strategy achieved an excellent match between the proposed drain current model and experimental data notwithstanding the initial values of the fitting parameters. Also, the internal node capacitances of the short-channel SOI MOSFET were successfully extracted for use in compact models of its small-signal operation. [ABSTRACT FROM AUTHOR]

• We proposed the DG PNBT SOI-FET, which introduces the 2nd gate electrode, and the BJT is replaced by PMOSFET. • The turn-on starts below 1 pA. • It shows remarkable features, both no hysteresis and a big I on / I off ratio. • The DG PNBT SOI-FET shows the sharp turn-off characteristics, which is the same with SOI-FET. In this study, we report the first fabrication results of the steep subthreshold slope new type "dual-gate PN-body tied silicon on insulator field effect transistor (DG PNBT SOI-FET)." It simultaneously shows no hysteresis and a big I on / I off ratio and also resolves the small leakage current during turn-off, which is one of the problems on "PNBT SOI-FET," we have already reported many data on it. The results indicate that DG PNBT SOI-FET will be the more suitable candidate for the steep slope device for future ultra-low power Internet-of-things (IoT) applications. [ABSTRACT FROM AUTHOR]

Today submicron silicon-on-insulator (SOI) MOSFET structures are widely used in different electronic components and also can be used as sensing elements in some applications. The development of devices based on the structures with specified characteristics is impossible without computer simulation of their electric properties. The latter is not a trivial task since many complicated physical processes and effects must be taken into account. In current study ensemble Monte Carlo simulation of electron and hole transport in deep submicron n-channel SOI MOSFET with 100 nm channel length is performed. The aim of the study is investigation of the influence of interband impact ionization process on the device characteristics and determination of the transistor operation modes when impact ionization process starts to make an appreciable influence on the device functioning. Determination of the modes is very important for adequate and accurate modeling of different devices on the basis of SOI MOSFET structures. Main focus thereby is maid on the comparison of the use of two models of impact ionization process treatment with respect to their influence on the transistor current-voltage characteristics. The first model is based on the frequently used Keldysh approach and the other one utilizes the results obtained via numerical calculations of silicon band structure. It is shown that the use of Keldysh impact ionization model leads to much faster growth of the drain current and provides earlier avalanche breakdown for the SOI MOSFET. It is concluded that the choice between the two considered impact ionization models may be critical for simulation of the device electric characteristics.

Because of the low thermal conductivity of the SiO 2 (oxide), the Buried Oxide (BOX) layer in a Silicon-On-Insulator Metal-Oxide Semiconductor Field-Effect Transistor (SOI MOSFET) prevents heat dissipation in the silicon layer and causes increase in the device lattice temperature. In this paper, a new technique is proposed for reducing Self-Heating Effects (SHEs). The key idea in the proposed structure is using a Silicon undoped Region (SR) in the nanoscale SOI MOSFET under the drain and channel regions in order to decrease the SHE. The novel transistor is named Silicon undoped Region SOI-MOSFET (SR-SOI). Due to the embedded silicon undoped region in the suitable place, the proposed structure has decreased the device lattice temperature. The location and dimensions of the proposed region have been carefully optimized to achieve the best results. This work has explored enhancement such as decreased maximum lattice temperature, increased electron mobility, increased drain current, lower DC drain conductance and higher DC transconductance and also decreased bandgap energy variations. Also, for modeling of the structure in the SPICE tools, the main characterizations have been extracted such as thermal resistance (R TH ), thermal capacitance (C TH ), and SHE characteristic frequency (f TH ). All parameters are extracted in relation with the AC operation indicate excellent performance of the SR-SOI device. The results show that proposed region is a suitable alternative to oxide as a part of the buried oxide layer in SOI structures and has better performance in high temperature. Using two-dimensional (2-D) and two-carrier device simulation is done comparison of the SR-SOI structure with a Conventional SOI (C-SOI). As a result, the SR-SOI device can be regarded as a useful substitution for the C-SOI device in nanoscale integrated circuits as a reliable device. [ABSTRACT FROM AUTHOR]

In this work, Gate-All-Around Nanowire MOSFETs have been studied at very low temperatures. DC behaviors have been investigated in the linear operation and saturation regions, giving access to several analog parameters. Static characteristics at 4.2 K and low polarization exhibit step- like variations of the drain current, which can be linked to energy subband scattering. First results on the impact of quantum transport mechanism on the low frequency noise are shown. Finally the low frequency noise spectroscopy has led to the identification of silicon film traps. [ABSTRACT FROM AUTHOR]

This work presents the performance and transport characteristics of vertically stacked p-type MOSFET SOI nanowires (NWs) with inner spacers and epitaxial growth of SiGe raised source/drain. The conventional procedure to extract the effective oxide thickness (EOT) and Shift and Ratio Method (S&R) have been adapted and validated through tridimensional numerical simulations. Electrical characterization is performed for NWs with [1 1 0]- and [1 0 0]-oriented channels, as a function of both fin width (W FIN ) and channel length (L). Results show a good electrostatic control and reduced short channel effects (SCE) down to 15 nm gate length, for both orientations. Effective mobility is found around two times higher for [1 1 0]- in comparison to [1 0 0]-oriented NWs due to higher holes mobility contribution in (1 1 0) plan. Improvements obtained on I ON /I OFF by reducing W FIN are mainly due to subthreshold slope decrease, once small and none mobility increase is obtained for [1 1 0]- and [1 0 0]-oriented NWs, respectively. [ABSTRACT FROM AUTHOR]

A nanoscale SOI MOSFET structure with enhanced gate control is provided in this article. The gate is positioned in the silicon region's center and surrounded by insulating HfO 2 and SiO 2. Using this structure, we attempt to enhance the gate control over the channel. Furthermore, the source connection is positioned horizontally within the silicon region to generate an electric field caused by the potential difference between the gate and the source junction in the channel region. In fact, in addition to enhanced control of the gate over the channel, the idea of utilizing gate and source connections within the silicon region has led to the maximum electron temperature shifting from the channel to the drain region. Also, generating an undoped silicon region has been feasible to lower the lattice temperature. In addition, the electrical characteristics of the proposed MOSFET in both DC and AC states will be improved. The electrical features such as effective mobility, hot electron effect, electric field, and self-heating effect have been improved. The proposed structure is designed for RF applications and is studied in the 1 MHz to 500 GHz range. The frequency characteristics of the proposed structure, like the gate-source and gate-drain capacitors, S parameters, maximum unilateral power gain, transducer power gain, minimum noise figure, and noise conductance have also been enhanced. • A nanoscale SOI MOSFET structure with enhanced gate control is provided. • The gate is positioned in the center of the silicon region. • The source connection is positioned horizontally within the silicon region. • An undoped silicon region has been feasible to lower the lattice temperature. • The structure is designed for RF applications and is studied in the 1 MHz to 500 GHz range. • The frequency characteristics of the proposed structure have also been enhanced. [ABSTRACT FROM AUTHOR]

This work presents a model parameter extraction method based on four-port network for RF SOI MOSFET modeling. The gate, drain, source and body terminals are served as four separate ports. Four-port measurement simplifies the determination of small-signal equivalent circuit model elements such as parameters related to the body terminal which become clear in the equivalent circuit analysis. The extraction method of the RF SOI MOSFET extrinsic parasitic elements was also presented. The accuracy of the model extraction was verified by measurement and simulation from 100 MHz to 20 GHz. [ABSTRACT FROM AUTHOR]

This paper presents an analytical threshold voltage model for back-gated fully depleted (FD), recessed-source drain silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs). Analytical surface potential models have been developed at front and back surfaces of the channel by solving the two-dimensional (2-D) Poisson's equation in the channel region with appropriate boundary conditions assuming a parabolic potential profile in the transverse direction of the channel. The strong inversion criterion is applied to the front surface potential as well as on the back one in order to find two separate threshold voltages for front and back channels of the device, respectively. The device threshold voltage has been assumed to be associated with the surface that offers a lower threshold voltage. The developed model was analyzed extensively for a variety of device geometry parameters like the oxide and silicon channel thicknesses, the thickness of the source/drain extension in the buried oxide, and the applied bias voltages with back-gate control. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained from ATLAS™, a 2-D device simulator from SILVACO. [ABSTRACT FROM AUTHOR]

In short-channel silicon-on-insulatormetal-oxidesemiconductor transistors (SOI MOSFETs) the high electric field near the drain increases the floating-body effect. The aim of this article is to introduce a novel structure that reduces the electric field near the drain, so improving the floating-body effect. In the proposed structure, a dual trench is created in the buried oxide exactly under the junctions of drain/source and channel and is filled with an n-type SiGe material. The dual trench regions absorb the electric field lines and hence, the electric characteristic significantly improve. The proposed structure is named as dual SiGe trench double gate SOIMOSFET. In addition, we observe a considerable improvement in self-heating effects due to the higher thermal conductivity of SiGe in comparison with silicon dioxide. [ABSTRACT FROM AUTHOR]

In this paper, we show how the breakdown voltage and the on-state resistance can be improved by controlling of the electric field in LDMOSs. Insertion of two regions with low doping densities at both ends of the drift region as the side walls (SW-LDMOS) to enhance the uniformity of the electric field profile is the main point of this work. Also, the proposed structure has an extra oxide adjacent to the gate sidewall at drain side. By applying voltage to the gate, the density of the accumulation layer around of the extra oxide region increases and the on-state resistance will decrease. Our results show that the on-state resistance of the proposed structure improves and we have the smoother electric field distribution which improves the breakdown voltage. [ABSTRACT FROM AUTHOR]

In this paper we introduce a novel Silicon on Insulator Metal Oxide Semiconductor Field Effect Transistor (SOI MOSFET) with an embedded silicon heat pass path in the buried oxide (HPP-SOI). As this silicon path in the buried oxide conducts the generated heat in the active silicon channel from the shortest and most efficient path, self-heating effect improves while the fabrication process of this structure will remain without complexity. Moreover, the introduction of dopants in the source side of the channel leads to improvement in the leakage current, subthreshold slope, DIBL and threshold voltage roll-off in comparison with conventional SOI MOSFET (C-SOI). As proposed HPP-SOI structure shows these positive features, this structure can be considered as a serious candidate in nanoscale high temperature integrated applications. [ABSTRACT FROM AUTHOR]

A novel structure such as nanoscale silicon-on-insulator (SOI) MOSFET with silicon embedded layer (SEL-SOI) is proposed to reduce self-heating effects (SHEs) successfully. The SEL as a useful heat sink with high thermal conductivity is inserted inside the buried oxide. The SEL acts like a heat sink and is therefore easily able to distribute the lattice heat throughout the device. We noticed excellent improvement in the thermal performance of the device using two-dimensional and two-carrier device simulation. Our simulation results show that SHE has been dramatically reduced in the proposed structure. In regard to the simulated results, the SEL-SOI structure has shown good performance in comparison with the conventional SOI (C-SOI) structure when utilised in the high temperature applications. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a novel technique to control the electric field in Lateral Diffused Metal Oxide Semiconductor (LDMOS) Field Effect Transistors, in order to increase the breakdown voltage. The key idea in this work is increasing the smoothness of the electric field by extra oxide (EO) on the gate sidewall at the drain side of a deep gate structure. The EO region effects on the breakdown voltage by uniformity of the electric field profile. Our results show that the electric field will be maximally flatted by optimization of EO region. Therefore, the proposed structure is called maximally flat deep gate LDMOS (MFDG-LDMOS). The novel features of MFDG-LDMOS are simulated and compared with a conventional LDMOS (C-LDMOS). Our results show that the breakdown voltage and the on-state resistance of the MFDG-LDMOS improve about 48% and 25% in comparison with the C-LDMOS, respectively. [ABSTRACT FROM AUTHOR]

Several physical phenomena specific to silicon-on-insulator metal-oxide-semiconductor field-effect transistors, such as floating body effects, self-heating, and substrate coupling, are described and modeled. Small-signal equivalent circuit of ultra-thin body and thin buried oxide and fin field effect transistor (FinFET) are extracted, and their radio frequency figures of merit as well as their advantages and limitations are presented. We demonstrate the importance of performing wideband characterization at the early stage of the technology development in order to identify the device weaknesses and come up with technological solutions to overcome those. With the ongoing downscaling of the metal-oxide-semiconductor devices, the surrounding of the transistor, that is, the contacts, the access lines, and the substrate, starts to play a major role on the transistor behavior. There is an urgent need to develop adequate models for the new generation of devices valid over a wide frequency band. [ABSTRACT FROM AUTHOR]

This paper introduces a novel reduced body charge technique in nanoscale partially depleted (PD) SOI MOSFETs by an P+-type embedded silicon region inside the buried oxide and beneath source and channel regions. The embedded region creates a proper path to release the body accumulated holes easily. Actually, the P+ embedded and N+ active silicon regions constitute an Esaki tunnel diode to release the body accumulated holes by tunnel current. This work has investigated the main characterizations such as the kink effect, short channel effects (SCEs), leakage current, gate induced drain leakage (GIDL), self-heating effect, subthreshold swing, voltage gain, unilateral power gain, and current gain which all of them show the superiority of our structure when compared with a conventional SOI MOSFET (C-SOI) in reliable low-voltage applications. All the achieved numerical results have been extracted by two-dimensional and two-carriers simulator ATLAS. [ABSTRACT FROM AUTHOR]

Highlights: [•] Electrical characteristics of UTB (46nm) and NSD (1.6nm) SOI-MOSFETs are compared. [•] Initial SOI channel is thinned down to 1.6nm using a recessed-gate process. [•] Drain current values were found surprisingly different by 3 orders of magnitude. [•] Two Y-function-based extraction methods of series resistance are used and compared. [•] Article’s novelty is that our methods are based on I DS − V GS measured for several V DS. [ABSTRACT FROM AUTHOR]

Highlights: [•] Electrical characteristics of UTB (46nm) and NSB (1.6nm) SOI-MOSFETs are compared. [•] Initial SOI channel is thinned down to 1.6nm using a recessed-gate process. [•] Drain current values were found surprisingly different by 3 orders of magnitude. [•] Such a huge contrast was not found coherent with the literature. [•] We built a useful model approach to interpret NSB anomalous electrical behavior. [ABSTRACT FROM AUTHOR]

In this article, we present the thermal characteristics of the MOSFET with SELBOX structure. It is observed that the device shows a reduction in the self-heating effect and exhibits improved static and dynamic thermal behavior. A thermal model is developed to explain the thermal behavior of SELBOX structure. The model was evaluated using simulation implemented by Silvaco TCAD tools. Results show the effectiveness of the structure for the minimization of the self-heating effect (SHE) observed in SOI devices. Further, the results obtained from the simulation studies fit into the model showing the validity of the thermal circuit model. [ABSTRACT FROM AUTHOR]

Highlights: [•] Proposal of a novel SOI MOSFET including an undoped region for improving the self-heating effect. [•] Improvement on global lattice temperature. [•] Improvement on main DC and AC characteristics. [•] Optimization and design consideration. [ABSTRACT FROM AUTHOR]

Abstract: Device performance in the electronic circuits degrades with elapsed time. Therefore it is important to design a new device to have a reliable performance. In this paper, we present the unique features exhibited by a novel nanoscale silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) in which the silicon active layer consists of an insulator region (IR-SOI). The high-K dielectric HfO2 as an insulator material is located in the silicon active layer and drain region. Our simulation results demonstrate that this leads to improve the hot electron reliability of the IR-SOI in comparison with the conventional SOI-MOSFET (C-SOI). The insulator region HfO2 considerably decreases the electric field in the channel and drain regions. Therefore, the degradation mechanism in the proposed structure is lower than that in the C-SOI structure because of reduction of hot carrier effect (HCE). Also using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the HCE, off current, gate current and gate induced drain leakage (GIDL) which can effect on the reliability of the CMOS devices. [Copyright &y& Elsevier]

The initiative to standardize compact (SPICE-like) modelling has recently gained momentum in the semiconductor industry. Some of the important issues of the compact modelling must be addressed, such as accuracy, testing, availability, version control, verification and validation. Most compact models developed in the past did not account for these key issues which are of highest importance when introducing a new compact model to the semiconductor industry in particular going beyond the ITRS roadmap technological 100 nm node. An important application for non-fully depleted SOI technology is high performance microprocessors, other high speed logic chips, as well as analogue RF circuits. The IC design process requires a compact model that describes in detail the electrical characteristics of SOI MOSFET transistors. In this paper a non-fully depleted SOI MOSFET model and its Verilog-AMS description will be presented.

Abstract: This paper describes a preliminary attempt with a semi-analytical model and a scaling scheme of the cross-current tetrode (XCT) silicon-on-insulator (SOI) MOSFET aiming at low energy-dissipation circuit applications. The channel-current model for XCT MOSFET is separated into an intrinsic MOSFET part and a parasitic junction-gate field-effect transistor (JFET) part. Models for MOSFET and JFET are proposed by taking the potential coupling between MOSFET and JFET. The later part of the paper introduces experiments on the original SOI nMOSFET and XCT nMOSFET. This paper stresses the fundamental operations and features of the XCT device structure. Calculation results of I–V characteristics from the semi-analytical model are compared with the measurement values. It is shown that the proposed model reproduces the measured values successfully. In addition, design guidelines for XCT devices and scaling issues are discussed from the viewpoint of performance control aiming at low energy-dissipation circuit applications. Finally, preliminary circuit simulation results of XCT CMOS devices are revealed to demonstrate the definite low-energy performance. [Copyright &y& Elsevier]

Abstract: The classical physics description long-channel undoped asymmetric independently driven double-gate MOSFETs channel potential has been modeled thus far by means of two types of equations consisting of either hyperbolic or trigonometric functions, as dictated by the applied bias conditions. Instead of such separate regional equations, we propose here the use of a single completely generic equation based on complex variables, which is valid for all values of front and back-gate bias. The unified nature of the proposed equation may be useful for future development of double-gate MOSFET modeling work because it provides a better basis for global physical insight. The solution of this equation is analyzed for several cases, including the all important fully symmetric one. [Copyright &y& Elsevier]

The acoustic phonon modulation (confinement) in semiconductor nanostructures and their interaction with electrons are reviewed. Special emphasis will be placed on free-standing and layered slabs, as well as nanowires. Analysis includes acoustic phonon dispersion relations, displacement wave functions, amplitudes, form factor, electron-phonon scattering rate, and electron mobility. [ABSTRACT FROM AUTHOR]

Abstract: This paper aims at presenting a detailed and comprehensive study of the influence of space-charge condition at the substrate/BOX interface, as a function of the gate length and substrate bias, on both the front threshold voltage () and subthreshold slope (S), for sub-32nm Ultra-Thin Body (UTB) SOI MOSFETs with two different BOX thicknesses: either standard 145nm (UTB) or thin 11.5nm (UTB2). This study details for the first time, the important impact of the substrate/BOX interface regime variations with gate length from 1μm down to 25nm, substrate bias and BOX thickness together, on the mean channel position into film and its related impact on the electrical parameters and S. Experimental results and conclusions are also completed and enlightened by ATLAS simulations and analytical modeling. [Copyright &y& Elsevier]

Abstract: This paper presents a detailed experimental study of the electrical characteristics of long-channel ultra-thin body SOI MOSFETs with standard and thin buried oxides and high-k gate dielectric, using an analysis of the transconductance, gate-to-channel capacitance and mobility behaviors at different back-gate biases. The emphasis is on the evolution of the effective mobility when shifting the conduction channel in the film from front to back interface, and on the comparison between the two BOX thicknesses. It is found that the back-channel mobility significantly exceeds the front-channel mobility, which is presumably related to strongly different Coulomb scattering at the two interfaces, being in agreement with previously published experimental studies. Furthermore, the back-channel mobility is found to be the same for thick and thin BOX. This strongly suggests that BOX thinning does not degrade the quality of the back interface. The observed effect of much higher back-channel mobility, which is retained for the thin BOX, could find application for the additional improvement of the device performance, when adjusting the threshold voltage via back-gate bias. Adequate mobility interpretation is then required as a varying combination of front and back-channel mobilities. [Copyright &y& Elsevier]

This paper presents a complete study of the impact of mechanical stress on the performance of SOI MOSFETs. This investigation includes dc, analog and RF characteristics. Parameters of a small-signal equivalent circuit are also extracted as a function of applied mechanical stress. Piezoresistance coefficient is shown to be a key element in describing the enhancement in the characteristics of the device due to mechanical stress. [ABSTRACT FROM AUTHOR]

Abstract: The confined states in strained silicon fully depleted silicon-on-insulator MOSFETs are investigated using full-band k.p method within the envelope-function approximation. Full-band calculations of important transport parameters – energy band shifts, curvature masses and density-of-state masses – show new results, rising the issues of the limit of simple models like the effective mass approximation and the 6-level k.p model. [Copyright &y& Elsevier]