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Materials technology co-optimization (MTCO) modeling is used for the first time to simulate Performance-Power-Area (PPA) benefits of self-aligned gate contact (SAGC) technology. We also demonstrate a process flow to integrate novel CMOS compatible materials and processes to enable SAGC at the 3nm node and below.

Electron devices based on field emitters (FE) are promising for harsh-environments and high-frequency electronics thanks to their radiation hardness and scattering-free electron transport. Si field emitters with a sub-10 nm tip radius and self-aligned gates have demonstrated sub-20 V turn-on operation [1] , [2] . However, stability and operating voltage still need further improvement to enable circuit applications. III-Nitrides are excellent candidates to overcome these issues because of their strong bonding energies [3] and tunable electron affinities [4] . So far, there are few demonstrations of III-Nitride field emitters with self-aligned gates, which are critical to reduce the gate-emitter voltage (V GE ). In this work, a novel GaN nanowire (NW) field emitter based on self-aligned gates is demonstrated to reduce the gate-emitter turn-on voltage (V GE, ON ) below 30 V. To the best of our knowledge, this represents the lowest control voltage in any GaN field emitter device, opening an opportunity for using III-N in integrated field emitters.

This paper presents a promising technology to make quantum-well InAs transistors on SiO2/Si substrate by using a self-aligned gate-last fabrication technique. The full self-aligned fabrication process is demonstrated, and the fabricated device is characterized. A 2-D TCAD simulation is then performed based on the experimental data to understand the operation of the InAs transistors. We explore further optimizations for this technology through TCAD simulations, and it is found that with optimizations in materials, device geometry and fabrication, significant boost in RF performances is possible with these devices.

We demonstrate a nonvolatile single transistor ferroelectric gate memory device with ultra-thin (5.5 nm) Hf0.8Zr0.2O2 (HZO) fabricated using a self-aligned gate last process. The FETs are fabricated using silicon-on-insulator wafers, and the ferroelectric is deposited with atomic layer deposition. The reported devices have an ON/OFF drain current ratio of up to 106, a read endurance of $>10^{10}$ read cycles, and a program/erase endurance of 107 cycles. Furthermore, healing of the transistor after gate insulator breakdown is demonstrated.

Beta-phase gallium oxide $(\beta-\mathrm{Ga}_{2}\mathrm{O}_{3})$ has shown promise as a next-generation wide-bandgap semiconductor for use in power electronics. It possesses a bandgap and expected critical field strength of ~4.8 eV and ~8 MV/cm, respectively, surpassing the same measured characteristics of GaN and SiC [1]. Early work has been successful in demonstrating lateral metal-oxide-semiconductor field-effect transistors (MOSFETs), predominately for depletion mode operation, with high critical field strength [2], high current density [3], and high breakdown voltage [4], [5]. One limitation of $\beta-\mathrm{Ga}_{2}\mathrm{O}_{3}$ MOSFETs is source access resistance $(\mathrm{R}_{\mathrm{S}})$ , the ungated region between source and gate, with sheet resistance $(\mathrm{R}_{\mathrm{SH}})$ typically in the $\mathrm{k}\Omega/\mathrm{sq}$ range. The $\mathrm{R}_{\mathrm{S}}$ affects key device performance parameters such as transconductance $(\mathrm{G}_{\mathrm{M}})$ and drain-current density $(\mathrm{I}_{\mathrm{DS}})$ . Higher DC and RF performance can be expected from eliminating $\mathrm{R}_{\mathrm{S}}$ by self-aligning the gate and source contacts. We present, for the first time, a self-aligned gate (SAG) $\beta-\mathrm{Ga}_{2}\mathrm{O}_{3}$ MOSFET using a refractory metal gate-first design. MOSFET devices with $2\mathrm{x}50\mu \mathrm{m}$ gate periphery, $7.5\ \mu \mathrm{m}$ source-drain distance $(\mathrm{L}_{\mathrm{SD}})$ and $2\ \mu \mathrm{m}$ gate length $(\mathrm{L}_{\mathrm{G}})$ were directly compared with and without the SAG features. MOSFETs with SAG show a substantial increase in $\mathrm{G}_{\mathrm{M}}$ and $\mathrm{I}_{\mathrm{DS}}$ , from ~2 mS/mm to ~14 mS/mm and ~10 mA/mm to ~45 mA/mm, respectively, up to $\mathrm{V}_{\mathrm{GS}}=4$ V. Lastly, we report a laterally scaled device $(2\mathrm{x}50\mu \mathrm{m})$ with $\mathrm{L}_{\mathrm{SD}}=2.5\mu \mathrm{m}$ and $\mathrm{L}_{\mathrm{G}}=2\mu \mathrm{m}$ , achieving high current density $(\sim 140\mathrm{mA}/\mathrm{mm})$ , and high G M $(\sim 35\mathrm{mS}/\mathrm{mm})$ .

The diffusion break (DB) induced layout effect is one of the major culprits for device variability and deteriorators for chip Vmin and Iddq. For the first time, the performance and leakage impacts from varied types of diffusion breaks are quantified at the device and chip critical path levels. The continuous diffusion with gate tie-down stands out as the best choice due to the superior N/P balance and lower variability caused by the layout effect. To implement the continuous diffusion at the advanced FinFET technology node, careful physical design at cell boundary is crucial, which is enabled by EUV to solve the contact via color conflict and by self-aligned gate contact (SAGC) to mitigate the gate to diffusion leakage risk.

Vertical nanowire n-type (InAs) and p-type (GaSb) transistors are co-processed and co-integrated using a gate-last process, enabling short gate-lengths (Lg = 40 nm) and allowing selective digital etching of the channel. Two different common gate-stacks, including various pre-treatments, were compared and evaluated. The process was optimized to achieve high n-type performance while demonstrating p-type operation. The best n-type device is scaled down to 12-nm diameter and has a peak transconductance of $2.6\ \text{mS/}\mu \text{m}$ combined with a low Ron of $317~\Omega \cdot \mu \text{m}$ , while the p-type exhibits $74~\mu \text{S}/\mu \text{m}$ . In spite of increased complexity due to co-integration, our n-type InAs transistors demonstrate increased drive current, $1.8\ \text{mA/}\mu \text{m}$ , compared with earlier publications.

As the scale of graphene-based non-volatile memory is reduced, the ratio of access resistance R A to total channel resistance R TOT is increased. To investigate the effect of the R A on I–V characteristics, we fabricated devices with various access lengths L A and self-aligned structure. Proposed structure using self-aligned gate minimises L A, and thereby improves the drain current, ‘on/off’ current ratio I ON/I OFF and transfer characteristics. In proposed structure, ‘off’ current is increased from 0.16 to 0.28 mA because R TOT was reduced; ‘on’ current increased from 0.35 to 0.72 mA, but I ON/I OFF increased from 2.18 to 2.57. Proposed structure also had larger memory window (8.5 V) than did conventional devices (6.7 V).

We report on the fabrication of highly uniform field emitter arrays (FEAs) with an integrated self-aligned extraction gate from bulk molybdenum. All critical dimensions of the emitter tip were determined by a single process step of Inductively Coupled Plasma (ICP) etching. In addition, the height difference between the emitter tip and the gate plane was controlled by the thickness of the SiO2 dielectric layer. A 10 µm gate aperture molybdenum-FEAs (Mo-FEAs) at a typical 20 µm pitch with 6 µm height was achieved with 8.4 mA/cm2 current density at gate voltages of 110 V and the turn-on field of 1.4 V/µm. These self-aligned Mo-FEAs could be expanded to active larger areas to increase the emission current.

In this paper, standard cell design for iN7 CMOS platform technology targeting the tightest contacted poly pitch (CPP) of 42 nm and a metal pitch of 32 nm in the FinFET technology is presented. Three standard cell architectures for iN7, a 7.5-Track library, 6.5-Track library, and 6-Track library have been designed. Scaling boosters are introduced for the libraries progressively: first an extra MOL layer to enable an efficient layout of the three libraries starting with 7.5-Track library; second, fully self aligned gate contact is introduced for 6.5 and 6-Track library and third, 6-Track cell design includes a buried rail track for supply. The 6-Track cells are on average 5% and 45% smaller than the 6.5 and 7.5-Track cells, respectively.

This paper demonstrates the fabrication of self-aligned gate-last enhancement- and depletion-mode (E/D-mode) AlN/GaN metal-oxide-semiconductor high-electron-mobility-transistors (MOSHEMTs). In addition, the effects of annealing on threshold voltage (Vth) are analyzed. The E and D-mode transistors were fabricated with Ni/Au and Ti/Au as the gate metal, respectively. The Ni/Au gated MOSHEMTs show Vth = +0.3 V after post-gate metallization annealing, and the Ti/Au gated MOSHEMTs without annealing show Vth= -1.8 V. In the E-mode (Ni/Au gated) transistors, the Vth shift after post-gate annealing is due to the decrease of fixed charges at the Al2O3/GaN interface. An investigation has been conducted for the understanding of the Vth shift, which is crucial for improving the transistors' stability in various applications. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Electrical characteristics of fully self-aligned gate overlapped lightly doped drain (FSA-GOLDD) polysilicon TFTs, fabricated with a spacer technology providing submicron (0.35 mu m) LDD regions, have been analyzed by using two-dimensional numerical simulations. The numerical analysis was used to explain the observed reduced kink effect and short channel effects presented by FSA GOLDD devices, compared to SA devices. The reduction of the kink effect has been attributed to the reduced impact ionization rate, and related to reduced electric fields at the channel/LDD junction. In addition, the role of the LDD dose on the kink effect has been also investigated, clarifying the observed current inflection occurring in the kink effect regime and the LDD dose dependence of the breakdown. Reduced short channel effects were attributed to reduced floating body effects, since drain induced barrier lowering was apparently not affected by the SA GOLDD structure, when compared to SA devices.

Self-aligned gate structures are preferred for faster operation and scaling down of thin film transistors by reducing the overlapped region between source/drain and gate electrodes. Doping on source/drain regions is essential to fabricate such a self-aligned gate thin film transistor. For oxide semiconductors such as In-Ga-Zn-O, SiNx capping readily increases their carrier concentration. We report that the SiNx deposition temperature and thickness significantly affect the device properties, including threshold voltage, field effect mobility, and contact resistance. The reason for these variations in device characteristics mainly comes from the extension of the doped region to the gated area after the SiNx capping step. Analyses on capacitance-voltage and transfer length characteristics support this idea.

By introducing high-K dielectrics and metal gate in our planar self-aligned gate-all-around (GAA) fabrication process, we have successfully fabricated sub-35 nm CMOS devices that exhibit high-performance drive currents (2230/1000 muA/ mum for N/ P at Vd = 1.2 V), low off-state currents (3/5 nA/mum), and excellent subthreshold characteristics. When benchmarked with other published multigate data, the results presented in this paper are proved to be among the best and underline the potential of planar self-aligned GAA devices for the 32 nm technology and below. In particular, it is demonstrated that an optimized supply voltage can bring a significant improvement in circuit time delay and power when using GAA devices.

The electrical properties of p- and n-MOS devices fabricated on germanium with metal-organic chemical-vapor-deposition HfO2 as gate dielectric and silicon passivation (SP) as surface treatment are extensively investigated. Surface treatment prior to high-K deposition is critical to achieve small gate leakage currents as well as small equivalent oxide thicknesses. The SP provides improved interface quality compared to the treatment of surface nitridation, particularly for the gate stacks on p-type substrate. Both Ge p- and n-MOSFETs with HfO2 gate dielectrics are demonstrated with SP. The measured hole mobility is 82% higher than that of the universal SiO2/Si system at high electric field (~0.6 MV/cm), and about 61% improvement in peak electron mobility of Ge n-channel MOSFET over the CVD HfO2 /Si system was achieved. Finally, bias temperature-instability (BTI) degradation of Ge MOSFETs is characterized in comparison with the silicon control devices. Less negative BTI degradation is observed in the Ge SP p-MOSFET than the silicon control devices due to the larger valence-band offset, while larger positive BTI degradation in the Ge SP n-MOSFET than the silicon control is characterized probably due to the low-processing temperature during the device fabrication

In this work, we present a novel self-aligned gate-last fabrication process for vertical nanowire metal-oxide-semiconductor field-effect transistors. The fabrication method allows for exposure dose-defined gate lengths and a local diameter reduction of the intrinsic channel segment, while maintaining thicker highly doped access regions. Using this process, InAs nanowire transistors combining good on- and off-performance are fabricated demonstrating Q = gm,max/SS = 8.2, which is higher than any previously reported vertical nanowire MOSFET.

Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In0.7Ga0.3As channel 50-nm self-aligned and "standard" T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system

Issues surrounding the integration of Hf-based high-/spl kappa/ dielectrics with metal gates in a conventional CMOS flow are discussed. The careful choice of a gate-stack process as well as optimization of other CMOS process steps enable robust metal/high-/spl kappa/ CMOSFETs with wide process latitude. HfO/sub 2/ of a 2-nm physical thickness shows a very minimal transient charge trapping resulting from kinetically suppressed crystallization. Thickness of metal electrode is also a critical factor to optimize physical-stress effects and minimize dopant diffusion. A high-temperature anneal after source/drain implantation in a conventional CMOSFET process is found to reduce the interface state density and improve the electron mobility. Even though MOSFET process using single midgap metal gate addresses fundamental issues related to implementing metal/high-/spl kappa/ stack, integrating two different metals on the same wafer (i.e., dual metal gate) poses several additional challenges, such as metal gate separation between n- and pMOS and gate-stack dry etch. We demonstrate that a dual metal gate CMOSFET yields high-performance devices even with a conventional gate-first approach if an appropriate metal separation between band-edge metal for nMOS and pMOS is incorporated. Optimization of dry-etch process enables gentle and complete removal of two different metal gate stacks on ultrathin high-/spl kappa/ layer.

We have developed a self-aligned Lg = 55 nm In0.53Ga0.47As MOSFET incorporating metal-organic chemical vapor deposition regrown n++ In0.53Ga0.47As source and drain regions, which enables a record low on-resistance of 199 Ωμm. The regrowth process includes an InP support layer, which is later removed selectively to the n++ contact layer. This process forms a high-frequency compatible device using a low-complexity fabrication scheme. We report on high-frequency measurements showing fmax of 292 GHz and ft of 244 GHz. These results are accompanied by modeling of the device, which accounts for the frequency response of gate oxide border traps and impact ionization phenomenon found in narrow band gap FETs. The device also shows a high drive current of 2.0 mA/μm and a high extrinsic transconductance of 1.9 mS/μm. These excellent properties are attributed to the use of a gate-last process, which does not include high temperature or dry-etch processes.

We investigated the lifetimes for various poly-Si thin film transistor (TFT) structures. A gate-overlapped lightly doped drain (GOLDD) structure was self-aligned by the side etching of Al-Nd in an Al-Nd/Mo gate electrode. The dopant activation process in the LDD regions of GOLDD TFTs was performed by using a H/sub 2/ ion-doping technique. We also observed the effect of lifetime on the source/drain activation process. The thermal annealing of the source/drain region was found to extend the lifetime. The predicted lifetime of our GOLDD poly-Si TFT is superior to those of non-lightly doped drain (non-LDD) and lightly-doped drain (LDD) poly-Si TFTs. The trapped-electron density at the drain junction after bias-stressing was also investigated using a two-dimensional (2-D) simulation.

The paper reports high-performance enhancement-mode MOS high-electron mobility transistors (MOS-HEMTs) based on a quaternary InAlGaN barrier. Self-aligned gate technology is used for gate recessing, dielectric deposition, and gate electrode formation. An improved digital recessing process is developed, and an Al2O3 gate dielectric grown with O2 plasma is used. Compared to results with AlGaN barrier, the fabricated E-mode MOS-HEMT with InAlGaN barrier delivers a record output current density of 1.7 A/mm with a threshold voltage (V TH) of 1.5 V, and a small on-resistance (R on) of 2.0 Ω·mm. Excellent V TH hysteresis and greatly improved gate leakage characteristics are also demonstrated.

In this study, titanium nitride (TiN) is synthesized using reactive sputtering for a self-aligned gate process. The Schottky barrier height of the TiN on n-GaN is around 0.5 to 0.6 eV and remains virtually constant with varying nitrogen ratios. As compared with the conventional Ni electrode, the TiN electrode presents a lower turn-on voltage, while its reverse leakage current is comparable with that of Ni. The results of annealing evaluation at different temperatures and duration times show that the TiN/W/Au gate stack can withstand the ohmic annealing process at 800°C for 1 or 3 min. Finally, the self-aligned TiN-gated AlGaN/GaN heterostructure field-effect transistors are obtained with good pinch-off characteristics.

We report combining plasma-enhanced atomic layer deposition (PEALD) ZnO thin-film transistors (TFTs) with a gate-self-aligned process to fabricate high-speed circuits. The speed of our previous PEALD circuits (22 ns/stage) was largely limited by the parasitic capacitance between the gate and drain, and a selfaligned-gate process provides higher speed devices and circuits. In this letter, a backside exposure process was used to fabricate gate-self-aligned TFTs with a mobility of 20 cm2/V · s. The seven-stage self-aligned-gate PEALD ZnO TFT ring oscillators had a propagation delay of 9.8 ns/stage at a supply voltage of 18 V. These ring oscillators are similar in performance to the best reported saturated-load oxide-semiconductor circuits but with much longer channel length (> 5× longer).

We present test data for several spiral inductors with improved quality factor fabricated on GaAs substrates using the ITT MSAG (multifunction self aligned gate) multilayer process. It is shown experimentally that the quality factor of spiral inductors can be enhanced by using thick metallization and placing inductors on a thick polyimide layer which is placed on top of the GaAs substrate. Using this technique we observed up to 68% improvement in the quality factor of spiral inductors as compared to standard spiral inductors. Inductors having thick metallization can also handle DC currents as large as 0.5 A. © 2000 John Wiley & Sons, Inc. Int J RF and Microwave CAE 10: 139–146, 2000.

The effect of thermal stress on the d.c. parameter degradation of enhancement mode tungsten nitride (WN x ) self-aligned gate GaAs MESFETs was investigated. Threshold voltage, source-drain current and transconductance were measured during the tests. The physical properties of the device after thermal stress were analyzed by means of Auger electron spectroscopy (AES), X-ray diffractometry to identify the degradation mechanism. The d.c. failure mode consists of an increase in the threshold voltage and a decrease in the current and transconductance of the FETs. The device simulator was also used for analytical understanding of the d.c. parameter degradation. The simulated results showed that d.c. parameter degradation was mainly attributed to the increase in source and drain ohmic contact resistances. From the AES analysis, we found that the increase of contact resistance was due to carrier compensation, which was caused by Ga outdiffusion and Ni indiffusion under the ohmic contact layer. Therefore the thermally activated carrier compensation effects by trap generation are proposed to be the main failure mechanism for d.c. parameter degradation of enhancement mode WN x self-aligned gate GaAs MESFETs.

Bias-temperature stress examinations of self-aligned 0.1 μm length gate GaAs MESFETs have revealed a shift of threshold voltage related to Si doping concentration near the gate sides next to the channel region. With lower doping concentration, the increase in threshold voltage in FETs was faster and a 100 mV increase leads to a 20% reduction of operation speed in digital ICs after forward-biased storage at 200°C. The recovery of the performance under reverse-biased stresses was observed. The degradation is released by increasing Si doping concentration and thus we obtained the prediction of a median life exceeding 10 6 h at 100°C by setting the Si dose of 4 × 10 13 cm −2 , which is as high as it can be set without causing serious reduction of breakdown voltage.

We propose a large-signal model that can simulate the power-added efficiency of p-pocket self-aligned gate GaAs MESFET's. This model includes a new drain current model and a gate bias-dependent RF output resistance to express the drain conductance and its frequency dispersion at each gate bias. In addition, gate-source and gate-drain capacitances are modeled by functions of two variables of gate and drain biases so as to fit the measured values of ion implanted channels. The simulated power-added efficiency agreed with the measured value with a maximum error of 5%. The intermodulation distortion was also simulated and the maximum difference between the simulated and measured results was reduced to one-fifth of the results simulated by the conventional model. Practical applications were demonstrated by the load-pull simulation and the /spl pi//4 shift QPSK-modulated signal simulation.

This paper describes a newly developed GaAs metal semiconductor field-effect transistor (MESFET)-termed p-pocket MESFET-for use as a linear power amplifier in personal handy-phone systems. Conventional buried p-layer technology, the primary technology for microwave GaAs power MESFET's, has a drawback of low power efficiency for linear power applications. The low power efficiency of the buried p-layer MESFET is ascribed to the I-V kink which is caused by holes collected in the buried p-layer under the channel. In order to overcome this problem, we have developed the self-aligned gate p-pocket MESFET which incorporates p-layers not under the channel but under the source and drain regions. This new MESFET exhibited high transconductance and uniform threshold voltage. The problematic I-V kink was successfully removed and an improved power efficiency of 48% was achieved under bias conditions, which resulted in adjacent channel leakage power at 600-kHz offset as low as -59 dBc for 1.9-GHz /spl pi//4-shift QPSK modulated input.

Characteristics of a 0.2-mum capless InAlAs/InGaAs pseudomorphic high electron mobility transistor (p-HEMT) having a self-aligned gate (SAG) were investigated. The 0.2-mum SAG capless p-HEMT showed a source resistance comparable to that of a conventional recessed p-HEMT having a heavily n-doped In0.53Ga0.47As cap layer primarily due to the SAG and optimized ohmic-metallization processes and excellent characteristics of Gm,max, fT, and fmax of 1.12 S/mm, 185 GHz, and 225 GHz, respectively, even without a heavily doped InGaAs cap layer. The capless device exhibited much better device parameters for digital logic applications including I ON/IOFF and subthreshold slope (1.27times104 and 78 mV/dec) compared with those (5.1times103 and 120 mV/dec) of the conventional recessed device, respectively

A new power HBT and HFET were developed for low unity supply voltage operation in PHS handsets. The emitter region, the emitter electrode, the buried collector and the base electrodes in the power HBT are formed using the emitter electrode self-alignment process in order to reduce parasitic resistance and capacitance. The wirings on each electrode of the HBT are formed by Au plating technique for high current operation. The gate electrode in the power HFET is self-aligned to the drain/source electrodes by using the drain/source contact mesas as a mask, where the distance between the drain and the source is minimized and the parasitic resistances are reduced. In addition, an asymmetrical double-doped structure of AlGaAs/GaAs/InGaAs/AlGaAs is applied to the HFET in order to obtain a high current density. Both the power HBT and HFET exhibited the knee voltage less than 1 V with the maximum current more than 500 mA. The power HBT performed a power gain of 14.2 dB, an efficiency of 33.8% and the power HFET performed 12.5 dB and 34.5%, with a sufficient margin of distortion for PHS standard at an output power of 22 dBm, a supply voltage of 3.5 V and a frequency of 1.9 GHz under the unity operation.

We report on 0.1-/spl mu/m gate-length self-aligned Au/WSiN-gate GaAs MESFET technology. The FET we produced using this technology has a planar structure with a selective ion-implanted channel layer and self-aligned n/sup +/- layers. One of the key structural parameters affecting device performance is the offset separating the gate electrode from lightly-doped source and drain n' layers. A 0.1-/spl mu/m gate length is attained by i-line photolithography using an anti-reflection top coat film and SF/sub 6/ gas ECR plasma etching. We demonstrate FET uniformity in a 3-in wafer and excellent high-frequency performance. The standard deviation of the threshold voltages is 0.058 V with an average of about 0 V at a gate length of 0.126 /spl mu/m and the current gain cutoff frequency (f/sub T/) is 168 GHz at a gate length of 0.06 /spl mu/m.

We report record DC and RF performance obtained in deeply-scaled self-aligned-gate GaN-HEMTs with heavily-doped n+-GaN ohmic contacts to two-dimensional electron-gas (2DEG). High density-of-states of three-dimensional (3D) n+-GaN source near the gate mitigates “source-starvation,” resulting in a dramatic increase in a maximum drain current (I dmax ) and a transconductance (g m ). 20-nm-gate D-mode HEMTs with a 40-nm gate-source (and gate-drain) distance exhibited a record-low R on of 0.23 Ω·mm, a record-high I dmax of >4 A/mm, and a broad g m curve of >1 S/mm over a wide range of I ds from 0.5 to 3.5 A/mm. Furthermore, 20-nm-gate E-mode HEMTs with an increased L sw of 70 nm demonstrated a simultaneous f T /f max of 342/518 GHz with an off-state breakdown voltage of 14V.

WSiN Schottky diodes on GaAs have been electrically and chemically characterized for atomic silicon and nitrogen; compositions of 0 to 42% and 0 to 28%, respectively. It is found that the main cause for Schottky diode degradation, after high temperature annealing, is the out-diffusion of As from GaAs. For films with atomic nitrogen composition of /spl ges/5%, As outdiffusion is eliminated as long as the atomic Si composition is /spl les/40%. WN films (5% nitrogen) were applied to the fabrication of self-aligned gate lightly doped drain MESFET's with buried P layer. A maximum transconductance, g/sub m/, of 370 mS/mm, f/sub T/ of 33 GHz, and DCFL inverter delay of 29 ps are measured for a 0.5 /spl mu/m gate technology. >

Self-aligned-gate heterostructure field-effect transistor (HFET) is fabricated using a wet-etching method. Titanium nitride (TiN) is one kind of thermal stable material which can be used as the gate electrode. A Ti/Au cap layer is fixed on the gate and acts as an etching mask. Then the T-shaped gate is automatically formed through over-etching the TiN layer in 30% H2O2 solution at 95 °C. After treating the ohmic region with an inductively coupled plasma (ICP) method, an Al layer is sputtered as an ohmic electrode. The ohmic contact resistance is approximately 0.3 Ωmm after annealing at a low-temperature of 575 °C in N2 ambient for 1 min. The TiN gate leakage current is only 10−8 A after the low-temperature ohmic process. The access region length of the self-aligned-gate (SAG) HFET was reduced from 2 μm to 0.3 μm compared with that of the gate-first HFET. The output current density and transconductance of the device which has the same gate length and width are also increased.

Electrical characteristics of fully self-aligned gate overlapped lightly doped drain (FSA-GOLDD) polysilicon thin-film transistors (TFTs), fabricated with a spacer technology and providing submicron (0.35 μm) LDD regions, have been analyzed. Device characteristics show negligible series resistance of the LDD region while effective drain field relief has been demonstrated by a reduced kink effect and off-current, if compared to conventional self-aligned (SA) devices. Short channel effects are also mitigated by the LDD region, while substantial reduction in the hot-carrier induced instability is found, when compared with conventional SA devices. Optimum doping dose of the LDD region has been identified to be 9 × 1012 cm2.

A novel process for fabricating self-aligned gate-overlapped LDD (SAGOLDD) poly-Si thin film transistors (TFTs) was demonstrated. Laser irradiation for dopant activation was performed from the backside of the quartz wafer. The graded LDD structure was naturally formed under the gate edges due to the lateral diffusion of the dopants during the laser activation. In comparison with the conventional laser-processed self-aligned poly-Si TFTs, the SAGOLDD poly-Si TFTs exhibited lower leakage current, suppressed kink effect, and higher reliability. Moreover, the proposed process was simple and very suitable for low-temperature processing.

In this paper we present a 55 nm gate length In 0.53 Ga 0.47 As MOSFET with extrinsic transconductance of 1.9 mS/µm and on-resistance of 199 Ωµm. The self-aligned MOSFET is formed using metalorganic chemical vapor deposition regrowth of highly doped source and drain access regions. The fabricated 140 nm gate length devices shows a low subthreshold swing of 79 mV/decade, which is attributed to the described low temperature gate-last process scheme.

We report record DC and RF performance in deeply-scaled self-aligned gate (SAG) GaN-HEMTs operating in both depletion-mode (D-mode) and enhancement-mode (E-mode). Through aggressive lateral scaling of the gate length (L g ) and the source-drain distance (L sd ) using a novel self-aligned gate technology and engineering of a thin top barrier layer, 20-nm gate AlN/GaN/AlGaN double-heterojunction (DH) HEMTs operating in D-mode (and E-mode) exhibited record DC and RF characteristics with high yield and uniformity; R on = 0.29 (0.33) Ω·mm, I dmax = 2.7 (2.6) A/mm, a peak extrinsic g m = 1.04 (1.63) S/mm, threshold voltage uniformity σ (V th ) = 44 (63) mV over a 3-inch wafer area, and a simultaneous f T /f max = 310/364 (343/236) GHz. Delay time analysis clarified that an unique dependence of f T on V ds resulted from suppressed drain delay and enhanced electron velocity due to the lateral source-drain (S-D) scaling.

Self-aligned 0.25 μm T-gate pHEMT technology was described in this paper. Basic requirements of the self-aligned technology for gate profile were presented. Metallization system and annealing parameters providing low resistance ohmic contacts were chosen. Current-voltage characteristics, capacity-voltage characteristics and current gain of routine and self-aligned pHEMT were compared. The self-aligned technology provides an increase in transconductance S and drive current I ds of 10…15% comparing with routine process. Cutoff frequency increased by 15 GHz and reached F t ∼70 GHz.

Tunnel field effect transistors (TFET) have gained interest recently owing to their potential in achieving sub-kT/q steep switching slope, thus promising low Vcc operation[1–5]. Steep switching slope has already been demonstrated in Silicon TFET [2]. However, it has been theoretically shown and experimentally proved that Si or Si x Ge 1−x based homo-junction or hetero-junction TFETs would not meet the drive current requirement for future low power high performance logic applications [3]. III–V based hetero-junction TFETs have shown promise to provide MOSFET like high drive currents at low operating Vcc while providing the sub-kT/q steep switching slope[1,4,5]. However, the device design demands extremely scaled EOT and ultra-thin body double-gate geometry in order to achieve the desired transistor performance [4]. In this paper, we discuss a vertical TFET fabrication process with self-aligned gate [6] which can ultimately lead to the ultra-thin double-gate device geometry in order to achieve the desired TFET performance.

We have developed a new self-aligned gate technology for InGaAs High Electron Mobility Transistors with non-alloyed Mo-based ohmic contacts and a very low parasitic capacitance gate design. The new process delivers a contact resistance of 7 Ohm-µm and a source resistance of 147 Ohm-µm. The non-alloyed Mo-based ohmic contacts show excellent thermal stability up to 600 °C. Using this technology, we have demonstrated a 60 nm gate length self-aligned InGaAs HEMT with g m = 2.1 mS/µm at V DS = 0.5 V, and f T = 580 GHz and f max = 675 GHz at V DS = 0.6 V. These are all record or near record values for this gate length.

Here we report high performance sub-100 nm channel length grapheme transistors fabricated using a self-aligned approach. The graphene transistors are fabricated using a highly-doped GaN nanowire as the local gate, with the source and drain electrodes defined through a self-aligned process and the channel length defined by the nanowire size. This fabrication approach allows the preservation of the high carrier mobility in graphene, and ensures nearly perfect alignment between source, drain, and gate electrodes. It therefore affords transistor performance not previously possible. Graphene transistors with 45–100 nm channel lengths have been fabricated with the scaled transconductance exceeding 2 mS/µm, comparable to the best performed high electron mobility transistors with similar channel lengths. Analysis of and the device characteristics gives a transit time of 120–220 fs and the projected intrinsic cutoff transit frequency (fT) reaching 700–1400 GHz. This study demonstrates the exciting potential of graphene based electronics in terahertz electronics.

A vertically configured nanodiamond vacuum field emission transistor (VFET) is developed. The device is fabricated on a silicon-on-insulator (SOI) substrate, using the active silicon layer patterned with inverted pyramidal mold for nanodiamond deposition and as the self-aligned gate of the final VFET construct. Gate modulation of the emission current is observed with a relatively low gate turn-on voltage. The I a -V g -V a characteristics of the device show distinct linear, saturation and cutoff regions, demonstrating the transistor behaviors. The VFET shows a high dc voltage gain of ~ 1000, an ac voltage gain of ~ 44 and a phase shift of 180° when operated as a voltage amplifier. This nanodiamond VFET promises potential applications in vacuum microelectronics, including integrated circuits.