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3. Early Testable Addressable Logic (ETAL) Test Structure: Showcasing the use of an Alternate Logic Yield Learning Test Structure for Technology Development

4. A 12nm FinFET Technology Featuring 2nd Generation FinFET for Low Power and High Performance Applications

5. Bulk planar 20nm high-k/metal gate CMOS technology platform for low power and high performance applications

12. TDDB robustness of highly dense 65NM BEOL vertical natural capacitor with competitive area capacitance for RF and mixed-signal applications

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