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In the presence of structural disorders, carrier conduction via localized hopping sites emerges in two-dimensional systems and results in a unique thermopower characteristic with T1/3 dependence. The disorders induced potential differences of hopping sites leading to energy variations along current-carrying paths. A systematic thermoelectric study is presently required in comprehending the statistical effects. Therefore, we proposed a statistical model of the Seebeck coefficient on the basis of percolation theory and hopping mechanisms. With this model, the carrier density and temperature dependences can be practically predicted. Key parameters can be extracted by calibration to molybdenum disulfide and black phosphorus experiments, providing a deeper insight into device physics. Moreover, a Mott-like analytical model is developed to investigate the parametric dependence. The thermopower deviations from the noninteracting Mott picture at high and low temperatures are analyzed. Finally, the temperature dependence on the thermoelectric figure of merit is evaluated in a variable range hopping regime. Our model is essential for a reliable prediction of the disorder induced statistical effects on thermoelectric behaviors, which guides both device optimization and material engineering. [ABSTRACT FROM AUTHOR]

A comprehensive understanding of the disorder-induced transport characteristics in resistive random-access memory (RRAM) is critical for its thermal stability analysis and analog switching for the coming neuromorphic computing application. Superior to the previous transport mechanisms which are only valid within their respective ranges of temperatures, we propose a unified physics-based model that can accurately predict the transport dependence on all temperature ranges up to 300 K. By utilizing percolation theory and the Fermi Golden Rule, the probability distributions for both the tunnel junction energy barrier and gap distance based statistical resistance model are described. It is found that different programming cycles and resistance states contribute to transition behavior between various low-temperature transport mechanisms. Moreover, the model can also investigate the dependence of electrical characteristics on defect generation like radiation damage. Therefore, it quantitatively relates the thermal stability and percolation effects to the structural disorders in RRAM. The good agreement between the simulation and experimental results indicates that our physics-based model can provide an accurate prediction of temperature and disorder dependent effects in RRAMs. [ABSTRACT FROM AUTHOR]

The thermal conductivity measurement of films with submicrometer thicknesses is difficult due to their exceptionally low thermal resistance, which makes it challenging to accurately measure the temperature changes that occur as heat flows through the film. Thus, specialized and sensitive measurement techniques are required. 3ω method is a widely used and reliable tool for measuring the thermal conductivity of films. However, the high in-plane thermal conductivity in thin films results in rapid heat dissipation across the thin film, resulting in poor measurement sensitivity and making it difficult to accurately measure the temperature gradient with the traditional 3ω method. Also, the traditional 3ω method requires cross-plane thermal conductivity to derive the in-plane counterpart. Here, we introduce a dual-domain 3ω method that adopts AC-modulated heating and electrode arrays facilitating surface temperature profiling: (1) the sensitivity was significantly improved due to the employment of low-thermal-conductivity-substrate, and (2) cross-plane thermal conductivity is not required for the analysis of in-plane counterpart. This measurement platform allows us to control heat penetration in depth via varied heating frequencies as well as spatial temperature detection through laterally distributed electrodes on the thin film surface. By utilizing the described method, we have determined the in-plane thermal conductivity of a copper film, having a thickness of 300 nm, which was found to be 346 Wm−1K−1 and validated by the Wiedemann–Franz law. [ABSTRACT FROM AUTHOR]

A surface potential based compact model for two-dimensional field effect transistors (2D-FETs) is proposed to incorporate the structural disorders induced transition behaviors among variable range hopping (VRH), nearest neighbor hopping (NNH), and band-like transport in most 2D materials. These functions coupled with effective transport energy and multiple trapping and releasing theory enable our developed model to predict the temperature and carrier density dependent current characteristics. Its validity is confirmed by the experimental results such as the metal insulator transition (MIT) in transition metal dichalcogenides and VRH-NNH transition in black phosphorus nanoribbon. Based on this model, the band-tail effects on the crossover gate voltage of MIT behavior are quantitatively investigated. It is found that the transition behavior is closely related to the distribution of the band-tail states. Furthermore, this model is implemented in Verilog-A for circuit-level prediction and evaluation of 2D-FETs to provide deeper insight into the relationship between material properties, device physics, and circuit performances. [ABSTRACT FROM AUTHOR]

We report high-performance amorphous Indium-Gallium-Zinc-Oxide nanowire field-effect transistors ($\alpha $ -IGZO NW-FETs) featuring an ultrascaled nanowire width (${W}_{{\mathrm {NW}}}$) down to ~20 nm. The device with 100 nm channel length (${L}_{{\mathrm {CH}}}$) and ~25 nm ${W}_{{\mathrm {NW}}}$ achieves a decent subthreshold swing (SS) of 80 mV/dec as well as high peak extrinsic transconductance (${G}_{m,{\mathrm {ext}}}$) of $612~\mu S/\mu \text{m}$ at a drain–source voltage (${V}_{{\mathrm {DS}}}$) = 2 V ($456~\mu S/\mu \text{m}$ at ${V}_{{\mathrm {DS}}}$ = 1 V). The good electrical properties are enabled by using an ultrascaled 5 nm high- ${k}$ HfO2 as the gate dielectric, a water-free ozone-based atomic layer deposition (ALD) process, and a novel digital etch (DE) technique developed for indium-gallium-zinc-oxide (IGZO) material. By using low-power BCl3-based plasma treatment and isopropyl alcohol (IPA) rinse in an alternating way, the DE process is able to realize a cycle-by-cycle etch with an etching rate of ~1.5 nm/cycle. The scaling effects on device performance have been analyzed as well. It shows that the downscaling of ${W}_{{\mathrm {NW}}}$ improves the SS notably without sacrificing ON-state performance, and the shrinking of ${L}_{{\mathrm {CH}}}$ boosts the ${G}_{m,{\mathrm {ext}}}$. The ultrascaled $\alpha $ -IGZO NW-FETs could play an important role in applications where high performance and high density are highly desired. [ABSTRACT FROM AUTHOR]

Prostheses and robots have been affecting all aspects of life. Making them conscious and intelligent like humans is appealing and exciting, while there is a huge contrast between progress and strong demand. An alternative strategy is to develop an artificial peripheral neural system with high‐performance bionic receptors. Here, a novel functional composite material that can serve as a key ingredient to simultaneously construct different artificial exteroceptive sensors (AE sensors) and artificial proprioceptive sensors (AP sensors) is demonstrated. Both AP sensors and AE sensors demonstrate outstandingly high stretchability; up to 200% stretching strain and possess the superior performance of fast response and high stability. An artificial peripheral neural system integrated with the highly stretchable AP sensor and AE sensor is constructed, which makes a significant breakthrough in the perception foundation of efficient proprioception and exteroception for intelligent prostheses and soft robots. Accurate feedback on the activities of body parts, music control, game manipulation, and wireless typing manifest the enormous superiority of the spatiotemporal resolution function of the artificial peripheral neural system, all of which powerfully contribute to promoting intelligent prostheses and soft robots into sophistication, and are expected to make lives more fascinating. [ABSTRACT FROM AUTHOR]

We investigate the effect of channel layer thickness on effective mobility (μeff) in the sub-10-nm regime of amorphous indium–gallium–zinc–oxide thin-film transistors (α-IGZO TFTs). TFT devices with extremely scaled channel thickness tα-IGZO of 3.6 nm were realized, exhibiting low subthreshold swing (SS) of 74.4 mV/decade and the highest effective mobility μeff of 34 cm2/V ⋅ s at a carrier density NCarrier of ~ 5 × 1012 cm−2 for any kind of α-IGZO TFTs having sub-10-nm tα-IGZO. No significant degradation of μeff is observed as α-IGZO thickness reduced from 6 to 3.6 nm. By scaling down the channel length LCH to 38 nm, high extrinsic transconductance (Gm, max) of 125 μs/μm (at VDS of 1 V) and ON-state current ION of 350 μA/μm at VGS – VT of 3 V with VDS of 2.5 V are achieved. [ABSTRACT FROM AUTHOR]

The analog resistive switching (RS) characteristics in 2-D polycrystalline (poly-) molybdenum disulfide (MoS2) field-effect transistors (FETs) enable new electronic devices capable of emulating biological synaptic behaviors. In 2-D poly-materials, grain boundary (GB)-induced trap states are of major significance to RS behaviors. However, there is still a lack of appropriate compact models that capture accurate physical mechanisms. Therefore, we developed a surface potential-based compact model, based on the theories of the GB energy barrier and space charge limited current (SCLC). By calibrating to experimental data of MoS2, the physical parameters are extracted, and the model explains the scaling behaviors of channel lengths and grain sizes. Due to the electric-field-induced defect redistribution, the energy barrier modulation at a single-GB (e.g., intersecting GB) quantitatively matches the reported experiments. Moreover, the possible SCLC-based RS behavior is also investigated. Furthermore, we have optimized the set/reset process and simulated the postsynaptic current (PSC) with a tunable potentiation (or depression) process, and then the gate voltage dependence and statistical effects on RS and PSC have been investigated. Thus, this model provides important devices physics insights of 2-D poly-materials and it guides device design, fabrication, and material engineering, to meet the requirements of the future neuromorphic computing application. [ABSTRACT FROM AUTHOR]

FETs made on 2-D semiconductors, typically without degenerate doping at the contacts, have a significant Schottky junction (SJ) resistance, which complicates transistor analysis. This paper evaluates the effect of the contact resistance on the 2-D-material FET characteristics through four-terminal (4-T) resistance measurements on WSe2 FETs, which allow studying the channel and contacts characteristics separately. Apart from showing the nonnegligibility of contact resistance, this paper enables a finer understanding of commonly observed phenomena, such as transistor performance improvement with dielectric-encapsulation is observed to have a stronger effect on the contact than the channel; the resistance of the forward-biased SJ is observed to be not negligible, but comparable to that of the reverse-biased junction; at biases commonly referred to as “low-bias,” the WSe2 FET resistance could be dominated by the contacts; and pinchoff can be observed at relatively lower current levels, being related to the channel-contact resistance ratio rather than their magnitudes. In the devices where true channel pinchoff can be verified, a correlation emerges between current saturating behavior and asymmetry in the output characteristics with respect to the drain–source bias polarity, a feature that may serve as a guide toward interpreting standard FET output characteristics in 2-D materials. [ABSTRACT FROM PUBLISHER]

In this article, we present coupled experimental/simulated results about the influence of interface and border traps on the electrical characteristics and split-CV mobility extraction in InGaAs MOSFETs. These results show that border traps limit the maximum drain current under on-state conditions, induce a hysteresis in the quasi-static transfer characteristics, as well as affect CV measurements, inducing an increase in the accumulation capacitance even at high frequencies where trap effects are commonly assumed to be negligible. Hysteresis in the transfer characteristics can be used as a sensitive monitor of border traps, as suggested by a sensitivity analysis where either the energetic or the spatial distribution of border traps are varied. Finally, we show that mobility extraction by means of the split-CV method is affected by appreciable errors related to the spurious contributions of interface and border traps to the total gate charge, ultimately resulting in significant channel mobility underestimation. In very narrow channel devices, channel electron spilling over the InP buffer layer can also contribute to mobility measurement inaccuracy. [ABSTRACT FROM AUTHOR]

In recent CMOS technology, extreme shrinking of contact area at source/drain regions raises serious concerns of high metal/semiconductor contact resistance. Confronting this problem, we introduce a precontact amorphization implantation plus Ti silicidation technique (PCAI + TiSix) and achieve ultralow contact resistivity ( \rho c ) of (1.3 – 1.5) \times 10^-9 ~\Omega \cdot \text cm^2 on Si:P. This PCAI + TiSix technique utilizes light amorphization (low-energy implantation), thin Ti and TiSix film, and moderate thermal budget (500 °C –550 °C): these features are compatible with modern CMOS manufacturing. Moreover, the PCAI + TiSix-induced \rho c reduction is proved universal on both n- and p-Si. With additional characterizations, we find that the silicidation-induced \rho c variation is not merely a Schottky barrier height tuning effect. The electrical and physical characterizations suggest that the low \rho c is strongly correlated with the formation of interfacial TiSix crystallites between amorphous TiSi alloy and Si. [ABSTRACT FROM PUBLISHER]

The effective bandgap for heterojunction band-to-band tunneling ( $ {{E}}_{{\text {g,eff}}}$ ) is a crucial design parameter for a heterojunction tunneling FET (TFET). However, there is significant uncertainty on $ {{E}}_{{\text {g,eff}}}$ , especially for In0.53Ga0.47As/ GaAs0.5Sb0.5. This makes the prediction of TFET performance difficult. We calibrate $ {{E}}_{{\text {g,eff}}}$ by fabricating heterojunction p+/i/n+ diodes, comparing the simulated and the measured current–voltage and capacitance–voltage curves, while taking $ {{E}}_{{\text {g,eff}}}$ as a fitting parameter. Our calibration significantly reduces the uncertainty on $ {{E}}_{{\text {g,eff}}}$ compared with the range found in the literature. The comparison with the previous work on highly doped heterojunction diodes suggests that dopant-dependent bandgap narrowing reduces $ {{E}}_{{\text {g,eff}}}$ and therefore significantly impacts the performance of highly doped TFET. [ABSTRACT FROM AUTHOR]

An experimental low-frequency noise (LFN) assessment of long channel Ge pFinFET devices fabricated in different shallow trench isolation (STI) processes is presented, taking into consideration devices with fin widths from 100 nm (planar-like) down to 20 nm. In addition, the correlation among LFN parameters, hole mobility and threshold voltage, is also evaluated. The carrier number fluctuation ( $\Delta N$ ) model is confirmed as dominant mechanism for all studied Ge pFinFETs and there is no correlation with the used STI process. From the LFN, it is evidenced that the Coulomb scattering mobility mechanism plays an important role for STI-first process, resulting in a mobility degradation. [ABSTRACT FROM PUBLISHER]

This work discusses the thermal stability of metal-insulator-semiconductor (MIS) contacts. A case study is performed on a typical low-Schottky barrier height ( q\varphi b) MIS contact: Ti/TiO2/n-Si. By incorporating different levels of donor concentration in n-Si, we perform a systematic Ti/TiO2/n-Si thermal stability study under different electron conduction mechanisms. We find that both q\varphi b and contact resistivity ( \rho c) of the Ti/TiO2/n-Si MIS contacts vary dramatically after mere 300 °C–500 °C 1-min rapid thermal treatments. The variations in q\varphi b and \rho c are related to the thermally driven TiO2 decomposition. This thermal stability study of Ti/TiO2/n-Si reveals a general concern for the MIS contact application: since the MIS contacts on n-type semiconductor generally utilize a reactive low-work function metal and an ultrathin insulator, it is difficult to maintain their interface quality considering the thermal budget in standard manufacturing of integrated circuits. Possible solutions to this MIS thermal stability issue are discussed. [ABSTRACT FROM PUBLISHER]

This paper presents the low-frequency noise (LFN) behavior of vertical tunnel FETs (TFETs). The experimental input characteristics with different source compositions (Si and Ge) and different HfO2 thicknesses in the gate-stack (2 and 3 nm) are presented. A brief analog parameters analysis, including the transconductance, output conductance, and intrinsic voltage gain behavior under different bias conditions, shows that TFETs are promising for analog applications. For the LFN study, the standard number fluctuations model for MOSFETs was used in order to verify and compare the TFETs noise behavior, exploring the influence of different conduction mechanisms in each bias region. In the proposed model, the effective channel length ( L\mathrm{eff} ) is replaced by the tunneling length, resulting in good agreement between the experimental data and the model. The temperature influence on the TFET noise behavior is also investigated. [ABSTRACT FROM AUTHOR]

In this paper, we present an intensive study of 6T-SRAM designs for vertical gate-all-around (GAA) transistors (VFETs) and lateral GAA transistors (LFETs) using 5-nm node design rules. Optimizations of the nanowire (NW) diameter and the gate length are also conducted to enhance the SRAM performance. Device VT retargeting has been proposed for improving the minimum operating voltage ( V\min ) of SRAMs. The isoperformance and isoyield have been performed to assess and determine the benefits provided by LFET and VFET architectures, respectively. Our results show that the VFET bitcells are denser than the LFET bitcells by 20%–30%. The SRAM read stability (read static noise margin) is significantly improved using the NW channel. For a $6\sigma $ yield target and an isoarea of SRAM bitcells, V\min of the VFET bitcell is 80 mV lower than LFET designs. Applying the proposed VT retargeting technique can allow the VFET 122 bitcell to operate at 0.57 V without using assist circuits. A standby leakage below 10 pA/cell can be achieved for both architectures. At isoperformance, the standby leakage of VFET bitcells is $2.6\times $ lower than LFET bitcells. [ABSTRACT FROM AUTHOR]

In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow allows controlling the gate height asymmetry between the nMOS and the pMOS by driving the work function shifter directly into the high- $k$ , and then by removing the dopant source (dummy doped metal gate) and depositing a fresh TiN metal gate. Although the integration flow is compatible with a standard 45-/28-nm technological node, it has been specifically designed to be compatible with dynamic random access memory peripheral applications or other emerging memories (embedded applications). A material down-selection is done (TiN/Mg/TiN gate-stack for nMOS and Al2O3 capping layer for pMOS), and it is demonstrated that a process window exists and guarantees enough work function lowering without compromising the electrical parameters (electrical oxide thickness, mobility, subthreshold slope, and gate leakage). Regarding the CMOS integration, it is shown that an nMOS-first integration is preferable, and that there is no contamination issue of the pMOS work function shifter (in this case, Al2O3) on the nMOS side. Finally, CMOS device performance is on par with the non-D&GR baseline, validating the integration flow. [ABSTRACT FROM AUTHOR]

For sub-7-nm technology nodes, the gate-all-around (GAA) nanowire-based device structure is a strong candidate to sustain scaling according to Moore’s Law. For the first time, the performance of two GAA device options—lateral FET (LFET) and vertical FET (VFET)—is benchmarked and analyzed at the system level using an ARM core processor, based on realistic compact device models at the 5-nm technology node. Tradeoffs among energy, frequency, leakage, and area are evaluated by a multi- Vth optimization flow. A variety of relevant device configurations, including various number of fins, nanowires, and nanowire stacks, are explored. The results demonstrate that an LFET GAA core has a larger maximum frequency than its VFET counterpart because the channel stress that can be created in the LFETs results in a larger ON current. For fast timing targets, the LFET cores are therefore superior. However, for slow timing targets (e.g., 5 ns), the VFET cores with three nanowires offer a 7% area reduction and a 20% energy saving compared with the LFET cores with 2fin/2stack at the same leakage power. [ABSTRACT FROM PUBLISHER]

In anomaly detection problems for advanced semiconductor devices, non-visual defects occur frequently. Machine learning (ML) algorithms have the advantage of identifying such defects. However, in this real-world problem, data comes sequentially in a streaming fashion, thus, we may not have sufficient data to train an ML model in batch mode. In such a scenario, online ML models are useful to detect defects immediately since they work in a single-pass mode. Besides, when data is collected from more realistic non-stationary monitoring environments, online ML models with evolving architecture are more practical. Thus, evolving and online ML models are developed in this work to detect defects in technology computer-aided design (TCAD)-based digital twin model of advanced nano-scaled semiconductor devices such as a fin field-effect transistor (FinFET) and a gate-all-around field-effect transistor (GAA-FET). Activation functions (AFs) in deep neural networks (DNNs) and membership functions (MFs) in neuro-fuzzy systems (NFSs) play an important role in the performance of those ML models. This work focuses on analyzing the effects of various AFs/MFs in our developed online ML models while detecting defects in real-world nano-scaled semiconductor devices, where significant training samples are not available. From various semiconductor datasets having fewer samples, it has been observed that the proposed evolving neuro-fuzzy system (ENFS) with Leaky-ReLU MF performs better (improvement in the range of 1.9% to 30.8% considering overall classification accuracy) than the other DNN or ENFS-based online ML models. Having an evolving architecture and online learning mechanism, besides anomaly detection, the proposed model's performance has also been evaluated for handling large data streams problems with concept drift. The performance of the proposed method has been compared with some recently developed baselines under the prequential test-then-train protocol. The classification rates of the proposed method has an improvement in the range of 1.1% to 65.9% than the existing methods. The code of this work has been made publicly available at https://github.com/MdFerdaus/LREC. • Machine learning guided online defect detection in advanced semiconductor devices. • Development of Leaky-ReLU-based novel evolving neuro-fuzzy system. • Evaluation of proposed system in single-pass mode. • Evaluation of proposed system under the prequential test-then-train protocol. [ABSTRACT FROM AUTHOR]

The gate-stack quality of planar MOSFETs fabricated in Ge-on-Si substrates and passivated by a GeOx interfacial layer is evaluated by low-frequency noise analysis. It is shown that for both n- and p-channel transistors predominantly 1/ f^\gamma noise ( $\gamma \sim 1$ ) has been observed, which originates from number and correlated mobility fluctuations. The oxide trap density and mobility scattering coefficient derived from the input-referred voltage noise power spectral density are demonstrated to be significantly higher for nMOSFETs than for pMOSFETs with the same gate-stack, which explains the low electron mobility. [ABSTRACT FROM PUBLISHER]

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules. [ABSTRACT FROM AUTHOR]

The goal of this paper is to study the analog performance parameters of tunnel field-effect transistors (TFETs) with different source compositions and process conditions. The experimental matrix included devices with either a 100% silicon or Si1–xGex source, so that the germanium amount at the source/channel interface could be correlated with the prevailing transport mechanism and its impact on transconductance (gm), output conductance ( g\mathrm {DS} ), and early voltage ( V\mathrm {EA} ) could be analyzed. The used process conditions were highlighted by comparing a reference split with no Si passivation to the cases with 12 and 18 Si monolayers to determine their influence on the interface trap density and eventual reduction of the traps in the gate oxide. All these process parameters enable to make conclusions on the intrinsic voltage gain ( AV ) and the low-frequency noise. Based on these results, the suitability of each type of TFET has been discussed, revealing that 100% Si may still be considered for analog applications depending on the bias conditions. [ABSTRACT FROM PUBLISHER]

This paper presents a new integration scheme to fabricate a Si/Si0.55~Ge0.45 heterojunction line tunnel field effect transistor (TFET). The device shows an increase in tunneling current with gate length. The 1-\mum gate length device shows on current in excess of 20 \muA/\mum at VGS=VDS=1.2~\rm V. Low-temperature measurements, performed to suppress trap-assisted tunneling (TAT), reveal the point subthreshold swing as low as 22 mV/dec at 78 K. Field-induced quantum confinement effects are found to increase the tunneling onset voltage by \sim0.35~V. Variation of the tunneling onset voltage measured experimentally is correlated to variation in the pocket thickness and its doping concentration. Small geometry devices were found to be more susceptible to microvariations in the pocket thickness and doping concentration. [ABSTRACT FROM AUTHOR]

The role of trap-assisted tunneling (TAT) in the degradation of the subthreshold swing (SS) in n-type line tunnel field-effect transistors (TFETs) is investigated through the experiments and simulations. A two to fourfold increase in the interface state density is achieved by applying a positive or a negative stress between the gate and the source. The negative stress shows no impact on the SS in spite of nearly fourfold increase in the interface state density. A nearly twofold increase in interface state density and improvement in SS are observed under the application of positive stress. The improvement in SS is attributed to H^+ species released from the Si/SiO2 interface during stress, which moves toward the bulk Si, passivating boron and bulk Si traps, thereby improving the SS. Under negative stress bias, the released H^+ species drifts toward the gate electrode, and hence no change in SS was observed. These experiments suggest that the SS degradation is mainly caused by TAT through bulk Si traps and insensitive to interface traps. A good control of bulk semiconductor trap density will be required to achieve sub-60-mV/decade SS in line TFETs. [ABSTRACT FROM PUBLISHER]

Biosynthetic production of vanillin via microbial biotransformation offers a low-cost alternative for manufacturers to meet the consumer demands for natural vanillin. However, identifying the high vanillin-producing microbial strains among multitudinous samples using the current analytical techniques such as liquid chromatography (LC) and mass spectroscopy (MS) is time consuming, cumbersome and costly. Here, we propose an alternative low-cost and rapid aptamer-based capacitive assay for sensitive and selective vanillin recognition based on the preferential binding affinity and stability of the aptamer-vanillin complex. This redox-free approach measures the changes in non-faradaic capacitance of transducing graphene-oxide (GO) activated gold electrodes immobilized with vanillin-specific aptamer. Aptamer-vanillin interaction on the GO surface alters the aptamer conformation causing surface charge redistribution detected via capacitance-frequency characteristics. The aptasensor showed a wide dynamic detection range of 10 pM-10 nM and a low limit of detection (LOD) of ~9.91 pM, which is the best reported so far. Finally, validation of the capacitive aptasensing against high-performance LC (HPLC) reference containing vanillin dissolved in a complex M9 medium with interfering compounds (ferulic acid and glycerol), to mimic typical microbial biotransformation, demonstrated good sensitivity and selectivity. The successful proof-of-concept can be translated to high-throughput electronic multi-analyte screening kits supplementary to existing analytical tools. Unlabelled Image • Label-free non-faradaic capacitive detection of vanillin by graphene oxide aptasensor. • Redox-free augmentation of bare GO vanillin response (6-fold) achieved using hybridized aptamer receptor. • The graphene oxide aptasensor showed a wide dynamic detection range (10 pM-10 nM). • The sensor showed a very low detection limit (9.91 pM) for vanillin detection. • The excellent sensor selectivity in a real complex biosynthesis HPLC matrix. [ABSTRACT FROM AUTHOR]

We report on the dual mechanical and proximity sensing effect of soft-matter interdigitated (IDE) capacitor sensors, together with its modelling using finite element (FE) simulation to elucidate the sensing mechanism. The IDE capacitor is based on liquid-phase GaInSn alloy (Galinstan) embedded in a polydimethylsiloxane (PDMS) microfludics channel. The use of liquid-metal as a material for soft sensors allows theoretically infinite deformation without breaking electrical connections. The capacitance sensing is a result of E-field line disturbances from electrode deformation (mechanical effect), as well as floating electrodes in the form of human skin (proximity effect). Using the proximity effect, we show that spatial detection as large as 28 cm can be achieved. As a demonstration of a hybrid electronic system, we show that by integrating the IDE capacitors with a capacitance sensing chip, respiration rate due to a human's chest motion can be captured, showing potential in its implementation for wearable health-monitoring. [ABSTRACT FROM AUTHOR]