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In this paper, a physical mechanism for hot carrier injection (HCI) induced trap generation and degradation in bulk FinFETs is investigated and verified with both experiment and simulation evidence. HCI degradation is mainly caused by interface states generated by drain avalanche hot carrier injection. From this model, impact ionization intensity, location and trapping immunity are proposed as key parameters to modulate HCI degradation. HCI reliability in I/O FinFETs is severely degraded with respect to planar FETs because of the enhanced capability of the gate to control the channel potential profiles increasing the intensity of the lateral E-field in comparison with planar devices. Based on this FinFET HCI mechanism, we have successfully optimized source/drain junction process to achieve reliable HCI characteristics for 14nm and 10nm FinFET devices.

Highly porous low-k dielectrics are essential for downscaling of the interconnects for 20–10 nm technologies. A planar capacitor test vehicle was used to investigate the intrinsic time dependent dielectric breakdown (TDDB) reliability of low-k dielectrics and the origin of an observed C–V hysteresis was studied. We hypothesize that the hysteresis is caused by donor-like traps present in the bulk of the low-k but not by electron/hole trapping or mobile charges. It is proposed that porogen/carbon residues are the source of these donor-like traps. Using Ileak vs. time measurements, it was found that the donor-like traps accelerate the dielectric degradation due to an enhanced EOX, causing a localized partial breakdown. The intrinsic TDDB reliability of the low-k film was improved by adding a sealing layer as such layer blocked the donor-like traps discharging.

In this paper, a low-cost and low-leakage gate-first high-k metal-gate CMOS integration compatible with the high thermal budget used in a 2× node dynamic random access memory process flow is reported. The metal inserted polysilicon stack is based on HfO 2 coupled with Al 2 O 3 capping for pMOS devices, and with a TiN/Mg/TiN stack together with As ion implantation for nMOS. It is demonstrated that n and pMOS performance of 400 and 200 μA/μm can be obtained for an OFF-state current of 10 -10 A/μm, while maintaining gate and junction leakages compatible with low-power applications. Reliability and matching properties are aligned with logic gate-stacks, and the proposed solution is outperforming the La-cap-based solutions in terms of thermal stability.

Channel hot-carrier (CHC) reliability in p-FinFET devices is studied related to the postdeposition anneal (PDA) process. Clearly reduced CHC degradation is observed with N2-PDA at the VG = VD stress condition. The interface defect density degradation calculated from the subthreshold slope is similar in the reference and PDA devices. However, the pre-existing high- k bulk defect is lower in the PDA-treated device as observed by the low-frequency-noise measurement. This leads to less hot/cold-carrier injection into the bulk defects at the high field under the VG = VD condition, where a higher charge trapping component is expected than under the classical VG ~ VD/2 condition. The responsible bulk defect is pre-existing, not generated during the CHC stress as proven by the stress-induced leakage current analysis.

In this work, the oxide electric field (Eox) reduction caused by negatively charged traps is proposed to explain the robustness of SiGe pMOSFETs to negative gate bias temperature instability (NBTI) stress. The high density of negatively charged acceptor-like traps close to the SiGe valance band (E v ) lowers the E ox and reduces the NBTI degradation at fixed overdrive. We demonstrate that trap engineering can be exploited to meet aggressive reliability requirements. Furthermore, it is predicted that there are no reliability issues in the SiGe pMOSFETs comparing with the Si counterparts.

The channel hot carrier degradation mechanisms in n-FinFET devices are studied. In long channel devices, interface degradation by hot carriers mainly degrades the device at the maximum impact ionization condition (VG ~ VD/2). At higher VG closer to VD, cold and hot carrier injection to the oxide bulk defect increases and dominates at the VG=VD stress condition. On the other hand, in short channel devices, hot carriers are generated continuously with respect to VG and highly at VG=VD, and this hot carrier injection into the oxide bulk defect is the main degradation mechanism.

(Si)Ge channel pMOS technology offers remarkably reduced Negative Bias Temperature Instability (NBTI) at ultra-thin EOT.We ascribe this property to a reduced interaction of channel holes with dielectric defects thanks to energy decoupling.The reduced NBTI projects to a dramatic reduction of the time-dependent variability in nanoscale devices.Other device degradation mechanisms are shown not to constitute showstoppers. With a significantly reduced Negative Bias Temperature Instability (NBTI), SiGe channel pMOSFETs promise to virtually eliminate this reliability issue for ultra-thin EOT devices. The intrinsically superior NBTI robustness of the MOS system consisting of a Ge-based channel and of a SiO2/HfO2 dielectric stack is understood in terms of a favorable energy decoupling between the SiGe channel and the gate dielectric defects. Thanks to this effect, a significantly reduced time-dependent variability of nanoscale devices is also observed. Other reliability mechanisms such as low-frequency noise, channel hot carriers, and time-dependent dielectric breakdown are shown not to be showstoppers.

This paper presents a comprehensive study on channel hot-carrier (CHC) degradation in short channel MOSFETs with high-k dielectric. Different reliability scenarios are analyzed, i.e., temperature influence, impact of high I"D and dynamic operation conditions. To explain the CHC damage behavior in short channel devices, we divide the total CHC degradation in two components: the classical CHC damage located at drain side and the degradation produced by the voltage drop over the gate dielectric, which can be considered as bias temperature instability (BTI).

The time-dependent variability of nanoscaled Si0.45 Ge0.55 pFETs with varying thicknesses of the Si passivation layer is studied. Single charge/discharge events of gate oxide defects are detected by measuring negative bias-temperature instability (NBTI)-like threshold voltage (Vth) shift relaxation transients. The impact of such individually charged defect on device Vth is observed to be exponentially distributed. SiGe channel devices with a reduced thickness of their Si passivation layer show a reduced average number of active defects and a reduced average impact per charged defect on device Vth. Our model for the superior reliability of the SiGe channel technology previously proposed in Part I, which is based on the energy decoupling between channel holes and dielectric defects, is shown to also explain these experimental observations. Other reliability mechanisms, such as 1/f noise, body biasing during NBTI, channel hot carriers, and time-dependent dielectric breakdown, are also investigated. None of these mechanisms are observed to constitute a showstopper for the reliability of this promising novel technology.

New insights into the negative/positive bias temperature instability (N/PBTI) degradation mechanisms in the sub-1-nm equivalent oxide thickness (EOT) regime are presented in this paper. The electric field requirements suggested by the International Roadmap for Semiconductors demand an even higher value in the sub-1-nm-EOT regime, which is practically difficult to meet with the increased hole trapping mechanism involved. Thus, a fixed electric field target of 5 MV/cm is considered as well here, which might be a reasonable target to achieve. The sub-1-nm-EOT devices in this paper are obtained by adopting a thinner TiN metal gate inducing Si in-diffusion and reducing the interfacial oxide layer thickness. NBTI degradation follows an isoelectric field model in over an EOT of 1 nm due to the degradation mechanism of Si/SiO_2 interface state generation combined with a hole trapping mechanism. However, in the sub-1-nm-EOT regime, the probability of hole trapping into the gate dielectric increases, and it is strongly dependent on the thickness of the interfacial oxide layer. Several experimental proofs of this increased bulk defect effect are shown in this paper. In addition, the bulk defect affecting NBTI is shown to be mostly a preexisting defect, although the permanently generated defects are relatively higher in sub-1-nm-EOT devices. Therefore, NBTI in the sub-1-nm-EOT regime faces the lifetime limit by both electric field dependence and increased degradation by increased hole trapping into bulk defects. Further, we found a minimum interfacial layer thickness of 0.4 nm that is required to prevent the accelerated NBTI degradation by increased direct tunneling. The main degradation mechanism of PBTI in sub-1-nm EOT is the electron trapping into bulk defects, which is the same as in over 1-nm-EOT devices. This enables us to modulate the bulk defect energetic locations in the oxide and to improve PBTI.

In this paper, the time-dependent dielectric breakdown (TDDB) in sub-1-nm equivalent oxide thickness (EOT) n-type bulk FinFETs is studied. The gate stacks consist of an IMEC clean interfacial layer, atomic layer deposition HfO2 high-k and TiN metal electrode. For the 0.8-nm EOT FinFETs, it is found that TDDB lifetime is consistent with results of planar devices for areas around , implying that the FinFET architecture does not seem to introduce new failure mechanisms. However, for devices with smaller area, the extrapolated voltage at a ten-year lifetime for soft breakdown (SBD) does not meet the specifications, and as a consequence, the SBD path wear-out will have to be included in the final extrapolation. Furthermore, it is shown that for EOTs smaller than 0.8 nm, the TDDB reliability on n-type FinFETs is challenged by the high leakage currents.

Extraction of interfacial trap density Nit in extremely reduced gate oxides with equivalent oxide thickness (EOT) below 1 nm by conventional charge pumping is virtually impossible due to the high gate leakage current through the very thin oxide. However, interface quality assessment in subnano EOT devices is essential for the reliability and performance improvement of future logic devices. In this paper, an accurate approach to determine the interfacial trap density in a 5.8-Å EOT device is performed by an advanced charge pumping technique employing ring-oscillator-connected devices. A consistency comparison of this technique to the conventional charge pumping is done by a frequency sweep on the 10.1-Å EOT device. Clear charge pumping currents are obtained on the 5.8-Å EOT oxide, and further analysis by varying the applied frequency and amplitude is performed. The interface trap density in the 5.8-Å EOT device is found to be higher than that in the 10.1-Å EOT device due to the physically reduced interfacial layer in the thinner EOT device. Moreover, direct tunneling-based calculation gives the charge injection distance as about 2Å inside the oxide. Stress-induced defect generation is investigated by applying dc stress between charge pumping and Idrain - Vgate measurements. The 5.8-Å EOT device shows higher initial Nit but lower stress-induced Nit as compared with the 10.1-Å EOT device. The bulk trap Not generated after stress is higher in the 5.8- A EOT device due to the higher initial bulk trap density.

Study of the intrinsic time dependent dielectric breakdown (TDDB) of dielectric copper diffusion barriers was realized using a unique planar capacitor (Pcap) test structure. The test vehicle has several advantages over the metal dot method. The most important one is the elimination of field enhancement effect which could be more than 50% in the case of metal dots. In order to test the effectiveness of this test vehicle, two different dielectric barriers, one conventional SiCN film and the other a BN film still under development, were selected for TDDB evaluations. Significant differences were observed between the two films in TDDB lifetime, the shape parameter β of the Weibull failure time distributions, and the characteristics of the current versus time curves. The BN film had a degradation of more than four orders of magnitude in TDDB lifetime than SiCN. The Weibull shape parameter β of SiCN was 8.4, among the highest values that have been reported for any dielectric barrier films, versus 1.4 for the boron nitride film. Furthermore, the SiCN film showed a decrease in current versus time curves during the initial stage of the stressing, a trend which is typically related to charge trapping in defect-free films. This was not the case for the BN film where the leakage currents were much higher. The results demonstrate that the Pcap test structure is an effective vehicle to evaluate the intrinsic reliability of dielectric barrier films.

In this work we examine the positive bias temperature instability (PBTI) and stress induced leakage current (SILC) reliability of nFET devices with thin (2.5 nm) ZrO2 gate dielectric layers. nFET devices show anomalous PBTI behavior in the form of a negative threshold voltage (Vt) shift during positive bias stress with little temperature dependence and it is not ‘frozen out’ at lower temperatures, indicating a single non-diffusion based mechanism. Correlations between the PBTI and the stress induced leakage current (SILC) suggest that the PBTI effect originates from trapping into empty defects which are initially detected as SILC and located just below the silicon conduction band. These defects also appear to be linked to the time dependent dielectric breakdown behavior.

In ultrascaled complimentary metal-oxide-semiconductor technologies, the lucky-electron model does not describe correctly Channel Hot-Carrier (CHC) degradation for typical transistor test conditions independently of the gate dielectric (SiO2 or high- k). A new model to describe the CHC degradation behavior in n-channel metal-oxide field-effect transistors, based on the dominant role of the gate voltage into the total CHC stress, is presented. This new model can be applicable to long- and short-channel transistors with high- k or SiO2 as a dielectric.

A comparison between pMOS and nMOS short channel transistors with high-k dielectric subjected to channel hot-carrier (CHC) stress is presented. Smaller CHC degradation is observed in pMOS devices. At high temperature, the CHC degradation increases for pMOS and nMOS. The temperature dependence of the CHC degradation has been explained, for both transistor types, by considering a larger influence of a bias temperature instability (BTI)-related component of the total CHC induced degradation.

The temperature dependence of channel hot-carrier (CHC) degradation in n-MOS transistors with high-k dielectrics has been studied. The analysis starts from the most damaging CHC stress conditions at room temperature (V G = V D/2 for long channels and V G = V D for short channels). We find that, for long-channel transistors, the CHC degradation decreases at high temperature, while for short-channel transistors, an increase is observed. In this paper, a new picture to explain the observed increment of CHC damage with temperature for short-channel transistors with high-k dielectric is presented. We demonstrate that the total CHC degradation consists of two components: the classical CHC damage located at the drain side and the degradation produced by the voltage drop over the gate dielectric, which can be considered a positive bias temperature instability (PBTI) effect. Particularly for short transistors stressed at high temperatures, this PBTI component dominates the total CHC degradation.

Channel hot-carrier (CHC) degradation in nMOS transistors is studied for different SiO2/HfSiON dielectric stacks and compared to SiO2. We show that, independent of the gate dielectric, in short-channel transistors, the substrate current peak (used as a measure for the highest degradation) is at VG = VD, whereas for longer channels, the maximum peak is near VG = VD/2. We demonstrate that this shift in the most damaging CHC condition is not caused by the presence of the high- k layer but by short-channel effects. Furthermore, the CHC lifetime of short-channel transistors was evaluated at the most damaging condition VG = VD, revealing sufficient reliability and even larger operating voltages for the high-k stacks than for the SiO2 reference.

In this paper, we study time-dependent dielectric breakdown in thin gate oxides and propose a new methodology applicable to a wide range of gate stacks for extracting soft breakdown (SBD) and post-SBD wear-out (WO) parameters from measuring the time to hard breakdown (t HBD) only. By introducing this methodology, we can get around the problems related to the detection of the first SBD and the corresponding WO time. We show that the shape of the HBD distribution can change with voltage and area, depending on the ratio of WO and SBD times. We also explain why, in literature, contradictory results related to the voltage acceleration factors of SBD and WO are reported. Finally, we construct a complete reliability prediction model that includes SBD and WO.

This work reports that introducing lanthanide in the gate dielectric or in the gate electrode results, in both cases, in large effective work function (eWF) modulation towards n-type band-edge for Ni-FUSI devices. This is done by: (a) deposition of a Dy 2 O 3 capping layer on the host dielectric (SiON or HfSiON), or (b) simple Yb implantation of nMOS poly gates prior to FUSI. We show that: (1) both cases result in dielectric modification with gate leakage (J G ) reduction; (2) adding a cap has no significant impact on T inv (

We propose the use of medium-κ dielectrics for direct tunneling floating gate memory devices, targeting embedded-random-access memory (e-RAM) applications. We found that SiON offers best performance if voltage reduction overrules refresh time, while Hf-silicates would be preferred if the refresh time is more critical. Our analysis is based on a direct tunneling current model, a response surface methodology and experimental data on small metal–oxide–semiconductor field-effect transistors (MOSFET's). The impact of dielectric degradation during cycling is studied for scalability towards the 32 nm node.

We study RTN and PBTI in nanoscale InGaAs FinFETs fabricated on 300mm Si wafers. The average instability is found to be comparable to planar structures, but significantly larger when compared to Si devices. Although the novel devices follow the same time-dependent variability statistics and the corresponding area-scaling as their Si counterparts, a larger stochastic impact of single defects on the device characteristic is found to induce larger aging-related variance. We ascribe this to a more percolative channel conduction induced by still excessive interface and channel defectivity.

Our present understanding of BTI in Si and (Si)Ge based sub 1-nanometer EOT MOSFET devices is reviewed and extended to benchmark other Beyond-Si based devices. We discuss the evolution of NBTI for Si-based pMOS devices as a possible showstopper for further scaling below 1nm EOT. Then we present the BTI reliability framework which was developed for SiGe based MOSFET devices, showing strongly improved BTI reliability, explained by carrier-defect decoupling. Also the important issue of increasing stochastic behavior and time dependent variability is discussed. Based on the presented framework developed for SiGe stacks we benchmark alternative Beyond-Si gate stacks using a metric for carrier-defect decoupling, allowing to screen stacks for acceptable reliability.

The gate dielectric breakdown induced microstructral changes in HfO2 high-κ gate stacks are analyzed using high resolution transmission electron microscopy. A new failure mechanism along the interface of HfO2/spacer has been observed in HfO2 high-κ gate stacks. This breakdown which is more common in accumulation mode stressing conditions in HfO2 high-κ/poly-Si gate stacks has not been observed in oxynitride gate dielectrics. It is believed that this interfacial breakdown could be dependent on enhanced electric field at the source/drain extension regions and on the corner geometry of the high-κ/poly Si gate stacks.

This work examines stress-induced leakage current (SILC) in both ultrathin silicon oxynitride and hafnium silicate dielectric layers for future MOS technology nodes. SILC is confirmed to be sense voltage dependent and is observed to have a dependence on bulk oxide traps for both dielectric layers. A possible explanation for the sense voltage dependence is provided. SILC is found to be a greater problem in the HfSiON layers, because of its magnitude relative to the initial current. This results in the leakage current density quickly becoming greater than that for SiON. The SILC is found to have a transient component in the HfSiON layers, indicating the presence of slow electron traps. Finally, the correlation between SILC and drive current reduction is demonstrated. It is concluded that in the high-k layers investigated in this study, SILC seems more of a problem than dielectric breakdown.

In order to reduce the gate leakage current, high-k gate dielectrics are expected to replace SiO2 in future CMOS generations. Many of these novel dielectrics are stacks of a thin SiO2 and a high-k layer. We present a theoretical study that aims at identifying the combination of the stack architecture and high-k material with the lowest leakage current. In the first part of this work the leakage current through high-k double stacks with various thicknesses, materials and gate electrodes is calculated assuming tunneling only. We discuss the difference between gate and substrate injection and show quantitatively the impact of interfacial layer thickness, barrier height, k-value and the work function of the gate material on the tunneling current. In the second part the material properties are no longer considered to be independent and with the universal relation between k-value and barrier height introduced, we are able to identify what material suits best all requirements. The leakage current is calculated for different EOTs and we demonstrate that if all dielectrics follow this universal relation, for a fixed thickness there exists one material, which gives a minimum gate leakage current. It is concluded that even for sub 1 nm EOT devices the k-value has not to exceed ∼25 and ZrO2 or HfO2 come closest to the ideal high-k if only leakage current issues are considered.

Negative bias temperature instability (NBTI) reliability in p-FinFET devices is studied with respect to the silicon substrate orientation. Interface trap density Nit is lower in the 45° rotated devices compared with the 0° rotated devices because of lower density of Si dangling bond at the (100) side walls than the (110) side walls. This improves NBTI reliability in the 45° rotated FinFET devices. Furthermore, we demonstrate that the lower inversion charge density Ninv-exhibited when transitioning from planar to FinFET architecture at 45° rotation-plays an important role in the whole NBTI degradation. NBTI clearly improves in the 45° rotated FinFET devices compared with the planarlike device because of the lower Ninv. Leakage current density analysis is shown as an experimental proof, in addition to simulation results of Cho et al.

Display Omitted Investigation of the reliability implications of Al-doping, which has been show to increase the k-value of HfO2.Very little TDDB improvement.High stress induced leakage current, confirmed to be due to defects at the HfO2/SiO2 interface. In this work we detail the reliability implications of doping HfO2 fabricated for use as the gate dielectric in an advanced CMOS process with aluminium. Introducing two single pulses of an Al-precursor during ALD causes the HfO2 to crystallise into a higher dielectric constant phase allowing for up to a factor of 300 reduction in the initial leakage current for a given EOT. However this results in only a small increase in TDDB lifetime due to the fact that there is a relatively large stress induced leakage current (SILC) generated in the doped layers, which we find to be mostly due to shallow defects. Furthermore, charge pumping measurements show large Nit generation in Al-doped layers, particularly towards the HfO2/SiO2 interface.

The negative bias temperature instability (NBTI) reliability of sub-1-nanometer equivalent oxide thickness (EOT) ZrO2 and HfO2 dielectrics with metal gate is investigated. The threshold voltage shift (ΔVTH) at identical NBTI over-drive stress conditions is observed to be lower in ZrO2 than in HfO2 field-effect transistors. Ring oscillator charge pumping is applied to determine interface trap generation (ΔNit) in the sub-1-nanometer EOT devices, with ZrO2 devices showing about one order of magnitude lower ΔNit than HfO2 device. However, the ΔNit contribution to the total ΔVTH is very limited in sub-1-nanometer EOT devices, as the recoverable component from the pre-existing bulk defects dominates the whole NBTI degradation. Pulsed Id-Vg technique is applied to analyze the pre-existing bulk defects in those sub-1-nanometer EOT devices, and lower pre-existing bulk defect density is shown in ZrO2, which decisively reduces NBTI in ZrO2 gate dielectric.

The reliability of ultra-thin (1.38 nm–2.14 nm EOT) hafnium silicate gate dielectrics was studied to determine their suitability for incorporation into large-scale integration processes at sub-100 nm channel length. The reliability study includes a discussion of the evolution of current with time during a constant voltage stress, deduction of Weibull slopes, voltage acceleration and an estimate of the 10-year maximum operating voltage for devices fabricated with these layers. Finally, the change in Weibull slope at increased current step magnitude for constant voltage stress is used to observe the change in trap generation rate during a CVS until breakdown.

A detailed study on charge trapping and dielectric re- liability of SiO -Al O gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were found to be strongly polarity dependent. The gate current is strongly reduced for injection from the TiN (gate) electrode compared to injection from the n-type Si substrate. For substrate injection, electron trapping occurs in the bulk of the Al O film, whereas for gate injection mainly hole trap- ping near the Si substrate is observed. Furthermore, no significant interface state generation is evident for substrate injection. In case of gate injection a rapid build up of interface states occurs already at small charge fluence ( mC/cm ). Dielectric reliability is consistent with polarity-dependent defect generation. For gate injection the interfacial layer limits the dielectric reliability and results in low Weibull slopes independent of the Al O thickness. In the case of substrate injection, reliability is limited by the bulk of the Al O layer leading to a strong thickness dependence of the Weibull slope as expected by the percolation model.

A detailed study on charge trapping and dielectric reliability of SiO/sub 2/-Al/sub 2/O/sub 3/ gate stacks with TiN electrodes has been carried out. Due to the inherent asymmetry of the dual layer stack all electrical properties studied were found to be strongly polarity dependent. The gate current is strongly reduced for injection from the TiN (gate) electrode compared to injection from the n-type Si substrate. For substrate injection, electron trapping occurs in the bulk of the Al/sub 2/O/sub 3/ film, whereas for gate injection mainly hole trapping near the Si substrate is observed. Furthermore, no significant interface state generation is evident for substrate injection. In case of gate injection a rapid build up of interface states occurs already at small charge fluence (q/sub inj/ /spl sim/ 1 mC/cm/sup 2/). Dielectric reliability is consistent with polarity-dependent defect generation. For gate injection the interfacial layer limits the dielectric reliability and results in low Weibull slopes independent of the Al/sub 2/O/sub 3/ thickness. In the case of substrate injection, reliability is limited by the bulk of the Al/sub 2/O/sub 3/ layer leading to a strong thickness dependence of the Weibull slope as expected by the percolation model.

The continual scaling of complementary metal oxide semiconductor (CMOS) technologies has pushed the Si-SiO2 system to its very limits and has led to the consideration of a number of alternative high-ĸ gate dielectric materials. In the end, it will be the electrical properties of the new Si/high-ĸ system that will determine its usefulness in future CMOS generations. For this reason, the study of the electrical properties of high-ĸ gate insulators is crucial. We present an overview of some of the electrical characterization techniques and reliability tests used to evaluate possible high-ĸ gate materials. Most of these techniques are well known from the characterization of SiO2 layers, but there are some additional complications, such as the presence of several different layers within one gate stack or the use of different gate electrode materials. These make the interpretation and comparison of experimental results more troublesome.

The reliability of 0.69 nm EOT GdHfO dielectric with metal gate is investigated. The threshold voltage shift at identical PBTI stress conditions is only 20% of the shift of a 0.78 nm EOT HfO 2 + La 2 O 3 (or HfLaO) device. The resulting reliable gate over-drive at 10 years of this GdHfO device is 0.85 V. Analysis of the stress induced leakage current (SILC) shows that the improved PBTI in the GdHfO device is related to the reduced trap generation under low bias stress, which already exists in the HfLaO device.

We propose the bipolar-mode operation of resistive random access memory devices in a purely oxygen-vacancy (V0)-controlled regime, which is achieved by very low compliance capping for forming/set transitions. This regime enables us to achieve a very low reset current of 10-100 nA, in which the governing mechanism for switching only involves the reversible drift of oxygen ions to and from oxygen soluble gate electrodes. The physical analysis of a gate stack in this V0 regime confirms the absence of metallic nanofilaments. These findings pave the way for the realization of ultralow switching power RRAM devices.

We propose the use of high-oxygen-solubility metalgate electrodes as a material of choice for high- gate stacks in order to prolong the time-dependent-dielectric-breakdown (BD) reliability. Our findings on n-channel metal-oxide-semiconductor devices with these gate electrodes reveal that the application of low negative bias stress after a soft-BD (SBD) event helps to restore the oxygen ions and passivate the oxygen vacancy traps that comprise the percolation path. This can be a simple yet effective designfor-reliability tool to initiate the self-repair of the percolation path and operate the circuit for a prolonged period after repair. The only requirement for achieving this SBD reversibility is to choose gate electrodes that can serve as good oxygen reservoirs.

Degradation and breakdown mechanisms of a SiOCH low-k material with k=2.3 (25% porosity) and thicknesses ranging from 90nm to 20nm were investigated. By combining time dependent dielectric breakdown (TDDB) data at positive/negative bias stress with thickness scaling results, dielectric failure is proven to be intrinsic and not influenced by copper drift or barrier deposition induced dielectric damage, which is further demonstrated by a very low TDDB thermal activation energy. During dielectric degradation, low field leakage current increase is suggested to be caused by donor type trap generation. It is shown that stress induced leakage current (SILC) can be used as a measure of dielectric degradation. Therefore, by monitoring SILC, low field lifetime can be safely estimated using extrapolation. Based on our experimental results, it is suggested that the impact damage model has a better accuracy for low field lifetime prediction.

We present a comprehensive study of Positive Bias Temperature Instability (PBTI) in In 0.53 Ga 0.47 As devices with Al 2 O 3 gate oxide, and with varying thickness of the channel quantum well. We show significant instability of the device electrical parameters induced by electron trapping into a wide distribution of defects in the high-k layer, with energy levels just above the InGaAs conduction band. A significant PBTI dependence on the channel thickness is found and ascribed to quantization effects. We argue that, in order to be relevant for production, the superior transport properties of III-V channels will need to be demonstrated with more stable high-k gate stacks.

In this work, a correlation between effective work function (EWF) and negative bias temperature instability (NBTI) is considered as a key for understanding the cause of NBTI acceleration in ultra-thin oxides and for its mitigation. High-k first process combined with slant etching of SiO 2 interfacial layer (IL) provides EWF and NBTI trend over the varied SiO 2 thickness. Evaluation of NBTI on the metal/high-k capacitors is done by employing the CV-BTI assessment technique. Whereas a modulation of EWF originating from the metal/high-k interface doesn't affect the NBTI, EWF roll-off originating from SiO 2 /Si interface causes a significant increase in NBTI at UT-EOT. This is explained by the change in alignment of defect level in gate dielectrics and hole injection level in Si substrate induced by the positive fixed charge generation. In contrast, introducing negative fixed charge near SiO 2 /Si interface, causing misalignment of the defect level and hole injection level, results in reduction of NBTI at thick EOT. Finally, lowering the channel doping density is proposed as a way to reduce both NBTI and PBTI.

In this paper we elaborate on challenges faced by contact formation at dense pitch: maintaining gate-to-contact reliability and keeping contact resistance low. We investigate intrinsic and integrated reliability of the gate-to-contact spacing materials and demonstrate capability of nitride gate encapsulation combined with a self-aligned contact etch process to handle misaligned contacts. Resistance of a silicide-through contact process is evaluated on fin substrates.

In this letter, submelt laser anneal used to achieve ultrashallow junctions (USJs) in capped high- devices with TaN/TiN metal gate electrode is investigated. The submelt laser anneal results in USJ and sharp junction on both n- and pMOSFET devices. However, this process induces interface and bulk defects and reduces negative-bias temperature instability (NBTI) reliability additionally. It is shown that if the laser anneal is followed by a rapid thermal anneal, the laser-related damage decreases, and the NBTI robustness improves without altering the obtained junction sharpness.

Este trabajo presenta el desarrollo de un modelo termo-eléctrico de elementos finitos (EF) con el fin de analizar los mecanismos de falla responsables de la degradación física causada por alta densidad de corriente en contactos de cobre de 90 nm empleados en dispositivos FinFET. De hecho en [1], esta degradación física fue interpretada como consecuencia principal del efecto Joule, sin embargo el modelo empleado alcanzó temperaturas demasiado bajas comparadas con el daño observado. Con el propósito de confirmar esta hipótesis, el modelo de EF de estado estable desarrollado en este trabajo calcula el incremento y la distribución de temperatura causada por alta densidad de corriente eléctrica fluyendo a través de un contacto de cobre, tomando en cuenta interfaces eléctricas y térmicas no idealizadas. Además, un análisis de sensibilidad fue realizado como un medio para identificar parámetros críticos de falla. La respuesta del modelo ante la variación independiente de la resistividad eléctrica de los materiales estudiados, y las conductancias eléctricas y térmicas entre el contacto de cobre y su barrera de difusión fue obtenida. La disminución de la conductancia eléctrica de dicha interfaz desencadenó temperaturas de estado estable superiores a los puntos de fusión del cobre y los silicatos del contacto y, en consecuencia, permite explicar la degradación física observada.

This letter reports a novel approach to achieve low threshold voltage (Vt) Ni-fully-silicide (FUSI) nMOSFETs with SiON dielectrics. By using a dysprosium-oxide (Dy2O3) cap layer with a thickness of 5 Aring on top of the SiON host dielectrics, Vt,lin of 0.18 V for long-channel devices (Lg = 1 mum) using NiSi-FUSI electrode is obtained, satisfying the high-performance device requirements. The Vt modulation due to the Dy2O3 cap layer is also maintained in the short-channel devices (with an Lg,min of 90 nm as demonstrated in this letter). In particular, approximately 150times reduction in gate leakage current is seen while preserving the dielectric capacitance equivalent thickness after adding the Dy2O3 cap layer on SiON dielectrics, likely due to a high-k layer (DySiON) formation during device source/drain activation process. We also report that the Dy2O3 layer does not vitally degrade the device reliability, such as positive-bias temperature instability and time-dependant dielectrics breakdown.

In downscaled poly-Si gate MOSFET devices reliability margin is gained by progressive wearout. When the poly-Si gate is replaced with a metal gate, the slow wearout phase observed in ultrathin SiON and HfSiON dielectrics with poly-Si gate disappears, and with it, the reliability margin. We demonstrate for several combinations of dielectric and gate materials that the large abrupt current increase (/spl Delta/I) as compared to poly-Si is not likely due to process issues, but is an intrinsic property of the dielectric/metal gate stack. The occurrence of large /spl Delta/I is a potential limitation for the reliability of metal gate devices.

The impact of the Al 2 O 3 position with respect to HfO' 2 in the process flow, is investigated. It is shown that Al 2 O 3 incorporation in order to increase the pMOS threshold voltage, slightly degrades the mobility, slightly increases NBTI and increases the EOT with respect to the reference without Al 2 O 3 Moreover, the trap density profiles depend on the Al 2 O 3 position: higher in the interfacial layer when Al 2 O 3 is below and higher in the HfO 2 when Al 2 O 3 is above HfO 2 • Furthermore, Al 2 O 3 below HfO 2 shows higher gate leakage, reduced LF noise but marginal NBTI difference compared to AL 2 O 3 above HfO 2 .