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2. Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration.

3. Feasibility and performance of the Idylla™ <scp> NRAS </scp> / <scp> BRAF </scp> cartridge mutation assay on thyroid liquid‐based fine‐needle aspiration

4. Methodology for Active Junction Profile Extraction in thin film FD-SOI Enabling performance driver identification in 500°C devices for 3D sequential integration

5. 3D sequential integration: applications and associated key enabling modules (design & technology)

6. Opportunities and challenges brought by 3D-sequential integration

7. SST5 expression and USP8 mutation in functioning and silent corticotroph pituitary tumors

8. Cytological features and nuclear scores: Diagnostic tools in preoperative fine needle aspiration of indeterminate thyroid nodules with RAS or BRAF K601E mutations?

9. OR23-04 SST5 Expression and USP8 Mutation in Functioning and Silent Corticotroph Pituitary Tumors

10. Confined selective lateral epitaxial growth of 16-nm thick Ge nanostructures on SOI substrates: Advantages and challenges

11. Is Gross Total Resection Reasonable in Adults with Craniopharyngiomas with Hypothalamic Involvement?

12. Tunability of Parasitic Channel in Gate-All-Around Stacked Nanosheets

14. Local lateral integration of 16-nm thick Ge nanowires on silicon on insulator substrates

15. Single-mode waveguides for GRAVITY: I. The cryogenic 4-telescope integrated optics beam combiner

16. Performance and Design Considerations for Gate-All-Around Stacked-NanoWires FETs

17. High performance low temperature FinFET with DSPER, gate last and Self Aligned Contact for 3D sequential mtegration

18. Stacked-Wires FETs for Advanced CMOS Scaling

19. Dense N over CMOS 6T SRAM cells using 3D Sequential Integration

20. Vertically Stacked-NanoWires MOSFETs in a Replacement Metal Gate Process with Inner Spacer and SiGe Source/Drain

21. Top-down fabrication and electrical characterization of Si and SiGe nanowires for advanced CMOS technologies

22. Recent advances in low temperature process in view of 3D VLSI integration

23. Ns laser annealing for junction activation preserving inter-tier interconnections stability within a 3D sequential integration

24. High performance CMOS FDSOI devices activated at low temperature

26. Facteurs prédictifs de l’expression du STTR5 par les adénomes corticotropes

28. W and Copper Interconnection Stability for 3D VLSI CoolCube Integration

29. (Invited) Annealing Techniques for Low Temperature Junctions Design in a 3D VLSI Integration

30. Pituitary MRI characteristics in 297 acromegaly patients based on T2-weighted sequences

31. Fine-needle aspiration biopsy with ultrasound guidance in patients with malignant melanoma and palpable lymph nodes

32. Facteurs pronostiques de rémission postopératoire précoce dans l’acromégalie. Étude d’une série de 63 patients opérés

33. Hyperparathyroïdies primaires juvéniles. À propos de 24 observations

34. Facteurs prédictifs de rémission postopératoire précoce dans les tumeurs hypophysaires neuro-endocrines : évaluation de la classification KNOSP revisitée

35. The beam combiners of Gravity VLTI instrument: concept, development, and performance in laboratory

36. Association between microsomal triglyceride transfer protein gene polymorphism and the biological features of liver steatosis in patients with Type II diabetes

37. Les opérations pour hyperparathyroïdie primaire en 1998.À propos de 66 patients et de trois voies d’abord

38. Chimiothérapie par 5-Fluorouracile-Dacarbazine : une alternative thérapeutique possible dans les cancers médullaires métastatiques rapidement progressifs

39. Hémangiome capillaire splénique en échographie conventionnelle et avec produit de contraste

40. Mise au point d’un test moléculaire améliorant le diagnostic préopératoire des nodules thyroïdens

41. Integrated optical detection circuit for magneto-optical drives

42. The integrated optics beam combiner assembly of the GRAVITY/VLTI instrument

43. Through Silicon Via technology using tungsten metallization

44. Effects of stress in polysilicon VIA - first TSV technology

45. Mid-process through silicon vias technology using tungsten metallization: Process optimazation and electrical results

46. Through Silicon Vias Technology for CMOS Image Sensors Packaging: Presentation of Technology and Electrical Results

47. Wafer level packaging technology development for CMOS image sensors using Through Silicon Vias

48. Through silicon vias technology for CMOS image sensors packaging

49. High Aspect Ratio Vias First for Advanced Packaging

50. Via First Technology Development Based on High Aspect Ratio Trenches Filled with Doped Polysilicon

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