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In the quantum mechanical simulation of exploratory semiconductor devices, continuum methods based on a k ⋅ p/envelope function model have the potential to significantly reduce the computational burden compared to prevalent atomistic methods. However, full-zone k ⋅ p/envelope function simulation approaches are scarce and existing implementations are not self-consistent with the calculation of the electrostatic potential due to the lack of a stable procedure and a proper normalization of the multi-band envelope functions. Here, we therefore present a self-consistent procedure based on a full-zone spectral k ⋅ p/envelope function band structure model. First, we develop a proper normalization for the multi-band envelope functions in the presence of transmitting boundary conditions. This enables the calculation of the free carrier densities. Next, we construct a procedure to obtain self-consistency of the carrier densities with the electrostatic potential. This procedure is stabilized with an adaptive scheme that relies on the solution of Poisson's equation in the Gummel form, combined with successive underrelaxation. Finally, we apply our procedure to homostructure In 0.53 Ga 0.47 As tunnel field-effect transistors (TFETs) and staggered heterostructure GaAs 0.5 Sb 0.5 /In 0.53 Ga 0.47 As TFETs and show the importance of self-consistency on the device predictions for scaled dimensions. [ABSTRACT FROM AUTHOR]

Efficient quantum mechanical simulation of tunnel field-effect transistors (TFETs) is indispensable to allow for an optimal configuration identification. We therefore present a full-zone 15-band quantum mechanical solver based on the envelope function formalism and employing a spectral method to reduce computational complexity and handle spurious solutions. We demonstrate the versatility of the solver by simulating a 40 nm wide In0.53Ga0.47As lineTFET and comparing it to p-n-i-n configurations with various pocket and body thicknesses. We find that the lineTFET performance is not degraded compared to semi-classical simulations. Furthermore, we show that a suitably optimized p-n-i-n TFET can obtain similar performance to the lineTFET. [ABSTRACT FROM AUTHOR]

Efficient quantum mechanical simulation of tunnel field-effect transistors (TFETs) is indispensable to allow for an optimal configuration identification. We therefore present a full-zone 15-band quantum mechanical solver based on the envelope function formalism and employing a spectral method to reduce computational complexity and handle spurious solutions. We demonstrate the versatility of the solver by simulating a 40 nm wide In0.53Ga0.47As lineTFET and comparing it to p-n-i-n configurations with various pocket and body thicknesses. We find that the lineTFET performance is not degraded compared to semi-classical simulations. Furthermore, we show that a suitably optimized p-n-i-n TFET can obtain similar performance to the lineTFET. [ABSTRACT FROM AUTHOR]

Promising predictions are made for III-V tunnel-field-effect transistor (FET), but there is still uncertainty on the parameters used in the band-to-band tunneling models. Therefore, two simulators are calibrated in this paper; the first one uses a semi-classical tunneling model based on Kane's formalism, and the second one is a quantum mechanical simulator implemented with an envelope function formalism. The calibration is done for In0.53Ga0.47As using several p+/intrinsic/n+ diodes with different intrinsic region thicknesses. The dopant profile is determined by SIMS and capacitance-voltage measurements. Error bars are used based on statistical and systematic uncertainties in the measurement techniques. The obtained parameters are in close agreement with theoretically predicted values and validate the semi-classical and quantum mechanical models. Finally, the models are applied to predict the input characteristics of In0.53Ga0.47As n- and p-lineTFET, with the n-lineTFET showing competitive performance compared to MOSFET. [ABSTRACT FROM AUTHOR]

Promising predictions are made for III-V tunnel-field-effect transistor (FET), but there is still uncertainty on the parameters used in the band-to-band tunneling models. Therefore, two simulators are calibrated in this paper; the first one uses a semi-classical tunneling model based on Kane's formalism, and the second one is a quantum mechanical simulator implemented with an envelope function formalism. The calibration is done for In0.53Ga0.47As using several p+/intrinsic/n+ diodes with different intrinsic region thicknesses. The dopant profile is determined by SIMS and capacitance-voltage measurements. Error bars are used based on statistical and systematic uncertainties in the measurement techniques. The obtained parameters are in close agreement with theoretically predicted values and validate the semi-classical and quantum mechanical models. Finally, the models are applied to predict the input characteristics of In0.53Ga0.47As n- and p-lineTFET, with the n-lineTFET showing competitive performance compared to MOSFET. [ABSTRACT FROM AUTHOR]

Heterostructure tunnel field-effect transistors (HTFET) are promising candidates for low-power applications in future technology nodes, as they are predicted to offer high on-currents, combined with a sub-60 mV/dec subthreshold swing. However, the effects of important quantum mechanical phenomena like size confinement at the heterojunction are not well understood, due to the theoretical and computational difficulties in modeling realistic heterostructures. We therefore present a ballistic quantum transport formalism, combining a novel envelope function approach for semiconductor heterostructures with the multiband quantum transmitting boundary method, which we extend to 2D potentials. We demonstrate an implementation of a 2-band version of the formalism and apply it to study confinement in realistic heterostructure diodes and p-n-i-n HTFETs. For the diodes, both transmission probabilities and current densities are found to decrease with stronger confinement. For the p-n-i-n HTFETs, the improved gate control is found to counteract the deterioration due to confinement. [ABSTRACT FROM AUTHOR]

2-D material FETs hold the promise of excellent gate control, but the impact of nonidealities on their performance remains poorly understood. This is because of the need, so far, to use computationally intensive nonequilibrium Green’s function (NEGF) simulations. Here, we therefore use a semiclassical model to investigate the role of nonidealities in the scaling of back-gated (BG) and top-gated (TG) monolayer MoS2 FETs. We verify the electrostatics and transport of the semiclassical model with density functional theory-based NEGF simulations and calibrate nonidealities, such as interface traps (${D}_{\textsf {it}}$) and Schottky contact barrier height ($\phi _{\textsf {SB}}$) to experimental monolayer and bilayer MoS2 FETs. We find that among the nonidealities, ${D}_{\textsf {it}}$ has the strongest subthreshold swing impact with 70 mV/dec obtainable in BG devices for a ${D}_{\textsf {it}}$ of $5\times {10}^{11}$ cm−2eV $^{-1}$ , an equivalent oxide thickness (EOT) of 1 nm, and a channel length (${L}_{\textsf {ch}}$) of 5 nm. For scaled EOT, $\phi _{\textsf {SB}}$ only strongly impacts ${I}_{ \mathrm{\scriptscriptstyle ON}}$ for the TG case, as the overlapping gate thins the Schottky barriers in the BG case. We show in TG devices that a spacer of only 5 nm results in a 1000-fold drop in ${I}_{ \mathrm{\scriptscriptstyle ON}}$ because of the nonidealities. We propose positive spacer oxide charge as a solution and show that a charge density of above 1013 cm−2 is required to fully recover the device performance. [ABSTRACT FROM AUTHOR]

Complementary logic based on tunnel field-effect transistors (TFETs) would drastically reduce power consumption thanks to the TFET's potential to obtain a sub-60mV/dec subthreshold swing (SS). However, p-type TFETs typically do not meet the performance of n-TFETs for direct bandgap III-V configurations. The p-TFET SS stays well above 60mV/dec, due to the low density of states in the conduction band. We therefore propose a source configuration in which a highly doped region is maintained only near the tunnel junction. In the remaining part of the source, the hot carriers in the exponential tail of the Fermi-Dirac distribution are blocked by reducing the doping degeneracy, either with a source section with a lower doping concentration or with a heterostructure. We apply this concept to n-p-i-p configurations consisting of In0.53Ga0.47As and an InP-InAs heterostructure. 15-band quantum mechanical simulations predict that the configurations with our source design can obtain sub-60mV/dec SS, with an on-current comparable to the conventional source design. [ABSTRACT FROM AUTHOR]

The tunnel field-effect transistor (TFET) is a promising candidate to replace the metal-oxide-semiconductor field-effect transistor in advanced technology nodes, because of its potential to obtain sub-60 mV/dec subthreshold swings. However, it is challenging to reach sufficiently high on-currents in TFETs. Therefore, on-current boosters are actively being researched. In this paper, a p-n-i-n TFET, containing a vertical pocket at the source-channel junction, is studied with quantum mechanical simulations and compared with a line tunneling TFET, containing horizontal pockets in the source region. The comparison is carried out both for all-Si and all-Ge, while an extrapolation is made for smaller bandgap materials. The p-n-i-n TFET is found to perform better than a p-i-n configuration, thanks to the increased electric field at the source-pocket junction. Compared to the p-n-i-n TFET, the line TFET has an even higher on-current and lower subthreshold swing, attributed to the closer proximity of the tunnel junction to the gate. For the all-Ge case, the difference between the two configurations is found to decrease when direct transitions are taken into account semi-classically. [ABSTRACT FROM PUBLISHER]

In tunnel field-effect transistors, trap-assisted tunneling (TAT) is one of the probable causes for degraded subthreshold swing. The accurate quantum-mechanical (QM) assessment of TAT currents also requires a QM treatment of phonon-assisted tunneling (PAT) currents. Therefore, we present a multi-band PAT current formalism within the framework of the quantum transmitting boundary method. An envelope function approximation is used to construct the electron-phonon coupling terms corresponding to local Fröhlich-based phonon-assisted inter-band tunneling in direct-bandgap III-V semiconductors. The PAT current density is studied in up to 100 nm long and 20 nm wide p-n diodes with the 2- and 15-band material description of our formalism. We observe an inefficient electron-phonon coupling across the tunneling junction. We further demonstrate the dependence of PAT currents on the device length, for our non-self-consistent formalism which neglects changes in the electron distribution function caused by the electron-phonon coupling. Finally, we discuss the differences in doping dependence between direct band-to-band tunneling and PAT current. [ABSTRACT FROM AUTHOR]

2D materials offer a pathway for further scaling of CMOS technology. However, for this to become a reality, both n-MOS and p-MOS should be realized, ideally with the same (standard) material. In the specific case of MoS2 field effect transistors (FETs), ambipolar transport is seldom reported, primarily due to the phenomenon of Fermi level pinning (FLP). In this study we identify the possible sources of FLP in MoS2 FETs and resolve them individually. A novel contact transfer technique is used to transfer contacts on top of MoS2 flake devices that results in a significant increase in the hole branch of the transfer characteristics as compared to conventionally fabricated contacts. We hypothesize that the pinning not only comes from the contact-MoS2 interface, but also from the MoS2-substrate interface. We confirm this by shifting to an hBN substrate which leads to a 10 fold increase in the hole current compared to the SiO2 substrate. Furthermore, we analyse MoS2 FETs of different channel thickness on three different substrates, SiO2, hBN and Al2O3, by correlating the p-branch ION/IOFF to the position of oxide defect band in these substrates. FLP from the oxide is reduced in the case of Al2O3 which enables us to observe ambipolar transport in a bilayer MoS2 FET. These results highlight that MoS2 is indeed an ambipolar material, and the absence of ambipolar transport in MoS2 FETs is strongly correlated to its dielectric environment and processing conditions. [ABSTRACT FROM AUTHOR]

Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices. [ABSTRACT FROM AUTHOR]

This work experimentally investigates current conduction in 3-D NAND under up to 7 GPa of externally applied compressive mechanical stress. The impact of channel crystallinity and geometry is studied by comparing four types of Si channels: polycrystalline full channel, single-crystal full channel, polycrystalline macaroni channel, and single-crystal macaroni channel. In the studied channel types, the mechanical stress was found to cause reversible degradation of ION (up to one order of magnitude) and IOFF (up to seven orders of magnitude). Using TCAD simulations, ION and IOFF deterioration are attributed to carrier mobility and Si bandgap decreases under mechanical stress, respectively. The simulations also suggest that both effects depend on the channel morphology, which results in a different extent of stress impact on the four studied types of Si channels. [ABSTRACT FROM AUTHOR]

The above-named article [ibid., vol. 60, no. 7, pp. 2128?2134, Jul. 2013] contains an error in the legend of Fig. 11. The correct version is provided. [ABSTRACT FROM AUTHOR]

We propose a storage memory device that enables bit densities of >1 Tbit/mm2 based on the electro- deposition and electrodissolution of multilayered metal stacks in deep nanometer-sized wells. This device addresses the challenge of bit density scaling slowdown expected for 3-D NAND flash beyond 2030. We describe in detail the operating principles and discuss the response time, bandwidth, retention, and cycling endurance requirements for the device to be viable. As a proof-of-principle, we provide a first demonstration of the write/read (W/R) mechanism on millimeter- and micrometer-sized electrodes and show the device’s potential for reaching very high bit densities. To evaluate how the response time scales for the envisioned nanometer-sized electrodes, we derive simple analytical expressions based on finite element simulations that relate the well depth, radius, and electrolyte composition to the deposition/dissolution rate. [ABSTRACT FROM AUTHOR]

The effective bandgap is a crucial design parameter of heterojunction tunneling field-effect transistors. In this letter, we demonstrate a method to measure the effective bandgap directly from the band-to-band tunneling current of a heterojunction Esaki diode, of which we only require knowledge of the electrostatic potential profile. The method is based on a characteristic exponentially increasing current with forward bias, caused by sharp energy filtering at cryogenic temperature. We apply this method experimentally to a n+In0.53Ga0.47As/pGaAs0.5Sb0.5 Esaki diode and define requirements to apply it to other heterojunctions. [ABSTRACT FROM AUTHOR]

The Tunneling Field-Effect Transistor (TFET) is a promising device for future low-power logic. Its performance is often predicted using semiclassical simulations, but there is usually a large discrepancy with experimental results. An important reason is that Field-Induced Quantum Confinement (FIQC) is neglected. Quantum mechanical simulations show FIQC delays the onset of Band-To-Band Tunneling (BTBT) with hundreds of millivolts in the promising line-TFET configuration. In this letter, we provide experimental verification of this delayed onset. We accomplish this by developing a method where line-TFET are modeled using highly doped MOS capacitors (MOS-CAP). Using capacitance-voltage measurements, we demonstrate AC inversion by BTBT, which was so far unobserved in MOS-CAP. Good agreement is shown between the experimentally obtained BTBT onset and quantum mechanical predictions, proving the need to include FIQC in all TFET simulations. Finally, we show that highly doped MOS-CAP is promising for characterization of traps deep into the conduction band. [ABSTRACT FROM AUTHOR]

Trap-assisted tunneling (TAT) is a major hurdle in achieving a sub-60-mV/decade subthreshold swing (SS) in tunnel field-effect transistors (TFETs). This paper presents an insight into the TAT process in the presence of field-induced quantum confinement (FIQC) in line TFETs. We show that the SS degradation in line TFETs is mainly caused by TAT through traps located in the bulk of the semiconductor nearby the gate dielectric. For an Si n-type TFET, the energy quantization in the conduction band is found to suppress the TAT through the interface-region traps by several orders of magnitude and delay the TAT through bulk traps nearby the gate dielectric with several hundreds of millivolts. The trap levels closer to the conduction band were found to be the most efficient for TAT in this n-TFET. The FIQC onset voltage shift in TAT through bulk taps is found to be smaller than the band-to-band tunneling (BTBT) shift, enhancing the effective SS degradation in TFETs. We therefore show that it is equally important to include the FIQC effect when calculating TAT as when calculating BTBT generation rates. [ABSTRACT FROM PUBLISHER]