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In addition to the haze, the captured images may also contain some amount of noise. The image dehazing approaches may be invalid when the input hazy image contains significant noises. To mitigate the effects of both haze and noise, a joint framework for image dehazing and denoising is vital. An effective framework for joint dehazing and denoising for single-image in real-time is proposed here. The VLSI design for the proposed framework is also presented. In the low-frequency (LF) subband, a hardware-friendly dehazing algorithm that makes use of the saturation-based transmission map (TM) estimation technique is used. In the high-frequency (HF) subbands, wavelet denoising combined with hard thresholding rule is used to improve the denoising capabilities. This research displays a competitive performance in the image quality of the dehazed visuals and computational effectiveness in the presence of Gaussian noise when compared to previous sophisticated dehazing algorithms. The hardware complexity of the suggested framework is reduced by using discrete wavelet transform (DWT) structures based on fractional wavelet filter (FrWF) and canonical-signed-digit (CSD) method. To the best of our knowledge, this is the first attempt to design and implement VLSI architecture for simultaneous dehazing and denoising in the wavelet domain. The proposed architecture is defined using Verilog hardware description language (HDL) and synthesized using the Cadence genus compiler. When employing the CSD technique, the proposed framework reduces area and power by 5.09% and 1.75%, respectively. The maximum operating frequency of the proposed architecture is 96.25 MHz. [ABSTRACT FROM AUTHOR]

This paper presents a novel hardware architecture for Frequency Response Masking (FRM) Filter Bank based on Residue Number System (RNS) arithmetic for Digital Hearing Aids (DHA). FRM is a computationally efficient approach for filter bank design that separates different frequencies based on the Audiograms of a patient. However, filter banks are critical power-hungry elements that require high computational resources. Therefore, the proposed architecture aims to provide an efficient implementation of FRM filter banks, which can improve the value and affordability of DHAs. The proposed architecture employs FIR filters in direct form, linear phase, and poly phase using RNS arithmetic. This approach enables the performance of arithmetic operations in parallel and independently. The concepts are further extended for the efficient implementation of FRM filter bank. The results of the proposed architecture show that direct implementation reduces the delay when the number of taps increases in the FIR filter. However, to reduce computational resources and optimize the area requirement, a Folded RNS architecture is also proposed. The Folded RNS architecture offers hardware savings of 23–27% for a 40-tap FIR filter and 29–31% for a 60-tap FIR filter. Additionally, it improves speed by 13–15% for a 40-tap FIR filter and 16–19% for a 60-tap folded RNS FIR filter. The implementation of FRM filter bank using the folded FIR filter shows the same trend in hardware saving and speed improvement as in the case of FIR filters. These results demonstrate that the proposed hardware architecture has the potential to improve the efficiency and affordability of DHAs while enhancing the listening comfort, which can enhance the quality of life for patients with hearing impairments. [ABSTRACT FROM AUTHOR]

In the event of an epileptic attack, the Field-Programmable Gate Array (FPGA)-accelerated Convolutional Neural Network (CNN) model is paired with Electroencephalogram (EEG) acquisition equipment to produce a reliable production system that can be used in clinical medical diagnosis. Additionally, this study includes cybersecurity to protect both the epileptic patient’s data and the prediction system. Epilepsy is a frequent neurological disorder that manifests as recurrent seizures, a sign that indicates rapid intervention is necessary to minimize adverse events and improve patient health. The study provides a new real-time design for predicting epileptic seizures based on the Application-Specific Integrated Circuit (ASIC)-based Very Large-Scale Integration (VLSI) architecture. As a first step, EEG data from epilepsy patients were captured and pre-processed. Afterwards, faults and artefacts in the data were removed. Additionally, data was divided into short-time windows and then classified as either ictal, pre-seizure, or interictal. The CNN model was adapted for EEG signal analysis and then trained with categorized data. This technique is more effective and efficient for predicting epileptic seizures accurately, which is advantageous for patient monitoring and treatment. Additionally, cybersecurity measures were implemented to secure patient data and the prediction system. [ABSTRACT FROM AUTHOR]

Polar codes are the popular error-correcting codes and increased their attention after being adopted for the control channel in fifth-generation new radio (5G NR) standards. An efficient hardware architecture for polar code is often required with minimal encoding and decoding complexity. This work proposes a Multi-folded pipelined architecture and analyzes the performance in terms of latency, hardware utilization, and throughput. The designed architecture has two folded architectures interconnected in parallel to output 4-bits simultaneously. Folding transformations are used to reduce the number of idle processing elements (PEs) in every stage leading to the effective utilization of PE. Precomputation is effectively utilized in the PE to reduce the critical path delay, which improves the maximum operating frequency. A Loop-based shifting register (LSR) is employed to reduce the number of registers used. The analytical model for latency and utilization rate has been derived from the scheduling of the proposed architecture. The proposed design shows 63–71% higher hardware utilization than conventional semi-parallel design for code length N = 512 suitable for the physical downlink control channel (PDCCH) in 5G NR. The architecture is also implemented in Virtex-6, ZYNQ-Ultrascale+ MPSoC device for maximum supported code length of 5G NR, i.e., up to 2 10 , compared with the existing decoders. The proposed design also has the benefit of lesser look-up-table (LUT) consumption and zero random-access-memory (RAM) usage with some additional registers, making it suitable for resource-constraint applications. [ABSTRACT FROM AUTHOR]

An efficient 2-D Finite Impulse Response (FIR) filter is designed using modified McClellan transformations with optimized coefficients. The P3 transformation is considered to attain sharp circular symmetry filters to reduce the complexity of the architecture of the 2-D FIR filter. The filter coefficients are represented in Canonical Signed Digit (CSD) space to construct the filter architecture by multiplierless design. The CSD representation is optimized using the Cuckoo Search Algorithm (CSA) with fitness function Mean Square Error (MSE). Further, a Fully Direct (FD) type architecture of a 2-D FIR filter is implemented according to the obtained CSD-based coefficients for the length of N × N = 11 × 11 . Each row filter structure is realized and explored. All the hardware structures of row filters were realized and integrated using Verilog HDL and synthesized by Genus tools provided by the CADENCE Vendor in a 45 nm CMOS generic library. The area, delay, and power reports are generated by this synthesis tool and compared with the existing 2-D FIR filter architectures. The area, power, and delay values of the proposed filter architecture are decreased by 28.9%, 49.59%, and 36.02%, respectively to the conventional filter architecture. The Power-Delay-Product (PDP) and Area-Delay-Product (ADP) values of the proposed filter architecture are reduced by a minimum of 2.14 and 1.96 times, and a maximum of 4.31 and 66 times to the existing filter architectures respectively. [ABSTRACT FROM AUTHOR]

The complex harmonic wavelet (CHW) for the discrete signal is orthogonal, compact support in the frequency domain but is not complex conjugate symmetric for positive and negative half-planes. The modified complex harmonic wavelet (MCHW) transform is the improved version of CHW as it is the complex conjugate symmetry along with other desired properties of CHW such as orthogonality, and compact support in the frequency domain. Due to the complex conjugate symmetry, MCHW has lesser computational complexity compared to CHW. This paper introduces a new VLSI architecture for MCHW for hardware implementation and prototyped on a commercially available virtex5 field-programmable gate array (FPGA). For the validation of the proposed implementation, the real-time captured results in the logic analyzer are verified with simulation results. The maximum operating frequency targeting the above-mentioned FPGA device is reported as 92.82 MHz. The total on-chip power of the above implementation is 1.117W, out of which 84 mW is the dynamic power dissipation at a toggle rate of 12.5 %. Finally, for the area utilization of the above implementation, its resource utilization targeting the above FPGA device is reported. [ABSTRACT FROM AUTHOR]

This work aims at optimizing the hardware implementation of the SubBytes and inverse SubBytes operations in the advanced encryption standard (AES). To this, the composite field arithmetic (CFA) is employed to optimize all building blocks in S-box (and inverse S-box) of SubBytes (and inverse SubBytes) transformation. A joint design of S-box and inverse S-box is also proposed to further enhance the area efficiency. Specifically, the area of multiplier in the Galois composite field, GF $((2^{2})^{2})$ , is reduced. The squaring and multiplication with constant $\lambda $ in GF $((2^{2})^{2})$ are combined and optimized as well. Moreover, the multiplicative inversion in GF $((2^{2})^{2})$ is manually optimized. Furthermore, the S-box and inverse S-box are combined and optimized using the pre_processing and post_processing modules. To increase the throughput, a balanced and pipelined architecture is derived. Using the proposed architecture, a throughput of 5.79 Gbps for the S-box can be achieved on Virtex-6 XC6VLX240T and 10% better than the conventional work. According to the ASIC implementation result, the proposed design can still achieve the highest area efficiency and approximately 30% better than conventional works using TSMC 90nm process.

Communication channels with memory are often sensitive to burst noise, which drastically reduces the decoding performance of standard channel code decoders, and this degradation worsens as channel memory increases. Hence, interleavers and de-interleavers are usually used to reduce the effects of burst noise at the expense of increased latency in the communication system. The delay imposed by interleavers/de-interleavers and the performance deterioration induced by channel memory are unacceptable in novel applications that require ultra-low latency and high decoding performance. Guessing Random Additive Noise Decoding (GRAND) is a universal Maximum Likelihood (ML) decoding technique for short-length and high-rate channel codes. GRAND Markov Order (GRAND-MO) is a hard-input variant of GRAND that has been specifically developed for communication channels with memory that are subject to burst noise. GRAND-MO can be used directly on hard demodulated channel signals, removing the requirement for extra interleavers/de-interleavers and considerably reducing overall latency in communication systems. This paper describes a high-throughput GRAND-MO VLSI architecture that can achieve an average throughput of up to 52 Gbps and 64 Gbps for code lengths of 128 and 79, respectively. Furthermore, we propose improvements to the GRAND-MO algorithm to simplify hardware implementation and reduce decoding complexity. When compared to GRANDAB, a hard-input variant of GRAND, the proposed improved GRAND-MO algorithm yields a decoding performance gain of 2 ∼ 3 dB at a target FER of 10 - 5 . Similarly, as compared to the (79, 64) BCH code decoder, the proposed GRAND-MO decoder has a 33% reduced worst-case latency and a 2 dB gain in decoding performance at a target FER of 10 - 5 . [ABSTRACT FROM AUTHOR]

Ultrareliable low-latency communication (URLLC), a major 5G new-radio (NR) use case, is the key enabler for applications with strict reliability and latency requirements. These applications necessitate the use of short-length and high-rate channel codes. Guessing random additive noise decoding (GRAND) is a recently proposed maximum likelihood (ML) decoding technique for these short-length and high-rate codes. Rather than decoding the received vector, GRAND tries to infer the noise that corrupted the transmitted codeword during transmission through the communication channel. As a result, GRAND can decode any code, structured or unstructured. GRAND has hard-input as well as soft-input variants. Among these variants, ordered reliability bits GRAND (ORBGRAND) is a soft-input variant that outperforms hard-input GRAND and is suitable for parallel hardware implementation. This work reports the first hardware architecture for ORBGRAND, which achieves an average throughput of up to 42.5 Gb/s for a code length of 128 at a target frame error rate (FER) of 10−7. Furthermore, the proposed hardware can be used to decode any code as long as the length and rate constraints are met. In comparison to the GRAND with ABandonment (GRANDAB), a hard-input variant of GRAND, the proposed architecture enhances decoding performance by at least 2 dB. When compared to the state-of-the-art fast dynamic successive cancellation flip decoder (Fast-DSCF) using a 5G polar code (PC) (128, 105), the proposed ORBGRAND VLSI implementation has $49\times $ higher average throughput, $32\times $ times more energy efficiency, and $5\times $ more area efficiency while maintaining similar decoding performance. [ABSTRACT FROM AUTHOR]

This paper presents a generalized novel design of a family of multiplier free orthogonal wavelet filter banks (FBs) with low complexity. In the proposed method, maximum number of zeros at $z=-1$ is ensured for a desired length of analysis and synthesis filters. A new class of technique is proposed to obtain dyadic filter coefficients based on double shifting orthogonality property with allowable deviation from original filter coefficients. This is achieved by slightly altering perfect reconstruction (PR) condition to obtain dyadic filter coefficient. A general closed form expression is formulated using double shifting orthogonality property to reduce the error between original filter coefficients and proposed dyadic filter coefficients. The designed wavelet FB improved time-frequency product, Sobolev regularity and frequency selectivity (low energy in error) over well known existing wavelet FBs. In addition, a fixed point VLSI architecture is proposed for the designed family of orthogonal wavelet FBs. The suggested architecture is designed and implemented on Kintex7 FPGA board. The proposed family of orthogonal wavelet FBs is multiplier less with significantly reduced adders, shifters and dynamic power dissipation. The performance of the proposed wavelet FB is validated on two different applications namely image compression and medical image retrieval. The proposed FBs are tested on well known datasets such as CLASSIC, EPFL, RAISE, and FiveK for image compression and on three different medical image databases such as NEMA, OASIS, and EXACT09 for image retrieval. [ABSTRACT FROM AUTHOR]

In this paper, we propose a low-complexity and high-speed VLSI architecture design methodology for complex square root computation using COordinate Rotation DIgital Computer (CORDIC). The proposed methodology is independent of angle computation in the CORDIC unlike the state-of-the-art methodologies. The proposed methodology is modelled in VHDL and synthesized under the TSMC 45-nm CMOS technology @ 1 GHz frequency. The synthesis results show that the proposed design saves 18.39%, 4.06% and 17.26%, 2.56% on chip area and power consumption when compared with the state-of-the-art methodologies without loss in accuracy. The proposed design saves the latency of 16 and 14 clock cycles when compared with the state-of-the-art implementations. The proposed design can process 23.4 and 127.344 billion additional samples per one joule energy when compared with the state-of-the-art designs. [ABSTRACT FROM AUTHOR]

The irrational coefficients of orthogonal wavelet filters require a large amount of hardware for their implementation. This results in huge memory requirement, increased power dissipation and reduction in speed of operation. This paper presents a new class of multiplier free db3 orthogonal wavelet filter bank with significantly reduced power dissipation, adders and shifters. In this paper, dyadic filter coefficients of db3 have been obtained by slightly altering double-shifting orthogonality property for perfect reconstruction. The proposed db3 wavelet filter improved time–frequency product, Sobolev regularity and frequency selectivity. Also, the VLSI architecture is suggested for the proposed db3 wavelet filter banks to analyse the hardware computational complexity. The performance of the proposed db3 wavelets achieved satisfactory performance for feature extraction in medical image retrieval and fingerprint recognition of infants and toddlers. [ABSTRACT FROM AUTHOR]

Stochastic computing (SC) has been applied on the implementations of complex arithmetic functions. Complicated polynomial-based approximations lead to large hardware complexity of previous SC circuits for arithmetic functions. In this paper, a novel piecewise approximation method based on Taylor series expansion is proposed for complex arithmetic functions. Efficient implementations based on unipolar stochastic logic are presented for the monotonic functions. Furthermore, detailed optimization schemes are provided for the non-monotonic functions. Using NAND and AND gates as main computing elements, the optimized hardware architectures have extremely low complexity. The experimental results show that a broad range of arithmetic functions can be implemented with the proposed SC circuits, and the mean absolute errors can achieve the order of 1 × 10-3. Compared with the state-of-the-art works, the approximation precision for some typical functions can be increased by more than 8× with our method. In addition, the proposed circuits outperform the previous methods in hardware complexity and critical path significantly.

Performing the image compression over the resource constrained hardware is quite a challenging task. Although, there has been various approaches being carried out towards image compression considering the hardware aspect of it, but still there are problems associated with the memory acceleration associated with the entire operation that downgrade the performance of the hardware device. Therefore, the proposed approach presents a cost effective image compression mechanism which offers lossless compression using a unique combination of the non-linear filtering, segmentation, contour detection, followed by the optimization. The compression mechanism adapts analytical approach for significant image compression. The execution of the compression mechanism yields faster response time, reduced mean square error, improved signal quality and significant compression ratio performance. [ABSTRACT FROM AUTHOR]

The discrete wavelet transform is commonly used as a denoising step for many applications, like biomedical applications which are usually suffering from low SNR of the recorded signal. However, the choice of appropriate threshold value for DWT coefficients plays significant role in reconstructing the denoised signal. This paper presents a design of real -time wavelet denoising architecture which is suitable for wide range of real-time denoising applications. In this design, an adaptive thresholding approach based on feedback control loop is proposed to make the architecture more applicable for real-time wavelet denoising. This thresholding method considers a noise level estimator module based on first detail coefficients level 𝑑1 to calculate the unknown standard deviation of background noise. The proposed architecture is developed using MATLAB to simulate the suggested denoising method. The performance of the proposed denoising method is studied in terms of integral gain 𝐺 of feedback control and window size 𝑀 with respect to the improvement in SNR and settling time. The results imply that the proposed denoising architecture is suitable for real-time denoising applications with acceptable improvement in SNR approximately 8 dB. [ABSTRACT FROM AUTHOR]

This brief presents a novel VLSI architecture for computing discrete wavelet packet transform (DWPT) for the continuous flow of data. Each stage of the proposed multi-stage architecture consists of the bit-reordering circuit and serial wavelet filter. The conventional wavelet filter has been modified for single path serial data. The intermediate coefficients are reordered with the help of a bit reordering circuit in order to maintain a continuous flow of data from input to output end with minimum memory and minimum latency. In comparison to the recently published architectures, the proposed one not only reduces the memory requirement by more than 50% but also achieves a 100% hardware utilization ratio. Furthermore, the area and power requirements are reduced by more than 60% and 50%, respectively. [ABSTRACT FROM AUTHOR]

Active contour segmentation is an important stage in image analysis applications. In this article, an improved region based active contour segmentation is proposed. The proposed active contour model speeds up the contour convergence by up to 40 % while maintaining the advantages of a local region based active contour model by reducing the number of iterations. Moreover, we propose a low-complexity pipelined VLSI architecture for improved region based active contour model targeting FPGA and 90 nm ASIC platforms. The proposed pipelined design offers an increased speed of operation. Its complexity is independent of the size of image. • An improved region based active contour model is proposed. • The improved region based active contour reduces number of iterations. • Complexity of the proposed pipelined architecture is independent of input image. • The proposed pipelined architecture improves the speed of operation. [ABSTRACT FROM AUTHOR]

A novel sparsity adaptive compressed sensing (CS) scheme based on Reed-Solomon (RS) codes is proposed to reduce the amount of sampled data, which can adjust the sampling rate adaptively to achieve data sampling and reconstruct the original data accurately by any decoding algorithm on the finite field. Moreover, the proposed sparsity adaptive reconstruction architecture can greatly improve the data reconstruction efficiency of the proposed CS scheme. The simulation results show that the sparsity adaptive scheme can reduce 83.6% of the sampled data. The results illustrate that the proposed architecture needs about 95k gates and operates at 500 MHz to achieve the throughout of 4.0 Gb/s, which can greatly improve the efficiency of the communication system. Meanwhile, it is at least 21.4% more area-efficient compared with previously reported fixed sampling rate architecture based on RS codes. [ABSTRACT FROM AUTHOR]

This paper presents a digital signal processing (DSP) architecture for real-time and distortion-free recovery of electrically-evoked compound action potentials (ECAPs) from stimulus artifacts and periodic noises in bidirectional neural response telemetry (NRT) system. In this DSP architecture, a low computation-cost bidirectional-filtered coherent averaging (BFCA) method is proposed for programmable linear-phase filtering of ECAPs, which can be easily combined with the alternating-polarity (AP) stimulation method to reject stimulus artifacts overlapped with ECAP responses. Design techniques including the configurable folded infinite-impulse response (IIR) filter and division-free averaging are also presented for efficient hardware implementation. Implemented in 180-nm CMOS process, the proposed DSP architecture consumes 10.03-mm2 area and 2.35-mW post-layout simulated power. The efficacy of the DSP architecture in recovering ECAPs from recorded neural data contaminated by overlapped stimulus artifacts and periodic noises is validated in in-vivo electrical nerve stimulations. Experiment results show that compared with the previous coherent averaging technique, the proposed DSP architecture improves the signal-to-noise ratio (SNR) of ECAP responses by 11 dB and achieves a 3.1% waveform distortion that is 17.1× lower. [ABSTRACT FROM AUTHOR]

With the increasing demand in electronic gadgets expecting better video quality for multimedia applications, various coding standards evolved for the past two decades and optimization on the architectures of the various modules used in the video codec is most popular. In this paper, an efficient architecture for deblocking filter used to smoothen the pixels of the decompressed video data is proposed, which utilizes both pipelining and parallelism. The filtering process follows a sequential order as filtering vertical edges of luma block and chroma block followed by the horizontal edges of the luma block and chroma block. Three pipeline stages are used and four edges, either vertical or horizontal are filtered in parallel. Internal buffers which hold the sub-blocks read from the external frame buffers are accessed in a ping pong fashion to filter the adjacent sub-edges and thus reducing the external memory access cycles. Due to parallelism with novel edge filtering order, self-transposing mechanism, and ping pong buffer access, the throughput is increased. The proposed quad parallel edge deblocking filter architecture is implemented using Synopsys 90 nm library. It achieves a target area of 19.8 K and can process a Macro Block in 58 clock cycles.

'Fast Fourier transform' (FFT), being a prevalent algorithm for the proficient computation of 'discrete Fourier transform,' constitutes one of the major sub-modules in numerous real-time signal processing systems. In this article, a new approach of CORDIC-based high-radix FFT architecture has been demonstrated. Having identified the complex rotation as the most time-consuming elementary operation of FFT, the number of such complex rotations has been optimized by adopting radix-8-based FFT computation. To add to this, CORDIC is employed to realize the complex rotation, keeping aside its multiplier–accumulator (MAC)-based counterpart, for further economizing the VLSI implementation of the proposed FFT architecture. Furthermore, the requirement of CORDIC blocks for last three stages of radix-8 FFT computation has totally been mitigated by utilizing SCALE blocks as the rotation in those stages can be expressed in terms of π / 4 or its multiples. RAM is arranged in the form of memory banks to provide parallel data path operations, and RAM switching is performed in between stages for sustaining continuous data flow circumventing data access hazards. The throughput of the proposed radix-8 architecture is eight outputs per clock cycle, while the maximum clock frequency is limited only by the propagation delay of an adder. Hardware utilization and comparative performance evaluation have been reported to prove the proposed architecture's supremacy. Our proposed prototype radix-8 architecture has been successfully implemented on Zynq UltraScale+ FPGA using Xilinx Vivado 18.2 software for verifying its feasibility in practical applications. [ABSTRACT FROM AUTHOR]

Pseudo Random Bit Generator (PRBG) is a need factor for getting data through transmission in different cryptographic applications. In the normal existing Pseudo random bit generation systems like Linear Feedback Shift Register (LFSR), Linear Congruential Generator (LCG), Coupled LCG (CLCG), and Dual Coupled LCG (Dual-CLCG), the last ends up being more secure. This technique relies upon correlations that causes pseudorandom bit generation at a non-uniform stretch. The drawbacks listed for this technique are excessive memory usage, high-initial clock latency, failing to grasp the foremost length sequence. In this paper we have proposed a Modified Dual-CLCG technique at a uniform clock rate to produce pseudorandom number. The tale commitment of the arranged PRBG method is to have pseudorandom bit with low power. The present proposed architecture offers significant improvement in terms of power and speed in comparison to other reported architectures. Architecture for LCG is compared with different devices so that Artix 7 shows least power having a value of 0.042W. The execution of PRBG strategy is simulated utilizing VHDL and is reconfigurable utilizing Artix 7 FPGA board. [ABSTRACT FROM AUTHOR]

Transform model estimation (TME) is a geometric operation, widely utilized in real-time imaging systems. Considering the massive computational load of matrix algebra-based TME realizations, most of the imaging systems resort to highly paralleled software-platform-based TME execution, which is power-intensive and expensive. Due to low-speed and power intensiveness, existing hardware for TME is not capable enough to meet the requirements of real-time systems. In this article, a hardware-realizable method of three-degree-of-freedom TME is formulated encompassing both the conventional CORDIC and the proposed modified CORDIC. The novelties of the proposed TME method and the corresponding architecture are that its latency sublinearly varies with the precision and the total computation time (CT) is almost independent of the input image sizes. The performance of prototype 16-bit fixed-point TME architecture (realized using VHDL in Xilinx Vivado 18.2) is compared with the software-counterpart. The proposed TME hardware is utilized along with other standard hardware modules to realize image registration (IR) operation. The proposed IR architecture achieves, on average, 60% reduction in total CT, $1.61 \times $ increase in maximum operating frequency with a comparable accuracy, only at the cost of 23% increase in power consumption with respect to other existing IR hardware. [ABSTRACT FROM AUTHOR]

This article proposes an encoding method based on a two-step encoding algorithm for the 12 quasi-cyclic (QC)-low-density parity-check (LDPC) (QC-LDPC) codes specified in the IEEE 802.11n/ac/ax standards. The proposed approach jointly considers all codes of the particular set, instead of targeting each code separately. The proposed algorithm performs multiplication by inverse matrices. The complexity of the multiplications is significantly reduced by the introduced encoding method. It allows the implementation of full-parallel architectures that execute the encoding process within a single clock cycle, or more for pipelined implementations, for any of the supported codes. A corresponding VLSI encoding architecture based on XOR-gate trees is also proposed. The proposed solution exploits the structure and features of the involved matrices to extract common subexpressions (CSs) using common sub-expression sharing techniques (CSST). Such expressions result due to common features of the original matrices and the corresponding inverses, identified in this article. Innovative subexpression extraction procedures that target the specific codes as a set are introduced here. Furthermore, illustrative single-clock hardware encoders derived by the proposed technique are integrated into 90- and 45-nm technologies at 1 GHz occupying 125 and 107 KGates, respectively, achieving throughput rates up to 1.62 Tbps. [ABSTRACT FROM AUTHOR]

Dedicated hardware realisation of 'Discrete Wavelet Transform' (DWT) is highly demanded for real-time multimedia operations in any handheld gadgets, as DWT is a popular transform-domain mathematical tool widely employed for many applications. Several DWT techniques exist in the literature assisting the software-based DWT realizations, inappropriate for real-time operations. There exist several hardware-based solutions for DWT. But most of the VLSI architectures of DWT fail to offer balanced performance, i.e. such architectures show good performance with respect to certain metrics while sacrificing other performance metrics. In this article, a convolutional DWT-based pipelined and tunable VLSI architecture of Daubechies 9/7 and 5/3 DWT filter is presented. The proposed architecture is designed with an ardent focus of maintaining balanced performance. The presented design, which blends the merits of convolutional and lifting DWT while dumping their demerits, is prepared area and memory efficient by employing 'Distributed Arithmetic' (DA) in our own ingenious method. Comparative experimental results justify the superiority of the proposed design regarding 30% area reduction, memory saving, remarkable clock frequency attainment and acceptable computation time. The proposed 2D DWT architecture is applied for real-time image decomposition. The outcomes of such real-time on-board testing prove the practicability of the presented work. [ABSTRACT FROM AUTHOR]

In this brief, a novel approximation method and its optimized hardware implementation are proposed for the sigmoid function used in Deep Neural Networks (DNNs). Based on piecewise approximation and truncated Taylor series expansion, the proposed method achieves very good approximation with low complexity while exploiting data representation with powers of two. In addition, by analyzing gradients of the sigmoid function, a small trick is introduced to improve the approximation precision. Furthermore, to reduce the hardware complexity and shorten the critical path, sampled values of the function are generated with simple logical-mapping. It is shown that the proposed approximation schemes can be implemented with purely combinational logic and the sigmoid function can be computed in one clock cycle. The experimental results demonstrate that the mean absolute errors are at the order of $1\times 10^{-3}$. Compared with prior arts, the new design can obtain significant improvement in critical path with comparable performance. [ABSTRACT FROM AUTHOR]

In this brief, we propose a low complexity VLSI architecture design Methodology for Wigner Ville Distribution (WVD) computation. The proposed methodology performs both auto and cross WVD computations using only the half number of Fast Fourier transform (FFT) computations as opposed to the state of the art methodologies. The FPGA implementation for proposed methodology was performed for 16 bit fixed point and 32 bit single precision floating point numbers on the Xilinx Virtex-7 FPGA (XC7vx485tffg). The proposed methodology saves 49% energy consumption when compared with the state of the art methodology. However it can be noted that the proposed methodology is independent of the VLSI implementation platform and technology node. [ABSTRACT FROM AUTHOR]

In this work we present least squares (LS) approach to design linear phase Finite Impulse Response (FIR) filter. Since the design of FIR digital filters is non-analytic, we aim at ideal zero-phase magnitude response and minimize the weighted error in passband and stopbands. The problem of least squares can then be solved non-iteratively by solving system of linear equations. Solution of which yields impulse response that is both real and symmetric. Frequency response of the proposed LS FIR filter shows a flat passband, and higher stop-band attenuation than traditional window based FIR design and comparable attenuation with Parks–McClellan method of the same order. In addition we have implemented LS FIR filter on FPGA based VLSI architectures. Performance evaluation of proposed LS FIR design on VLSI architecture shows comparable throughput, area and power consumption compared to classical filter design approaches. [ABSTRACT FROM AUTHOR]

To enable the continued scaling of distributed storage, failure recovery schemes that have low latency and low redundancy are indispensable. Minimum storage regenerating (MSR) codes have been developed to achieve this goal. Compared to other MSR codes, the recent coupled-layered (Clay) codes have many advantages such as low sub-packetization level, small finite field for construction, and uniform repair bandwidth over data and parities. This brief proposes efficient VLSI architectures for Clay encoder and decoder. Through exploiting subfield elements of finite fields, the logic complexity is substantially lowered. Additionally, the buffer size is reduced by optimizing the coupling scheme. For an example Clay code with (n,k)=(6,4), the proposed designs achieve 12% and 24% logic complexity reduction on the encoder and decoder, respectively, under the same timing constraint. [ABSTRACT FROM AUTHOR]

This article presents a piecewise linear approximation computation (PLAC) method for all nonlinear unary functions, which is an enhanced universal and error-flattened piecewise linear (PWL) approximation approach. Compared with the previous methods, PLAC features two main parts, an optimized segmenter to seek the minimum number of segments under the predefined software maximum absolute error (MAE), raising the segmentation performance to the highest theoretical level for logarithm, and a novel quantizer to completely simulate the hardware behavior and determine the required bit width and ${\text {MAE}}_{c}$ (MAE in circuits) for hardware implementation. In addition, the hardware architecture is also improved by simplifying the indexing logic, leading to nonredundant hardware overhead. The ASIC implementation results reveal that the proposed PLAC can improve all metrics without any compromise. Compared with the state-of-the-art methods, when computing logarithmic function, PLAC reduces 2.80% area, 3.77% power consumption, and 1.83% ${\text {MAE}}_{c}$ with the same delay; when approximating hyperbolic tangent function, PLAC reduces 6.25% area, 4.31% power consumption, and 18.86% ${\text {MAE}}_{c}$ with the same delay; when evaluating sigmoid function, PLAC reduces 16.50% area, 4.78% power consumption with the same delay, and ${\text {MAE}}_{c}$ ; and when calculating softsign function, PLAC reduces 17.28% area, 11.34% power consumption, 12.50% delay, and 33.28% ${\text {MAE}}_{c}$. [ABSTRACT FROM AUTHOR]

The Block Decoder (BD) which is an indispensable component of the JPEG 2000 image compression standard has the highest computational complexity and determines the speed of the overall decoder system. This paper proposes a high throughput pass parallel BD architecture, which can decode more than one bit per clock cycle. In BD, the dependency between context generation and arithmetic decoding unit incorporates stalling and reduces the throughput of the decoding process. The proposed selective byte input and synchronous sample skipping techniques are used to prevent stalling in the decoding process. The proposed architecture achieves 86% more throughput with 50% increment in the hardware cost than that of the best available serial BD architecture. In comparison with the best available pass parallel architecture, throughput improves almost 8.2 times with 61% increment in the hardware cost. Incorporation of the speed up techniques in the design is the main reason for more hardware consumption. The Figure of Merit of the proposed design, which is the ratio of throughput and hardware cost, is more than that of the available BD architectures for typical code block (CB) size of 32 × 32. The ASIC implementation of the proposed design consumes 66 mW power at maximum operating frequency. • High throughput pass parallel Block Decoder architecture for Point-of-Care applications. • Synchronous sample skipping and selective byte import techniques are proposed to improve throughput. • Efficient 3-subbank memory management technique is proposed to reduce unnecessary state memory access. [ABSTRACT FROM AUTHOR]

The metric-first-based multiple-input–multiple-output (MIMO) detection algorithm can achieve optimal performance with large stack size, which leads to huge memory consumption and extremely high-sorting complexity. This article presents the algorithm and architecture of a soft-input–soft-output metric-first MIMO detection. The proposed algorithm divides the global stack into multiple local stacks for each nonleaf of the tree. Furthermore, each level of the search tree is performed in parallel to improve the throughput and hardware efficiency. In the proposed algorithm, the hybrid enumeration strategy significantly reduces the computational complexity by avoiding the full enumeration and sorting. The simulation results show the novel algorithm can achieve good performance with lower complexity than other metric-first methods. The proposed detector has been designed for a $4\times 4\,\,64$ -QAM MIMO system and implemented in SMIC 65-nm CMOS technology. The detector can operate at 333-MHz clock frequency and achieve a maximum throughput of 799.2 Mb/s at a 17.3-dB signal-to-noise ratio with area equivalent 242 kg and power consumption of 102.3 mW, and the hardware efficiency is 3.3 Mb/s/kg. Compared with other detectors based on the metric-first algorithm, this article has an obvious advantage in terms of throughput and hardware efficiency. [ABSTRACT FROM AUTHOR]

A novel high-efficient reconstruction architecture of compressed sensing and an area-efficient integrated source-channel decoder based on Reed-Solomon (RS) code are proposed in this letter. The proposed reconstruction architecture only includes a parameter calculation (PC) block and a target locator and evaluator solution (TLES) block, resulting in 30 times higher throughput rate achieved and 85% area saved compared with previously reported reconstruction architecture based on orthogonal marching pursuit (OMP) algorithm. Moreover, the proposed integrated source-channel decoder can reduce 15.3% and 28.5% area respectively for the sampling rate of 25% and 12.5%. [ABSTRACT FROM AUTHOR]

The third generation (3G) of cellular communications standards is based on wideband CDMA. The wideband signal experiences frequency selective fading due to multipath propagation. To mitigate this effect, a RAKE receiver is typically used to coherently combine the signal energy received on different multipaths. An effective multipath searcher is, therefore, required to identify the delayed versions of the transmitted signal with low probability of false alarm and misdetection. This paper presents an efficient and novel WCDMA multipath searcher design and VLSI architecture that provides a good compromise between complexity, performance, and power consumption. Novel multipath searcher algorithms such as time domain interleaving and peak detection are also presented. The proposed searcher was implemented in 0.18 mu m CMOS technology and requires only 150 k gates for a total area of 1.5 mm(2) consuming 6.6 mw at 100 MHz. The functionality and performance of the searcher was verified under realistic conditions using a channel emulator.

This paper proposes an area-efficient fixed-point architecture for the computation of the discrete cosine transform (DCT) of multiple sizes in high efficiency video coding (HEVC). This result is obtained by comparing different DCT factorizations in order to find the most suitable one for implementation in the HEVC encoder. The recursive structure of fast algorithms, which decompose the $N$ -point DCT by means of two $N/2$ -point DCTs, is exploited to execute computations of small-size DCTs in parallel, thus maximizing the hardware re-usability while maintaining a constant throughput. The simulation results prove that the proposed solution features reduced rate-distortion loss es, with relevant complexity saving compared with the state-of-the-art implementations. Finally, the proposed architecture is exploited to design two families of architectures for the 2D-DCT, namely, folded and full-parallel. [ABSTRACT FROM AUTHOR]