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This paper demonstrates the gate-all-around P/N hybrid nanosheet p-channel junctionless field-effect transistors (GAA NS-JLFET) with trench and raised source and drain structure. The GAA NS-JLFET exhibits the superior electrical properties, including high field-effect mobility (18.9 cm2/Vs), high on/off current ratio (>5 × 106), steep subthreshold slope (136 mV/dec.), and low DILB (60 mV/V). The high mobility and steep subthreshold slope of this GAA NS-JLFET indicates that the conducting hole filled the whole thin nanosheet channel. This GAA NS-JLFET is simple to fabricate and highly favorable for use in advanced system-on-panel and three-dimensional stacked ICs applications.

The characteristic performance of n-type and p-type inversion (IM) mode, accumulation (AC) mode and junctionless (JL) mode, bulk Germanium FinFET device with 3-nm gate length (LG) are demonstrated by using 3-D quantum transport device simulation. The simulated bulk Ge FinFET device exhibits favorable short channel characteristics, including drain-induced barrier lowering (DIBL

In this paper, p-channel junctionless (JL) silicon-oxide–nitride-oxide–silicon (SONOS)-type nonvolatile memory (NVM) devices with gate-all-around (GAA) nanowire (NW) structure by using silicon-nanocrystal for the charge-trapping layer are presented. The devices exhibited good erase efficiency and excellent retention behavior and can be used in system-on-panel and 3-D-stacked flash memory applications. In addition, a band-to-band hot hole (BBHH) method for erasing is proposed and compared with the Fowler–Nordheim (FN) tunneling method. Because FN erasing requires a high gate voltage, BBHH erasing, which requires a low voltage, can increase the service life of the memory. Channel hot electron and band-to-band hot electron were used for programming and yielded low programming efficiency for the p-channel JL GAA NW NVM devices because of a lack of electron carriers. The program/erase efficiency is related to the channel type in JL NVM devices.

The fundamental of transistors of the circuits can be simulated by using L g = 15 nm FinFET CMOS Inverter and static random-access memory (SRAM). They will consume small amounts of power, and they are equipped with important characteristics of regenerating or cleaning up digital signals.

According to MOSFET scaling rule, the depletion layer formed in the channel of traditional 2D MOSFET near source and drain, the short-channel effect (SCE) has become inevitable along with the scaling of L g dimension.

Huge efforts are put into CMOS scaling to push the limits of Moore’s law. Semiconductor ICs manufacturing companies are currently ramping up 16-nm/14-nm FinFET processes, with 7 and 5 nm just around the corner.

In 1965, Gordon Moore proposed the rule that the number of devices on the wafer would be doubled every 18–24 months. This “Moore’s law” describes the continuous and rapid trend of scaling. Every reduction of feature size will be called a technology generation or technology node. The technology nodes include 0.18, 0.13, 90, 65, and 45 μm.

Technology computer-aided design (TCAD) refers to the use of computer simulations to develop and optimize semiconductor processing technologies and devices.

There will be junctions in the channels of source and drain of traditional inversion-mode (IM) MOSFET or FinFET, such as the nFET with doping style of N+PN+.

The simplest way for increasing the transistor density in the wafer is to reduce the feature size of transistor.

Since the development of metal-oxide-semiconductor field-effect transistor (MOSFET) started in 1950s, relevant technologies have been constantly improving (Sze and Ng in Physics of Semiconductor Devices. Wiley, New York, 2007 [1]).

This paper demonstrates a silicon-oxide-nitrideoxide-silicon (SONOS) nonvolatile memory (NVM) with fin-shaped polycrystalline silicon channel tunnel field-effect transistor (TFET). It differs from other memory devices in that its programming mechanisms include Fowler-Nordheim (FN) tunneling, channel hot-electron (CHE) injection, and band-to-band tunneling-induced hot electron (BBHE) in single memory cell. In FN programming, both the ON-state current and the program/erase (P/E) operations are based on quantum tunneling. For FN tunneling, when a V \(_{{{\rm G}}}\) of 17 V is applied for only 1 ms, this device has a large threshold voltage shift ( \(\Delta V_{\mathrm {\mathbf {TH}}}\) ) of 4.7 V. The fin-shaped TFET SONOS (T-SONOS) NVM exhibits superior endurance of 88% after 104 P/E cycles. The memory window remains 65% of its original value after 10 years at a high temperature of 85 °C. On the other hand, the device exhibits better endurance of 74% for CHE programming and BBHE programming after 104 P/E cycles. The memory window retains 81% in CHE programming and 65% in BBHE programming after 10 years. The fin-shaped T-SONOS NVM exhibits high performance that can be achieved in polycrystalline silicon NVM.

We investigated the device performance of the optimized 3-nm gate length ( $L_{G})$ bulk silicon FinFET device using 3-D quantum transport device simulation. By keeping source and drain doping constant and by varying only the channel doping, the simulated device is made to operate in three different modes such as inversion (IM) mode, accumulation (AC) mode and junctionless (JL) mode. The excellent electrical characteristics of the 3-nm gate length Si-based bulk FinFET device were investigated. The subthreshold slope values (SS $\sim $ 65 mV/decade) and drain-induced barrier lowering (DIBL $\vert V_{\rm TH}\vert \sim 0.31$ V. Furthermore, the threshold voltage ( $V_{\rm TH})$ of the bulk FinFET can be easily tuned by varying the work function. This letter reveals that Moore’s law can continue up to 3-nm nodes.

Silicon (Si) and Germanium (Ge) ultrathin body junctionless field-effect transistor (UTB-JLFET) with $L_{G}= 1$ nm and $L_{G} = 3$ nm were demonstrated by solving the coupled drift-diffusion and density-gradient model. The simulation results show that the Si and Ge channel can be used in ultrashort channel device as long as UTB is employed. As UTB is employed, ultra-short channel device does not need to follow an empirical rule of $T_{\rm ch} = \textrm {L}_{G}/3$ . Furthermore, Ge UTB-JLFET 6T-SRAM cell has reasonable static noise margin value of 149 mV. The circuit performances reveal that UTB-JLFET can be used for sub-5-nm CMOS technology nodes.

Pristine Li4Ti5O12 (LTO) and Ru-doped Li4Ti5O12 with the composition of Li4Ti4.95Ru0.05O12 (Ru-doped LTO) are synthesized by solid-state reaction. Ru doping into the lattice of LTO affects the electronic structure of LTO, leading to the modification of optical properties and improvement in electrochemical performance. The variations between pristine LTO and Ru-doped LTO in optical properties are investigated by UV–vis and Raman spectroscopy. In addition, the related microstructure is characterized by XRD, SEM and TEM. The enhancement in electronic conductivity of Ru-doped LTO can provide the discharge capacities of 222, 183 and 132 mAh/g at 1C, 5C and 10C, respectively, during the voltage window of 0.01–2.5 V. Furthermore, the capacity retentions are 95, 92 and 86% for 1C, 5C and 10C rates, respectively, at 100th cycles. The significant improvement in electrochemical performance demonstrates that ruthenium doped lithium titanate is promising as a high rate anode for lithium ion batteries.

Solid-state reactions are used for synthesizing Li 4 Ti 5 O 12 (LTO) of high purity and crystallinity. However, it is not easy to control the particle size of LTO in these reactions. In this study, an entanglement structure for an LTO/multi-walled carbon nanotube (MWCNT) composite is prepared by a ball-milling-assisted solid-state reaction. The LTO nanoparticles are confined in the interspace of the MWCNT matrix via this architecture control. The additive of MWCNTs can prevent the aggregation of LTO particles during the calcination process of the solid-state reaction. In addition, the entanglement of the MWCNTs and LTO creates an effective conductive network, which improves the conductivity of LTO. Therefore, the entanglement structure improves the electrochemical properties of LTO, such as the rate capability and cycle performance.

Unlike the high-temperature activation of dopants, such as rapid thermal annealing (RTA), the activation of dopants by low-temperature microwave annealing (MWA) suppresses their diffusion, reducing screening tunneling length ( $\lambda $ ). This letter compares low-temperature (490 °C) MWA with high-temperature (1050 °C) RTA of a fin-shaped polycrystalline silicon (Poly-Si) tunnel field-effect transistor (TFET). The band-to-band tunneling voltage ( $\mathrm{V}_{\mathrm {\mathbf {BTBT}}}$ ) indicates clearly that TFET annealed by MWA had a lower $\lambda $ than TFET that was annealed by RTA. The TFET that was annealed by MWA had a high ON/OFF current ratio of $10^{\mathrm {\mathbf {8}}}$ , a low subthreshold swing, and an almost negligible drain-induced barrier lowering.

Ultrathin channel trench junctionless poly-Si field-effect transistor (trench JL-FET) with a 2.4-nm channel thickness is experimentally demonstrated. Dry etching process is used to form trench structures, which define channel thickness ( $T_{\mathrm {CH}})$ and gate length ( $L_{G})$ . These devices ( $L_{G}= 0.5 \mu $ m) show excellent performance in terms of steep subthreshold swing (100 mV/decade) and high $I_{\mathrm{{\scriptstyle ON}}}/ I_{\mathrm{{\scriptstyle OFF}}}$ current ratio ( $10^{6}$ A/A) and practically negligible drain-induced barrier lowering ( $\sim 0$ mV/V). The $I_{\rm \mathrm{{\scriptstyle ON}}}$ current of the trench JL-FET can be further increased by the quantum confinement effect. Importantly, owing to its excellent device characteristics and simplicity of fabrication, the trench JL-FET has great potential for using in advanced 3-D-stacked IC applications.

Li4Ti5O12 and Ru-doped Li4Ti5O12 with the formulation of Li4Ti4.99Ru0.01O12 were prepared by a modified solid-state method. The structure and electrochemical properties of the as-prepared powders were systematically investigated. Li4Ti4.99Ru0.01O12 exhibited an excellent rate capability with a discharge capacity of 146 mAhg− 1 at 1 C, 126 mAhg− 1 at 5 C, 119 mAhg− 1 at 10 C and even 107 mAhg− 1 at 20 C. Electrochemical impedance spectra (EIS) reveal that the Li4Ti4.99Ru0.01O12 exhibited the improved electronic conductivity and higher lithium-ion diffusivity than that of Li4Ti5O12. The novel Li4Ti4.99Ru0.01O12 material stands as a promising potentially high rate anode material for the lithium ion batteries.

Pure Li 4 Ti 5 O 12 , modified Li 4 Ti 5 O 12 /C, Li 4 Ru 0.01 Ti 4.99 O 12 and Li 4 Ru 0.01 Ti 4.99 O 12 /C were successfully prepared by a modified solid-state method and its electrochemical properties were investigated. From the XRD patterns, the added sugar or doped Ru did not affect the spinel structure. The results of electrochemical properties revealed that Li 4 Ru 0.01 Ti 4.99 O 12 /C showed 120 and 110 mAh/g at 5 and 10 C rate after 100 charge/discharge cycles. Li 4 Ru 0.01 Ti 4.99 O 12 /C exhibited the best rate capability and the highest capacity at 5 and 10 C charge/discharge rate owing to the increase of electronic conductivity and the reduction of interface resistance between particles of Li 4 Ti 5 O 12 .It is expected that the Li 4 Ru 0.01 Ti 4.99 O 12 /C will be a promising anode material to be used in high-rate lithium ion battery.

A composite anode material was prepared with confined tin into multiwall carbon nanotube by carbothermal reduction. The morphology and structure of Sn/C (nature graphite) and Sn/C-C (nature graphite + multiwall carbon nanotube) were characterized by scanning electron microscopy (SEM) and X-ray diffraction (XRD). It was revealed that the additive of MWCNT was a crucial factor to improve Sn /C composite anodes for cyclability and reversible capacity. Volume changes and morphological changes in Sn can be reduced by encasing MWCNT in a carbonaceous material that has sufficient flexibility to act as a buffer. Electrochemical performance test shows that the charge capacity of the Sn/C-C (NG + MWCNT) electrode in the fiftieth cycle was 400 mAh/g, which was higher than that of the Sn/C (NG) electrode. After 50 cycles, the retention of the Sn/C-C electrode and the Sn/C electrode was 80% and 63%, respectively.

A composite anode materials was prepared that contained tin compounds of Sn 6 O 4 (OH) 4 , SnO 2 and Sn 3 PO 4 on the surface of carbonaceous mixture mesophase graphite particles (MGP) and nature graphite (NG). The nanosize tin compounds were electrolessly plated from aqueous solutions onto the carbonaceous mixture. The morphology and structure of tin compounds were characterized by scanning electron microscopy (SEM) and X-ray diffraction (XRD). It was found that the tin compounds particle size was a crucial factor to improve Sn compounds/Carbon composite anodes for cyclability and reversible capacity. The homogeneous dispersion and smaller particle size of tin compounds was attributed to the additive of NG. As the carbonaceous substrate was C–C mixture carbon, the particle size of Sn compounds was about 20–30 nm. However, the particle size was 100–200 nm, as the carbon substrate was singular MGP. Electrochemical performance test of the Sn compounds/C–C composite electrode shows the maximum specific charge capacity of 583 mAh g −1 at the 5th cycle. The charge capacity retention of Sn compounds/C–C electrode was 85% after 20 cycles. The reversible capacity of Sn compounds/C–C electrode increased 292 and 97 mAh g −1 more than pristine (NG + MGP) electrode and Sn compounds/C electrode at the 5th cycle, respectively.

Recently, combination of ductile carbonaceous materials with the metallic Sn has received a great deal of interest to be a novel anode material for lithium ion batteries, because of their higher capacity than the conventional graphite anodes and better cycleability than the pure Sn anodes. Electrochemical performance of the Sn/C composite anodes is influenced by the material system, particle size and size distribution of Sn as well as the amount of deposited Sn. This study revealed that a favorable Sn/C composite anode exhibited reduced size and uniformly distributed tin particles. The crystal structure, morphology and elemental distribution were analyzed by XRD patterns, SEM and EPMA, respectively. The carbothermal-reducted Sn/Mesophase graphite powder (MGP) composite anodes exhibited much higher capacity than the bare MGP, and the initial efficiency was also much higher than the metallic tin anode in literatures.

Ag and In-doped ZnS thin films were prepared by direct current and radio frequency reactive co-sputtering of a zinc target and an indium target covered by Ag wires in gas mixtures of argon and hydrogen sulfide. The influences of the various deposition parameters on the structural, optical and electrical performances of thin films as visible-light-active photoelectrodes have been investigated. The X-ray diffraction data revealed that the polycrystalline (Ag, In, Zn)S thin films contain mixed structures of AgIn 5 S 8 and ZnS. The images from an atomic force microscopy showed that the surface roughness was significantly increased with incremental increases of plasma power, resulting in increases of the refractive index and the reduction in photocurrent. The film deposited in the optimal deposition parameters, DC and RF powers at 50 W using a hydrogen sulfide ratio of 0.40 with a substrate temperature of 300 °C, exhibits the smallest refractive index, highest donor density, and the highest photocurrent density under illumination with a solar simulator (AM 1.5) at + 1.00 V vs. Ag/AgCl. The band-gap energies of as-prepared films are found to be in the range of 2.28 to 2.39 eV and flat-band potentials determined by application of the Mott–Schottky equation vary from − 0.55 to − 0.68 V versus normal hydrogen electrode.

This letter describes an asymmetric gate tunnel field-effect transistor (AG-TFET) with a gate-all-around (GAA) structure in the source and a planar structure in the drain. It has a low OFF-state current (6.55 ×10-16 A/μm) and a high ON-state current (2.47 ×10-5 A/μm) because the screening length λ of a GAA nanowire structure is half that of the planar structure. Simulations reveal that a subthreshold swing as low as 42 mV/decade and an ON/OFF current ratio as high as 1010 are realized. The AG-TFET is easily fabricated as an actual device by simply changing the layout of gate in a general TFET fabrication.

The characteristics and sensitivities of p-type junctionless (JL) gate-all-around (GAA) (JLGAA) nanowire transistors are demonstrated by simulating a 3-D quantum transport device with a view to their use in CMOS technology. The concentration of dopants in a p-type JL nanowire transistor is not as high as that in an n-type device owing to solid solubility of boron in silicon. However, we can use a midgap material as gate electrode to design an appropriate device threshold voltage. The p-type JLGAA transistor exhibits a favorable on/off current ratio and better short-channel characteristics than a conventional inversion-mode transistor with a GAA structure. Sensitivity analyses reveal that the channel thickness and random dopant fluctuation substantially affect the device performance in terms of threshold voltage (Vth), on current (Ion), and subthreshold slope because of the full depletion condition of the channel. The channel length and oxide thickness have less impact because the short-channel effect is well controlled.

The novel trench junctionless poly-Si thin-film transistor (trench JL-TFT) with ultra-thin body (2.4 nm) is utilized to simple dry etching process. This novel devices show excellent performance in terms of steep SS (99 mV/dec.) and high I ON /I OFF (>107). The I ON current of the ultra-thin body (UTB) JL-TFT is increased by quantum confined effect.

This work demonstrates a feasible single poly-Si gate-all-around (GAA) junctionless fin field-effect transistor (JL-FinFET) for use in one-time programming (OTP) nonvolatile memory (NVM) applications. The advantages of this device include the simplicity of its use and the ease with which it can be embedded in Si wafer, glass, and flexible substrates. This device exhibits excellent retention, with a memory window maintained 2 V after 104s. By extrapolation, 95% of the original charge can be stored for 10 years. In the future, this device will be applied to multi-layer Si ICs in fully functional systems on panels, active-matrix liquid-crystal displays, and three-dimensional (3D) stacked flash memory.

This study proposed the twin poly-Si fin field-effect transistor (FinFET) nonvolatile memory with a structure that is composed of Ω-gate nanowires (NWs). Experimental results show that the NW device has superior memory characteristics because its Ω-gate structure provides a large memory window and high program/erase efficiency. With respect to endurance and retention, the memory window can be maintained at 3.5 V after 104 program and erase cycles, and after 10 years, the charge is 47.7% of its initial value. This investigation explores its feasibility in the future active matrix liquid crystal display system-on-panel and three-dimensional stacked flash memory applications.

A silicon junctionless (JL) trench gate-all-around (GAA) nanowire field-effect transistor with an atomically thin channel thickness of 0.65 nm and a very thin oxide with a thickness of 12.3 nm are demonstrated experimentally. Experimental results indicate that this device with a channel thickness of 0.65 nm achieves a sub-threshold slope (SS) of 43 mV/decade, which is the best yet achieved by any reported JLFET. Owing to the atomically thin channel, this device has an extremely high ION/IOFF current ratio of >108. Furthermore, the atomically thin channel GAA JLFET exhibits a low threshold voltage (VTH) variation and negligible drain-induced barrier lowering (DIBL

In this study, we for the first time assess the characteristics and sensitivity of p-type junctionless (JL) gate-all around (GAA) nanowire transistor using 3D quantum transport device simulation for CMOS technology implementation. Since the doping concentration of p-type junctionless nanowire transistor does not as high as in n-type device due solid solubility of boron in silicon, it can be made by using midgap gate electrode material for appropriate threshold voltage. The p-type JLGAA transistor shows good on/off current ratio and better short channel characteristics compare to conventional inversion mode GAA structure. The sensitivity analyses show that the channel thickness affects the device performance such as threshold voltage (V th ), on current (I on ), and off current (I off ) significantly. In contrast, the channel length and oxide thickness have less impact owing to well control of short channel effect.

Pure Li4Ti5O12, modified Li4Ti5O12/C, Li4Ru0.01Ti4.99O12, and Li4Ru0.01Ti4.99O12/C are prepared by solid state reaction of LiCl, TiCl4, RuCl3, and (COOH)2 or sucrose (800 °C, 10 h).

This work presents p-channel and n-channel junctionless (JL) polycrystalline silicon (poly-Si) nanowires gate-all-around (GAA) nonvolatile memory (NVM) devices with silicon nanocrystals charge trapping layer. Experimental results indicate that the n-channel device has better programming efficiency and p-channel device has better erasing efficiency. For p-channel device, an extrapolation of the memory window to 10 yr demonstrates that 95% of the stored charge can be retained at high temperature of 85 °C. Such the p-channel and n-channel JL-GAA NVMs are feasible for use in system-on-panel (SOP) and 3-D stacked flash memory applications.

This work demonstrates the feasibility of a charge-trapping nonvolatile memory based on Pi-gate polycrystalline silicon tunneling field-effect transistor, which has a silicon-oxide-nitride-oxide-silicon structure. Both the conducting current and the program/erase operations are based on quantum tunneling. In addition to a large threshold voltage shift of 4.7 V when Vg of 17 V is applied for only 1 ms, the proposed nonvolatile memory exhibits superior endurance of 88% after 104 P/E cycles. Moreover, only 35% of its initial charges are lost after ten years at a high temperature of 85 °C.

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