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With lots of interest in negative capacitance field-effect transistors for ultralow-power complementary metal-oxide-semiconductor technology, negative capacitance thin-film transistors (NCTFTs) have also received much attention. Although previous studies on NCTFTs were done, the NC effect in organic-based TFTs was not studied yet. In this paper, P(VDF-TrFE) ferroelectric-gated P3HT semiconductor channel TFTs are experimentally demonstrated with solution-based fabrication process. Especially, this paper shed light on the NC effect in the organic based TFTs. The step-up current-voltage characteristics are repeatedly and reliably observed in diverse TFTs, and then, with the results, transconductance (gm) amplification implemented by the negative capacitance was delved. Moreover, with the aid of ferroelectric polarization switching, super steep-switching characteristic of the organic-based TFT was experimentally confirmed. These experimental results and discussion would be helpful in understanding NC effects in TFTs. [ABSTRACT FROM AUTHOR]

The operating voltage of a nanoelectromechanical (NEM) relay can be scaled down significantly using negative capacitance (NC), which is a unique property of ferroelectric materials. It has been observed that a ferroelectric capacitor can amplify the internal voltage of a device (higher than the externally applied voltage) by means of the NC effect. In this simulation work, depending on the structural parameters of a ferroelectric capacitor and an NEM relay, an NC + NEM relay (in which the gate electrode of the NEM relay is connected in series to the ferroelectric capacitor) was investigated. As a result, a sub-0.5-V operating voltage is theoretically estimated. [ABSTRACT FROM AUTHOR]

With the negative capacitance (NC) effect of ferroelectric materials, a sub-60-mV/decade subthreshold slope in a conventional field-effect transistor has been theoretically and experimentally demonstrated. In order to utilize the NC for complementary metal-oxide-semiconductor logic device applications, it is necessary to closely examine various parameters for the device performance. Specifically, the analysis of effective drive current (i.e., Ieff={IDS@[VDS =0.5VDD, VG=VDD] + IDS@[VDS=VDD, VG=0.5VDD]}/2) of the NC device is vital. In this work, Ieff of a NC fin field-effect transistor (FinFET), in which a baseline 70 nm FinFET is electrically integrated with a ferroelectric capacitor, is experimentally measured to explore the correlation between hysteresis and Ieff. [ABSTRACT FROM AUTHOR]

The performance and threshold voltage variability of fully depleted silicon-on-insulator (FD-SOI) MOSFETs are compared against those of conventional bulk MOSFETs via 3-D device simulation with atomistic doping profiles. Compact (analytical) modeling is then used to estimate six-transistor SRAM cell performance metrics (i.e., read and write margins, and read current) at the 22 nm CMOS technology node. The dependences of these metrics on cell ratio, pull-up ratio, and operating voltage are analyzed for FD-SOI versus bulk SRAM cells. Iso-area and iso-yield comparisons are then made to determine the yield and cell-area benefits of FD-SOI technology, respectively. Finally, the minimum operating voltages (Vmin) required for FD-SOI and bulk SRAM cells to meet the six-sigma yield requirement are compared. [ABSTRACT FROM AUTHOR]

The impact of random dopant fluctuation (RDF) on the performance variation of a PNPN feedback field effect transistor (PNPN FBFET) is investigated using a 3D technology computer aided design tool. To investigate RDF-induced device performance variation (e.g. threshold voltage (VTH) variation), the nominal doping profile of each region in a PNPN FBFET is separately randomized. Consequently, in terms of RDF-induced VTH variation, the channel-2 region (i.e. gated channel region) plays a key role as a main contributor to VTH variation, as it is the most decisive region for determining gate-to-channel controllability. As an example, the value of σVTH resulting from the channel-2 region is nine times higher than that from the channel-1 region. Based on the simulation results, guidelines for variation-immune device design are comprehensively discussed. [ABSTRACT FROM AUTHOR]

The impact of line edge roughness (LER) on gate-all-around FETs (GAAFETs) with various channel types is investigated. Among various channel types of GAAFET, (i) nanowire (NW), (ii) nanosheet (NS), and (iii) stacked channel are investigated. Considering the Si/SiGe stacking and selective etching process (which is commonly used to release the channel of GAAFET), we modeled the LER profile for channels. Moreover, 3D LER modeling is adopted to represent the LER profile in non-planar device structure. It turned out that the NS channel GAAFET has not only higher on-state drive current but also better performance variation immunity than the NW channel GAAFET. This is because the aspect ratio of channel affects the LER profile. Compared against single-channel GAAFET, the stacked channel GAAFET has better variation immunity because of its complementary effect in-between stacked channels. To investigate the impact of complementary effect, we simulated two different stacked channels, one of which has no correlation between stacked channels, and the other of which has the correlation induced from the channel-releasing processing step. It turned out that the stacked channel GAAFET with no correlation in-between the channels can have better variation-robustness. [ABSTRACT FROM AUTHOR]

In this study, the electrical characteristics of negative-capacitance junctionless nanowire FETs (NC-JL-NWFET) with an HfO2-based ferroelectric layer are investigated through 3D Sentaurus TCAD and MATLAB simulations. The performances of NC-JL-NWFETs with various aspect ratios (ARs) (i.e., the ratio of horizontal radius to vertical radius), doping concentrations (N), thicknesses of ferroelectric layers (Tfe), and different ferroelectric materials, are studied. The NC-JL NWFETs show improved performances over a broad range of the parameters, compared with the baseline JL-NW-FETs, in terms of subthreshold slope (SS) and on/off drain current ratio (Ion/Ioff). Additionally, the impacts of the mentioned parameters on the negative-capacitance effect are presented in terms of the internal voltage (Vint). The optimal parameters with NC-JL is compared to NWFETs with doping junction (J-NW), and then, showed better performance for low power device applications. [ABSTRACT FROM AUTHOR]

Thin films of ferroelectric materials are potential candidates to be implemented in the unfolding of a new paradigm in high-density memory devices. As the thickness of these films reaches the sub-10 nm level, the interface properties between the electrode and ferroelectric material undergo significant changes that play a crucial role in governing the ferroelectric behavior. The present state-of-the-art approach presents a detailed investigation of different high pressure annealing (HPA) conditions through simulation studies. The simulation studies were performed using Landau–Khalatnikov equations, with Landau’s parameters calculated using the least regression method as described in the Method S1. The extracted coefficients were used to determine various relationships (free energy, ferroelectric potential and negative capacitance) with which to observe the impact of HPA on the negative capacitance (NC) effect on account of the majority ferroelectric phase. To verify the simulation results, pulse transient switching measurements were conducted using Pt/Ti/TiN/Hf0.5Zr0.5O2/TiN-based metal-ferroelectric-metal (MFM) devices to study the coercive field, interfacial capacitance and load resistance behavior. The results suggest that the non-ferroelectric portion (t-phase) coexists with the ferroelectric (o-phase) within the thin layer of the MFM capacitor adjacent to TiN electrode, which undergoes a phase transformation from the t-phase to the o-phase when exposed to different HPA conditions as well as electric field cycling during PS measurements. The simulation and experimental results confirm that the 550 °C at 50 atm N2 environment provides the best possibility of achieving the highest ferroelectric characteristics with the lowest proportion of the non-ferroelectric phase and thus the maximum NC effect as well. [ABSTRACT FROM AUTHOR]

For stacked multiple-channel-structure devices such as stacked nanowire FETs (stacked NWFETs), work-function variation induced (WFV-induced) threshold voltage (VT) variation is quantitatively investigated using a three-dimensional technology computer aided design (TCAD) tool. In the stacked structure device, the more nanowires are stacked, the more the WFV-induced VT variation can be decreased. It is proposed that the ratio of average grain size to gate area (RGG) for stacked multiple channel structures can be used to estimate the WFV-induced VT variation. For accurate estimation, the effective gate area (GAeff) should be considered in the stacked structure, as the variation is averaged out by stacking multiple channels. If two 3-stacked NWFETs have the same GAeff but different nanowire diameters (i.e. one with 10/10/10 nm and the other with 7/9.34/13 nm), the two would have identical WFV-induced VT variation. In this context, if a single NWFET and a 2-stacked NWFET have identical GAeff, the two would have the same VT variation. Using the RGG concept with GAeff enables the WFV-induced VT variation to be precisely estimated, regardless of nanowire diameter and the number of nanowires. [ABSTRACT FROM AUTHOR]

In this study, the transient responses of polarization switching in a Pb(Zr0.52Ti0.48)O3 (PZT) ferroelectric capacitor are experimentally investigated. In order to measure the transient response of polarization switching in the ferroelectric capacitor, a conventional RC circuit consisting of a resistor and the PZT ferroelectric capacitor is first built. Then, to investigate the impact of the number of domains in the ferroelectric capacitor on the transient response, the three different sizes of top electrodes of the capacitor are chosen. The results show that the ferroelectric capacitor with a small-sized electrode is charged faster than the other capacitors with medium/large-sized electrodes. It is concluded that the number of domains affects the charging behavior, i.e., the ferroelectric capacitor is charged faster as the number of domains decreases. The effect of static terms (i.e., the alpha and beta parameters) on the transient responses is also studied. From the experimental data obtained above, the differential voltage amplification due to the polarization switching is observed. Using the multidomain Landau-Khalatnikov model, a circuit-level simulation is provided to support the experimental evidence. The simulation results show that the differential voltage amplification increases as the value of rho (ρ) coefficient decreases. [ABSTRACT FROM AUTHOR]

Herein, we introduce an interdigitated horizontal electrode (IHE) structure with a metal-based electron-collecting (or -injecting) electrode and a hole-collecting (or -injecting) electrode composed of a conductive polymeric material that has a nanoscale distance and is horizontally separated. In the IHE, a metal electrode is fabricated on a silicon-oxide substrate, and a self-assembled monolayer (SAM) is selectively bonded to the metal and the oxide to form a conductive polymer electrode by dip coating. Each of the SAM materials is composed of a head part bonded to the substrate surface and a tail part that is hydrophilic or hydrophobic. This inherent property makes the metal electrode hydrophobic and the oxide substrate hydrophilic. Ag is used as a metal electrode material and is combined with alkanethiol SAMs. The alkylsilane SAMs are combined with the silicon oxide substrate to make them hydrophilic, using poly (3, 4-ethylenedioxythiophene)-poly (PEDOT: PSS) as the conductive polymer material. In this study, we have found that there is a difference in the spacing between the two electrodes that depends on the combination of SAM materials. Each interval was spaced from a minimum of 140 nm to a maximum of 385 nm. [ABSTRACT FROM AUTHOR]

The improvement of drain-induced barrier lowering (DIBL) in hysteresis-free and ferroelectric-gated fin field effect transistors (FinFETs) [a.k.a., negative capacitance (NC) FinFET] has been experimentally verified. Moreover, all fabricated NC FinFETs (some of which are not hysteresis-free) have successfully shown sub-60-mV/decade subthreshold slope (SS) characteristics. By adjusting both the fin width and channel length, the ferroelectric and dielectric capacitance matching in the gate stacks of FinFETs is successfully implemented, resulting in hysteresis-free NC FinFETs with a 20 mV/decade SS. Finally, the negative DIBL phenomenon in the hysteresis-free NC FinFET has produced an enhanced DIBL of 20.78 mV/V (note that the DIBL of baseline FinFET is 68.89 mV/V at 300 K). [ABSTRACT FROM AUTHOR]

The energy-delay characteristics of a nanoelectromechanical (NEM) relay can be improved incomparably by using negative capacitance (NC) in a ferroelectric capacitor. This can augment the internal voltage of a device, which is larger than the externally applied voltage. In this study, the energy-delay product of an NC + NEM relay (in which the ferroelectric capacitor is connected to a switching electrode of an NEM relay in series), as well as the adhesion force of the relay, is investigated. The enhanced energy-delay property of an NEM relay is demonstrated theoretically. [ABSTRACT FROM AUTHOR]

Drain-induced-barrier-lowering (DIBL) is one of short-channel-effects (SCEs) of conventional field effect transistors (FET), which results in lowering the threshold voltage of short-channel transistors. To properly control the DIBL of FinFETs, it is well known that the fin width of the FinFET can be adjusted (usually, a narrower fin width to enhance gate-to-channel coupling). In this work, the fin width effect of FinFETs (vs. ferroelectric-gated FinFETs, a.k.a., negative capacitance (NC) FinFETs) on the DIBL has been investigated and compared. As a result, it is experimentally verified that the NC-FinFET has superior gate-to-channel controllability and better subthreshold swing due to the negative capacitance effect of ferroelectric capacitor. [ABSTRACT FROM AUTHOR]

A negative capacitance field-effect transistor (FET) with sub-60 mV/decade subthreshold slope (SS) at different temperatures (i.e. 14.8 mV/decade at 300 K, 15.7 mV/decade at 360 K and 24.3 mV/decade at 400 K) is experimentally demonstrated. A detailed account of the fabrication process of a negative capacitor is first introduced, followed by the measurement setup for the negative capacitance FET. The impact of temperature on negative capacitance FETs is investigated: (i) the equation for the internal voltage gain in the FET as a function of temperature is derived using Gibbs free energy and (ii) internal voltage against gate voltage (VInt against VG), internal voltage gain against gate voltage (dVInt/dVG against VG) and drain current against gate voltage (ID against VG) curves at different temperatures are measured. It is confirmed that internal voltage amplification can be achieved using the ferroelectric capacitor. However, the magnitude of the step-up voltage transformation is reduced, i.e. from 9.5 at 300 K to 2.6 at 400 K. Additionally, the SS is slightly increased (i.e. degrading from 14.8 mV/decade at 300 K to 24.3 mV/decade at 400 K) with increasing temperature; however, all SS values are better than the physical limits of SS as dictated by Boltzmann statistics. [ABSTRACT FROM AUTHOR]

Advances in semiconductor technology have enabled significant performance improvements over the past several decades. However, at the current pace of the development of semiconductor technology, it is increasingly important to achieve a proper balance between performance improvement and power consumption. In this study, to quantitatively analyze the performance and power consumption of new technologies, a compact effective-current model is proposed and used for power performance analysis (PPA). The PPA is performed by separately varying several device characteristics such as drain-induced barrier lowering (DIBL), mobility, and threshold voltage (VT) to determine which options can provide more benefits and better balance for new technologies. The analysis results indicate that the performance improvement due to DIBL reduction (especially below 20 mV/V) is limited. However, VT engineering has more advantages than DIBL and mobility enhancement, unless threshold voltage scaling induces leakage current degradation. Otherwise, mobility enhancement is the most attractive method. By using the proposed compact effective-current model for PPA, we enabled the effective and quantitative estimation of the benefits in terms of performance and power consumption. [ABSTRACT FROM AUTHOR]