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ASIC advances are forcing us to make radical changes in the way we simulate and sign off silicon. To keep pace with increasing complexity and to achieve the timing accuracy […]

If you examine your design requirements, design-cycle time application and end-use objectives, you should be able to select a complex PLD or FPGA that satisfies your most important requirements. With […]

Is BIST the best strategy for embedded memory? Will the overhead for testability be worth it? What are the testability issues for analog blocks? How important is at-speed emulation for […]

If you're in a position to purchase programmable logic devices, time devoted to learning what the PREP (Programmable Electronics Performance) benchmarks can and cannot do for you will be well […]

This month, Open Verilog International (OVI) presents its case for the standardization of the Verilog hardware description language (HDL), long the de facto standard in the field, to members of [...]

Verilog has refused to die and OVI's patrons are breathing new life into it. At the same time, VHDL is thriving in the worldwide arena. Will you have to choose […]

With FPGAS such hot items, silicon vendors have had a captive audience. In concentrating on silicon, however, FPGA vendors haven't always delivered toolsets that were easy to use or boasted […]

The use of FPGAs is growing explosively, forcing veteran programmable logic vendors to enhance performance with new-generation products. At the same time, more semiconductor giants are being tempted to enter […]

Still dealing with custom more than semicustom, analog designers plod along the trail without the help of synthesis, a standard analog HDL or test methodology. But the determined can still […]

Although testability is finally getting the respect it deserves from both vendors and users, it's clear that if you're designing testability into complex ASICs using today's tools, you'll still have […]

Recent advances in high-level synthesis technology and system verification through reprogrammable hardware emulation have pushed in the direction of hardware/software codesign and promise to enhance your ability to bring error-free [...]

Gate arrays and standard-cell ASICs are still the big winners when it comes to product development, but FPGAs are closing in with competitive benefits such as design flexibility, reduced cost [...]

Not much has happened with 5-ns-and-faster PAL products since focusing on that technology a year ago (see 'High-speed PALs keep pace with today's processors,' Computer Design, Oct. 1990, p 75). [...]

Analog design is still an art because the sophisticated analog specialist is the only one aware of all the nuances and complexity of a design. But for digital and system [...]

Synthesis is no longer perceived as a mysterious technology. Rather, it's being recognized as the design methodology that unlocks the silicon opportunities of the 1990s. Designers who have been exposed [...]

High-density ASICs force focus on testability High gate counts and maturing software tools have changed the economics of ASIC design. While ever-more-sophisticated tools have automated other tasks, the reliance on […]

Are mixed cells and arrays the solution ASIC vendors claim? As customers clamor for shorter turnaround times for complex ASIC designs, silicon vendors are pushing the practice of putting down […]

Analog-to-digital converters, digital displays, ICs, and microprocessors have allowed a digital revolution in instrumentation over the past few decades. An early digital readout called the nixie tube, made by Burroughs, […]

The elongated run times of increasingly complex IC and board designs have forced silicon and software vendors alike to chase after network-distributed processing. ASIC designers are finally getting a taste […]

High-speed PALs keep pace with today's processors About the only thing that makers of high-speed PALs agree on is that designers will need parts fast enough to support their 40- […]

Caught up in the integration race, ASIC vendors have pushed silicon beyond the design, assembly and test resources of most OEMs. Advanced processes with submicron geometries have brought to market […]

Test can be likened to the middle child; it's given no attention until it causes problems While the more glamorous aspects of the ASIC design cycle have held the industry [...]

Because silicon is only as competitive as the tools used to design it, vendors involved in the hot FPGA and complex PLD market have been scurrying to deliver what they [...]

To a market taken with programmable technologies such as PROMs, FPGAs and PLDs, VLSI Technology (San Jose, CA) has introduced a new concept in programmability: programmable functional system blocks (pFSBs) [...]

The complexity of both silicon and the systems into which it's going is forcing designers to higher levels of abstraction for complex ASICs, and the use of synthesis is putting […]

Leading ASIC vendors have been preparing for the rush to notebook, palmtop and penbased computers by introducing low-voltage cell-based and gate array products. Among the latest to turn out 3-V […]

When looking for high-fault-coverage test programs, you have to decide if you're willing to support full scan, or if a back-end approach will be less intrusive. Mentor Graphics (Wilsonville, OR) […]

So far, VHDL's user acceptance is still behind that of Verilog, which is perceived to be a de facto industry standard. Core issues such as the lack of tools and [...]

High-level synthesis unlocks potential of FPGAs Field programmable gate arrays (FPGAs) are proving to be not only the hottest technology but also the most unfathomable. Promising close to a magical [...]

CrossCheck testability reaches commercial gate array family It took longer than expected, but, more than three years after CrossCheck Technology (San Jose, CA) was founded, the first commercial silicon implementation […]

Chase for process portability prompts advances in cell library tools With the trend toward technology-independent design, library developers require parameterized cell representations that can be modified and reused as design […]

PLDs catch up to FPGAs in logic capacity and I/O It seems no turf is secure in the ASIC market. Boundaries are becoming increasingly blurry as high-density programmable logic devices […]

In a market where a product can be a dinosaur 18 months after it's first shipped, design teams are being encouraged to explore alternative, cost-effective technologies to speed product development. […]

A new floorplanning tool for submicron gate arrays, Compass Design Automation's ChipPlanner gives ASIC vendors and designers placement and timing analysis features that bridge the gap between design intent and [...]

Though there's much talk about HDL-based top-down design, the truth is most tools available today start at the middle, at the register-transfer level (RTL). Designers are, for the most part, […]

Processed in Hewlett-Packard's production-proven 0.8-(micro)m CMOS technology, Actel's ACT 3 FPGAs share the PLICE antifuse interconnect technology of ACT 1 and 2 devices, but capitalize on improvements in the circuit [...]

Prism from NeoCAD is the first timing-driven software tool to provide automatic post-map partitioning of logic functions into multiple FPGAs in the same family. Available as an option to the [...]

With real technological innovation apparently stalemated, suppliers of design automation tools are zeroing in on business opportunities that fall under the category of services. Vendors have discovered that it takes […]

If you're fed up with arguments concerning the advantages of VHDL over Verilog or vice versa, and you simply want libraries and tools that help get your job done, you [...]

Fueled by expectations that by 1995 the field-programmable gate array (FPGA) market will be more than five times what it was last year (consuming 1/3 of the gate array market), […]

The ADAS fault simulator from start-up ADAS Software employs a proprietary algorithm based on parallel differential fault simulation to achieve fast simulation time and reduce hardware memory requirements. With the [...]

After proving that silicon process technology has advanced to the point of turning out gate arrays with hundreds of thousands of gates, semiconductor vendors are now getting around to putting [...]

Anticipating how much impact any new technology will have on the industry is always difficult, especially if that technology is high-priced and perceived by the user as risky. But a […]

For use at both customer sites and at Gould AMI, the new Mixed-Signal Design Solution (MSDS) incorporates analog model generators as well as analog design-for-testability features. Gould AMI claims that […]

The Q20P025 ECL array from Applied MicroCircuits offers users digital logic gates and an on-chip phased-lock loop (PLL), with operating frequencies from 200 MHz to 1.25 GHz, to serialize and […]

The XLProcessor (XLP) simulation accelerator from Cadence Design Systems is the hardware implementation of the same XL algorithm that drives the Cadence Verilog-XL and VHDL-XL software simulators. XLP resides in […]

The bottom line in the programmable device market is to give designers the fastest time-to-market with the highest-speed device. The founders of Peer Research, now QuickLogic (Santa Clara, CA), having […]