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A novel substrate-triggered grounded-gate NMOS (GGNMOS) is verified in 65 nm CMOS silicide process. The trigger element is a PMOS controlled by the VDD bus line and no other detection circuit is needed. Compared to traditional GGNMOS, with a 50 µm trigger PMOS, the trigger voltage of the single finger structure can be reduced from 7.15 to 4.97 V and it also has lower overshoot voltage. Also the ultrathin gate oxide can be effectively protected, which is very important in nanometre circuits. For the multi-finger structure, with a 30 µm trigger PMOS the proposed structure showed a 15.9% reduction in trigger voltage and a 13.5% increment as to failure current compared to traditional GGNMOS. [ABSTRACT FROM AUTHOR]

All-optical ultra-wideband (UWB) doublet pulse generation based on the multiple nonlinear effects of a single semiconductor optical amplifier (SOA) is demonstrated. First, a monocycle pulse is obtained by means of cross-gain modulation and self gain-saturation in the SOA, and a Gaussian pulse at conjugated light is obtained using four-wave mixing of the SOA. Secondly, the Gaussian pulse at the conjugated light is combined with the monocycle pulse by proper time delay to form a doublet pulse. The central frequency and 10 dB bandwidth of the doublet radio frequency are 5 and 6.25 GHz, respectively. The scheme is simple since only a single SOA is required. [ABSTRACT FROM AUTHOR]

40 Gbit/s reconfigurable photonic logic gates with XNOR, AND, NOR, OR and NOT functions are demonstrated, based on various nonlinearities of a single semiconductor optical amplifier (SOA), including four-wave mixing (FWM), cross-gain modulation (XGM) and transient cross-phase modulation (T-XPM). Detuning optical bandpass filters are employed to enhance the SOA modulation bandwidth. [ABSTRACT FROM AUTHOR]

An ultrafast all-optical logic AND gate is realised based on two cascaded Semiconductor optical amplifiers (SOAs) each followed by an optical filter to accelerate the effective recovery process of the SOAs. 40 Gbit/s operation with return-to-zero signals has been achieved with SOAs, the 90–10% recovery time of which is much greater than the single bit period. Clear open eyes with quality factor of 6.3 are observed. The proposed AND gate has a potentially loose requirement on input pulse width. [ABSTRACT FROM AUTHOR]

A phase-coherent transformer (PCT) enabled 22 GHz dynamic frequency divider in 0.18 µm CMOS with 16 dB power gain, 7 dB phase noise reduction and superb speed-gain/power FOM of 2×102/pJ is demonstrated. The on-chip PCT enforces energy reverberation between the sensing/latching stages and enhances the frequency divider efficiency by eliminating the ‘slave’ stage and the buffer amplifiers. [ABSTRACT FROM AUTHOR]

A simple method for spectral response simulation of micro-ring resonators by combining the transfer matrix method with the FDTD method is presented. After calculating the inner circulation factor and coupling efficiencies using the FDTD method, spectral responses of micro-ring resonators are obtained using the transfer matrix method. It is shown that simulation results are in agreement with results in the literature. [ABSTRACT FROM AUTHOR]

Complementation silicon controlled rectifiers (CSCRs) with various novel layouts are designed in 0.18 µm RF CMOS process, including general CSCR, strip CSCR (SCSCR), island-strip CSCR (ISCSCR) and island-block CSCR (IBCSCR). SCSCR has highest FOM; however, the ISCSCR has lowest parasitic capacitance. Appropriate division layout of the CSCRs should be addressed to achieve a balance between active area capacitance and edge capacitance. [ABSTRACT FROM AUTHOR]

Because of its simple structure and snapback characteristics, the grounded-gate NMOS (GGNMOS) has been widely used as an electrostatic discharge (ESD) protection device. ESD performance of GGNMOS fabricated in the 65 nm CMOS process is investigated, and measurement results for the snapback behaviour, failure current It2, holding voltage, and trigger voltage of such advanced MOS devices are illustrated. The effects of four key GGNMOS parameters, channel length, finger number, drain-to-gate spacing and source-to-gate spacing on the ESD performance, are considered, and optimal MOS structures for robust ESD protection applications are suggested. [ABSTRACT FROM AUTHOR]

All-optical single-to-dual channel format conversion from non-return-to-zero (NRZ) to return-to-zero (RZ) using four-wave mixing (FWM) in a single semiconductor optical amplifier (SOA) is demonstrated. The original NRZ format is converted to RZ format by injecting a synchronised clock signal into the SOA. The FWM effect generates two sideband components, which contain the same data stream as the original NRZ signal with RZ format. The format conversion is successfully implemented both at 20 and at 40 Gbit/s, and all converted RZ signals have a Q-factor larger than 6. [ABSTRACT FROM AUTHOR]

Reported is an all-optical high-speed three-input logic AND gate using cascaded sum- and difference-frequency generation (cSFG/DFG) in a periodically poled lithium niobate (PPLN) waveguide. The converted idler wave via cSFG/DFG carries the AND result of the three-input signals. PPLN-based 40 Gbit/s three-input logic AND operations for both non-return-to-zero (NRZ) and return-to-zero (RZ) signals are successfully demonstrated in the experiment. [ABSTRACT FROM AUTHOR]

This 60 GHz voltage controlled oscillator (VCO) uses an on-chip resonator with embedded artificial dielectric in place of the LC tank. The advantages are reduced metal/substrate losses and higher resonator Q with 4.7 times reduction in length and 79% reduction in area. Occupying an active area of 0.015 mm2, this 90 nm CMOS VCO consumes only 1.9 mW. It shows very low phase noise of -107 dBc/Hz at 1 MHz frequency offset and an unprecedented F.O.M. of -200 dBc/Hz, which outperforms III-V HBT and SiGe BiCMOS technologies. [ABSTRACT FROM AUTHOR]

A 60 GHz CMOS differential receiver front-end has been demonstrated by using a novel transformer-folded-cascade (Origami) circuit architecture with high gain (24 dB without buffer amplifier), high linearity (-11 dBm input referred P1 dB compression point, or IRCP), low power dissipation (4.3 mW/arm) and small die area (0.022 mm2). [ABSTRACT FROM AUTHOR]

A novel decimal optical buffer based on a multi-loop configuration and an optical cross-point switch matrix is proposed and experimentally demonstrated. Its variable delay range is of 1–999 times the basic delay unit. The buffer dynamic reconfiguration can be achieved in nanosecond switching speed. Experimental results show that a differential phase-shift keying payload and an ON-OFF keying payload can be processed in such a buffer for 9.1 µs with a penalty of 3.3 and 6.5 dB, respectively. [ABSTRACT FROM AUTHOR]

A 24 GHz monolithic low-noise amplifier (LNA) is implemented in a standard 0.18 mm CMOS technology. Measurements show a gain of 12.86 dB and a noise figure of 5.6 dB at 23.5 GHz. The input and output return losses are better than 11 dB and 22 dB across the 22-29 GHz span, respectively. The operation frequency of 24 GHz is believed to be the highest reported for LNA in a standard CMOS technology. [ABSTRACT FROM AUTHOR]