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In this paper, we propose a scheme to design the reconfigurable filtering power divider with arbitrary operating channels based on external quality factor ($Q_{\mathbf {e}}$) control. By using an input feeding line, ${n}$ resonators, and $m$ output feeding lines, the $n^{\mathbf {th}}$ -order $m$ -way filtering power divider topology can be obtained with a simple configuration. A coupled-line output feeding structure loading with multiple PIN diodes is proposed to adjust the output $Q_{\mathbf {e}}$ values. Design theories for obtaining the desired $Q_{\mathbf {e}}$ values are provided. Then, the filtering power divider can be fully reconfigured in the states with one to $m$ operating channels. Good input matching can be achieved without using an additional reconfigurable impedance matching network in all these states, resulting in a size and loss reduction. For verification, a 2nd-order 4-way reconfigurable filtering power divider is designed, fabricated, and measured. As compared to the reported reconfigurable power dividers, the proposed design shows the merits of fully reconfigurable operating channels, favorable filtering responses, low insertion losses, high isolation, and a simple structure. [ABSTRACT FROM AUTHOR]

This paper presents a novel static digital pre-distortion (DPD) method for a current-steering digital-to-analog converter (CS-DAC). The proposed method utilizes the knowledge of the current cell array architecture to calculate the static mismatch currents of the cells. The mismatch values are stored in memory and added to the original input code to generate the new pre-distorted input word. The converter corrects the static error with its own current cells without incorporating an additional calibration DAC (CALDAC) or programmable current sources. This results in a reduction in area, power and simulation run times because of the simpler circuit design. An Overflow-Cell-Selection (OCS) is introduced as a novel solution to further enhance the static linearity of the converter. It also can be implemented as a software solution for already existing DAC designs which do not have an integrated DPD and lab/measurement equipment (e.g., arbitrary wave generator (AWG)). This poses as a strong differentiation factor compared to other state-of-the-art static DPD methods. The evaluation of the proposed DPD is done via simulations in MATLAB and on- chip measurements with a 14-bit CS-DAC in 16 nm. Single tone measurements show a performance gain of the total harmonic distortion (THD) of 12 dB. [ABSTRACT FROM AUTHOR]

The series-paralleling technique of dc-dc converters is utilized in various domains of electrical engineering for improved power conversion. Previous studies have proposed and classified the control schemes for the series-paralleled converters. However, they have several restrictions and lack diversity. The purpose of this paper is to propose passivity-based control (PBC) for the diverse output series-parallel connection of dc-dc converters. It is proved that the output series-paralleled converters regulated by PBC are asymptotically stable. The output series-paralleled converters are numerically simulated to confirm the asymptotic stability. PBC is shown to maintain the stability of the output series-paralleled converters with diverse circuit topologies, parameters, and steady-states. The result of this paper theoretically supports the numerical and experimental considerations in the previous studies and justifies the further extension of the series-parallel connection. [ABSTRACT FROM AUTHOR]

Energy harvesting techniques provide solutions for powering battery-free circuits or even for charging storage elements such as batteries or super capacitors. In this paper a self-starting switched-capacitor approach based on three-stage charge pump that is appropriate to thermoelectric and photo-voltaic energy harvesting, is carried out in a 28 nm ultra-thin buried oxide (UTBB) fully-depleted silicon-on-insulator (FD-SOI) CMOS technology. By taking advantage of the FD-SOI substrate characteristics, the forward-body-biasing (FBB) technique is applied in order to improve switch conductances. In addition, a sizing exploration of standard N-type and flipped-well P-type devices operating as switches is advanced, in order to provide optimum balance between their conductances. Extensive simulation results validate the proper operation of the charge pump at a minimum input voltage of 150 mV, and show a maximum efficiency peak of 63.3% at an input voltage of 350 mV and load a current of 500 nA. [ABSTRACT FROM AUTHOR]

On the emerging development of SiC MOSFET, the switching frequency of power converters has been pushed to the order of hundreds of kilohertz or even megahertz to improve power density. However, the state-of-the-art simulations for such high-frequency power electronics circuits are usually time-consuming, blocking the studies of long dynamics such as several seconds. What’s worse, adopting physical models to simulate the turn-on and turn-off transients leads to high stiffness and therefore convergence problems. In this paper, an event-driven approach is proposed to improve the solving speed and simulation stability of SiC based high-frequency converters. A time-scale hierarchical automaton is proposed to model the system, where piecewise analytical transient model for SiC MOSFET is established as the second layer in the automaton to simulate the switching transients with improved numerical stability. Simulation of the system is driven by discrete events in the automaton. A 3.3 kW 79.1 kHz wireless power transfer system for the wireless charging of electric vehicle is studied. Compared with ideal switch model in Simulink and physical switch model in LTspice, 60-fold and 400-fold increases in terms of simulation speed with same level of accuracy are achieved respectively. The simulated results are also attested to by experimental verifications. [ABSTRACT FROM AUTHOR]

Silicon Carbide (SiC) MOSFETs are usually paralleled to increase the current capability for high power applications. While, the asymmetrical parasitic parameters of the wide-used laminated busbar can cause current imbalance for paralleled MOSFETs. The fast switching of SiC devices can further deteriorate the imbalance. However, the complex current paths and their mutual effects are seldom considered and effectively modeled for the parasitics of the busbar, which is not accurate enough to evaluate the current imbalance for the busbar connected with SiC devices. This paper proposes accurate modeling of the effective parasitic parameter of laminated busbars with paralleled SiC MOSFETs. The model incorporates not only the self-inductance and resistance but also the complex mutual coupling effect of all the current paths. Moreover, a switching period is divided into two durations for accurate effective parasitic models, in which the busbar can have different effective models regarding one physical structure. Furthermore, for easy evaluation of the current balance, a single effective model, namely equivalent model, is derived for a physical structure by replacing the complex mutual network. A specific laminated busbar for EV inverter is analyzed to prove the above theory, which is validated by simulation and experiment separately. [ABSTRACT FROM AUTHOR]

This paper presents a 32-channel analog filterbank for front-end signal processing in sound classification systems. It employs a passive N-path switched capacitor topology to achieve high power efficiency and reconfigurability. The circuit’s unwanted harmonic mixing products are absorbed by the machine learning model during training. To enable a systematic pre-silicon study of this effect, we develop a computationally efficient circuit model that can process large machine learning datasets on practical time scales. Measured results using a 130 nm CMOS prototype IC indicate competitive classification accuracy on datasets for baby cry detection (93.7% AUC) and voice commands (92.4% average precision), while lowering the feature extraction energy compared to digital realizations by approximately $2\times $ and $10\times $ , respectively. The 1.44 mm2 chip consumes 800 nW, which corresponds to the lowest normalized power per simultaneously sampled channel in recent literature. [ABSTRACT FROM AUTHOR]

Power is becoming a major bottleneck in energy constraint applications such as internet-of-things (IoT). Emerging steep-slope devices such as tunnel FETs (TFET) and negative capacitance (NC) FETs are promising candidates for such type of applications. Nevertheless, due to the time-consuming characterization process and inconsistent evaluation criteria, conventional co-design and co-optimization process between novel devices and logic circuits takes too much time and its results rarely meet expectation. As a result, conventional co-design and co-optimization are quite inefficient. In this paper, for the first time, a new criterion is utilized to evaluate novel steep-slope devices for ultra-low power applications. In addition, an efficient evaluation method is proposed, which not only quantitatively guides device design, but also evaluates devices from a circuit perspective without the need for device compact model and circuit simulation. From a device design perspective, optimal design metrics of novel steep slope devices such as average subthreshold slope ($SS_{avg}$), off current (${I} _{OFF}$), and on current (${I} _{ON}$) can be directly figured out with the help of the proposed evaluation criteria and method. From a circuit design perspective, the proposed evaluation criteria and method can be used to determine application scope. [ABSTRACT FROM AUTHOR]

This paper presents a two-way time-interleaved (TI) 7-bit 2-GS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) in 28 nm CMOS. The design achieves wideband operation with an effective resolution bandwidth (ERBW) in the 3rd Nyquist zone. The converter’s front-end employs current integrating (CI) sampler that provide both buffering and anti-alias (AA) filtering at low power dissipation. Facilitated by the CI-samplers’ inherent inter-sample interactions, the timing mismatch among the TI channels can be detected in the amplitude domain, obviating the need for a dedicated reference channel for background calibration. After calibration, the ADC achieves 36.4 dB signal-to-noise-and-distortion ratio (SNDR) near Nyquist and >2.6 GHz ERBW at a sampling rate of 2 GS/s. The ADC’s power consumption is 7.62 mW (including the CI buffer) and its Walden figure of merit (FoMw) is 70.8 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper presents a systematic approach to synthetize constant power loads using switching converters under sliding-mode control. The generation of sliding motions is analyzed in converters with a series inductor in the input port and a switching function representing the error between the input power and a suitable power reference. The analysis establishes the existence conditions for sliding-mode and the stability of the resulting ideal dynamics. Simulation and experimental results verifying the theoretical predictions in boost, Ćuk and SEPIC converters illustrate the proposal. The design procedure yields a simple, economical and small-size prototype that can be useful in the experimental validation of converters supplying constant power loads. [ABSTRACT FROM AUTHOR]

This paper presents a nonlinear analytical model for an inverter-based switched-capacitor Class-D RF power amplifier (SCDPA). The root causes of the SCDPA AMAM and AMPM nonlinearities are studied. The major factors affecting SCDPA nonlinearities are identified as the unequal on-resistances of selected cell and unselected cell. Specifically, time-varying resistance of the switch, different transistor responses during the transition and parasitic resistance on the supply path (IR drop) are analyzed. Then, the system-level result, like EVM and power spectral density, can be obtained with nonlinear behavior of PA. The results of model calculation, schematic simulation, and measurement are presented and compared with validate the model both on transistor level and system level. This paper, for the first time, provides an accurate design guidance to enable fast architecture study and quick circuit-level prototype with close-to-optimum component initial parameters. It can be expanded to more architectures, therefore helps to pave the path to future design automation for highly linear SCDPAs. [ABSTRACT FROM AUTHOR]

In this paper, a class of discrete-time singularly perturbed switched systems $\left ({\text {SPSSs}}\right) $ with persistent dwell-time $\left ({\text {PDT}}\right)$ switching law is firstly proposed. Using the slow-state feedback control method, sufficient conditions to ensure the global uniform exponential stability of the closed-loop PDT SPSSs are derived. Based on the aforementioned conditions, the analyses of the extended dissipative performance of the closed-loop PDT SPSSs and a preferable decoupling method deriving the mode-dependent controller gains are given for the first time. Finally, the potential practicability of the method is verified by a purely numerical example and a tunnel diode circuit model, and a convex optimization method calculating the upper bound of the singular perturbation parameter is provided. [ABSTRACT FROM AUTHOR]

Critical conduction mode (CrCM) active clamp flyback (ACF) converter is regarded as a good candidate for low power adaptor applications. However, the most adopted control strategy of variable-frequency peak current mode (VF-PCM) and discrete zero voltage switch (ZVS) control makes it difficult to get the accurate small signal model. Therefore, by using sampled-data modeling method, this paper proposes an exact small signal model of CrCM ACF converter for the first time. In the modeling process, the influence of discrete-ZVS control is firstly considered. The conduction time of power switch is regarded as the control signal, which is different from constant-frequency converter. The total current close-loop transfer function is simplified by the linear combination of single VF-PCM and discrete-ZVS control model. After considering the sampling effect and the modulator gain from the derived sampled-data model respectively, the control-to-output transfer function of CrCM ACF converter is developed. The analytical results are analyzed by comparing with single VF-PCM and the widely used average model. Finally, to validate the accuracy of the proposed model, a 65W 20V output CrCM ACF converter is simulated and measured. The verification shown that the proposed sampled-data model is basically agreement with the simulation and experimental results. [ABSTRACT FROM AUTHOR]

This paper studies stability of stochastic impulsive switched systems. Different from exponential Lyapunov function and average dwell-time in the previous works, general Lyapunov function and fixed dwell-time are implemented in this paper to analyze input-to-state stability and global stability of stochastic impulsive switched systems. Two cases are investigated, that is, the case that the continuous dynamics is stable and the case that the discrete dynamics is stable. To implement multiple Lyapunov functions, there are two subcases considered in this paper: the subcase that the estimates on the derivatives of the multiple Lyapunov functions are the same and the subcase that the growths of the multiple Lyapunov functions by the jumps are the same. For aforementioned different cases, sufficient stability conditions are established for stochastic impulsive switched systems. Finally, the developed theory is illustrated through examples from networked control systems and synchronization problem of 3-D novel chaotic circuit systems. [ABSTRACT FROM PUBLISHER]

The main focus of this paper is the evolution of complex behavior in a system of coupled nonlinear memristor circuits depending on the applied coupling conditions. Thereby, the parameter space for the local activity and the edge-of-chaos domain will be determined to enable the emergence of the pattern formation in locally coupled cells according to Chua’s principle. Each cell includes a Niobium oxide-based memristor, which may feature a locally active behavior once it is suitably biased on the negative differential resistance region of its DC current-voltage characteristic. It will be shown that there exists a domain of parameters under which each uncoupled cell may become locally active around a stable bias state. More specifically, under these conditions, the coupled cells are on the edge-of-chaos, and can support the static and dynamic pattern formation. The emergence of such complex spatio-temporal behavior in homogeneous structures is a prerequisite for information processing. The theoretical results are confirmed by measurements as well as by the numerical simulations of the accurate device and circuit models. [ABSTRACT FROM AUTHOR]

With downscaling of process technology, conventional memories encounter challenges, such as soaring static power, low reliability, and charge sharing effect induced by radiation effects. Magnetic random access memory (MRAM) is considered as an outstanding candidate for addressing these challenges. In particular, emerging spin–orbit torque (SOT) MRAMs have shown ultra-fast switching and read-disturbance immunity compared with spin-transfer torque MRAMs. However, the write operation of the SOT-MRAM is more vulnerable to single-event upsets (SEUs) as its ultra-short write pulse is comparable to the radiation current pulse. In addition, its read circuit can also be disturbed by SEUs or even double-node upsets (DNUs) induced by the charge sharing effect. In this paper, we investigate radiation effects on read/write circuits of the SOT-MRAM. Then, we propose novel radiation hardening designs for SOT-MRAM. The hardening technique is first studied at the write circuit by adding six PMOS transistors as a feedback structure to charge/discharge. Afterwards, we propose a radiation hardening read circuit addressing the issue of SEUs and DNUs, which uses redundant six transistors and two feedback connections as the hardening structure. Based on a physics-based SOT magnetic tunnel junction model and a 65-nm complementary metal–oxide–semiconductor design kit, simulation results indicate that radiation-induced soft errors can be corrected at sensitive nodes. Moreover, the error rate of the proposed read circuit is $40\times $ smaller than the previous work, and restoring time is reduced by 30.6% with negligible area overhead. [ABSTRACT FROM AUTHOR]

The technology for oxide resistive memories offers nowadays a number of different implementations and solutions. As a consequence, many models have been presented so far, generally technology-specific, representing a problem for the memory design standardization. Moreover, the computational effort can be reduced using memristive models with lower complexity but that grant at the same time good speed and numerical stability. In this paper, the authors try to find a compromise between accuracy and computational costs, proposing a simulation procedure based on a linear approximation of the memristive device model. The description, formally derived from the traditional linear model, has been implemented in Verilog-A and, thanks to the analysis of practical design cases on a reference architecture, has been demonstrated to be useful in highlighting critical parasitic effects related to the interaction of the memristive cells with the memory circuit periphery. Thanks to the approximated method, a computer simulation time saving up to 40% is achieved when simulating a full cross-bar memory device. The model parameters have been extracted from experimental curves obtained from HfO2 devices implemented in a 250-nm BiCMOS IHP technology. [ABSTRACT FROM AUTHOR]

The high-speed successive-approximation-register (SAR) analog-to-digital converters (ADCs) rely on the switched capacitive digital-to-analog converter (CDAC) to perform the fast transition, which causes voltage ripples at the output of the reference circuits. Such ripples lead to the reference error that eventually prolongs the time for DAC settling. To minimize such error with a short available time, it either demands a power-hungry reference buffer or large die area for the decoupling. In this paper, we offer a comprehensive analysis of the reference errors in SAR ADCs with a practical reference network circuit (RNC) in consideration. A circuit model is developed in order to quantify the error amplitude for the critical DAC settling condition. Based on the proposed model, the settling behavior of the DAC with reference buffer can be precisely characterized, leading to a better understanding about the design tradeoff of the RNC. Finally, the developed model is verified by both circuit level simulations and measurement results. [ABSTRACT FROM AUTHOR]

Chopping is a technique to reduce offset and flicker noise in amplifiers by up-converting them to higher frequency, and subsequently filtering them out. A typical chopping implementation uses two complementary phases which have a finite non-overlap time in between them. When such a chopping phase is used in the first integrator of a continuous-time delta sigma modulator, the non-overlap time can significantly degrade two key parameters of the modulator’s performance—in-band noise and its inherent anti-aliasing. In this paper, we develop a model to include the effects of non-overlap duration on the modulator’s performance. Then this model is used to derive analytical expressions for in-band noise and anti-aliasing for a given non-overlap duration. The results obtained are verified using simulation. [ABSTRACT FROM AUTHOR]

We reconsider the black box model by Urbanek of electric-arc in air-blast circuit breakers or in circuit breakers characterized by an electro-negative gas (e.g., SF6) as quenching medium. It has the unique characteristic to account for the dielectric breakdown that possibly reignites the arc. We show some of its main features that have been almost hidden from the first publication of the model in the literature. The conductance in the Urbanek model plays two roles: 1) it effectively represents the conductance of the burning arc when positive and 2) it is a thermodynamic indicator when negative. This thermodynamic indicator is used to eventually trigger a restrike of the arc. We show that this switching behavior can be formally analyzed by considering the model as an hybrid dynamical system. In this paper, we reconsider it and show its main dynamic properties through some case studies. [ABSTRACT FROM PUBLISHER]

In this paper, a variation-aware simulation framework for hybrid circuits comprising MOS transistors and magnetic tunnel junction (MTJ) devices is presented. The framework is based on one-time characterization via micromagnetic multi-domain simulations, overcoming the inaccuracies introduced by single-domain analysis, which most of the existing frameworks are based on. As further distinctive capability, non-Gaussian stochastic variations of the MTJ write switching time are explicitly modeled through a Skew Normal distribution, making the model suitable for low-power and low-voltage designs. The framework involves the use of a Verilog-A look-up table-based model, which assures easy integration with commercial design tools. Our strategy is evaluated on a spin-transfer torque-magnetoresistive random access memory (MRAM) working in RAM and true random number generator (TRNG) modes. In RAM mode, while the commonly-used approach based on Gaussian-distributed switching statistics tends to underestimate the pulse width required for a write error rate of 10^-6 by about 20%, our Skew Normal-based strategy allows tracking reference micromagnetic results with an average error less than 4%. In TRNG mode, our approach also allows a better tracking of the reference 50%-switching probability contour with an error less than 1%abs. However, the incorporation of the Skew Normal distribution in our Verilog-A model results in an increase of the CPU time by 50% on average as compared with the use of the built-in statistical functions. [ABSTRACT FROM AUTHOR]

An efficient self-powered synchronous electric charge extraction CMOS interface circuit dedicated to piezoelectric harvesters is proposed in this paper. Self-powered peak detection (PKD) and switch circuits are used to reduce quiescent current so that the backup or pre-charged power can be saved. A new low phase lag (LPL) PKD circuit is designed to improve the synchronous extraction efficiency, which only requires one detection capacitor to perform positive and negative PKD. The circuit can be set at general mode (G-mode) or LPL mode (LPL-mode). Under LPL-mode, the phase lag can be reduced typically by 50%, the synchronous extraction efficiency can obtained up to 94%, while the output power can reach 659~\mu \textW when the piezoelectric transducer original open-circuit voltage V\mathrm{ oc,org}=5 V, which is 3.56 times of that of full-bridge rectifier standard energy harvesting circuit at the maximum power point. The minimum harvesting startup voltage is 1.7 V and is independent of the energy storage capacitor voltage V\mathrm{ DC} . The harvesting efficiency can still reach 71.3% at V\mathrm{ oc,org}=5 V. The size of the active area is 0.5 mm2 in a 0.18- \mu \textm CMOS technology. Circuit may be invoked as a functional block for energy autonomous wireless sensor network node of the Internet of Things. [ABSTRACT FROM PUBLISHER]

Memory-centric computing with on-chip non-volatile memories provides unique opportunities for native and local information processing in an energy-efficient manner. Design and modeling methodology based on resistive random access memory (RRAM) is presented in this paper. A hierarchical RRAM SPICE model having different levels of physics realism is described, where the incorporated stochasticity provides a more accurate representation of RRAM operations. Three in-memory operation schemes are developed and experimentally verified for reconfigurable in-memory logic, using RRAM built in 3-D vertical structure (i.e., 3-D RRAM). As a case study for RRAM-centric computing systems, we evaluate the Please note that there were discrepancies between the accepted pdf [TCAS_R1_combined.pdf] and the [TCAS_RRAM-centric computing_hli_FINAL_submit.docx] in the lines 12 and 70. We have followed [TCAS_RRAM-centric computing_hli_FINAL_submit.docx]. use of 3-D RRAMs for a language recognition system using the hyperdimensional (HD) computing model. Utilizing the inherent properties of 3-D RRAM, we demonstrate, using fabricated 3-D RRAM integrated with FinFET, the essential kernels for HD operations: multiplication, addition, and permutation (MAP). RRAM-centric HD systems exhibit strong resilience to hard errors induced by RRAM endurance failures, making a promising case for using various types of RRAM for memory-centric HD systems. [ABSTRACT FROM PUBLISHER]

This paper presents a nonlinear state-space model (SSM) for a low power 28-nm complementary metal–oxide–semiconductor switched-capacitor digital-to-analog converter. The proposed model utilizes current–voltage (I-V) input and output relationships for passive devices, which are described by a set of first-order differential equations. The proposed model significantly increases accuracy when compared with the state-of-the-art models. The SSM simulation results have been verified using SpectreRF transistor-level simulations and validated by on-chip measurements. [ABSTRACT FROM AUTHOR]

A constant on time variable frequency one-cycle control technique (CVFOCC) for switched-capacitor (SC) converters is presented in this paper. It is designed to accomplish the continuous variable conversion ratio and fast dynamical response to reject the external disturbance. A proper regulation can be obtained by controlling the related “off time” of a transistor with the constant “on time” which is less than the time constant $\tau $ of the charge loop. A unique large-signal dynamic capacitor ampere-second balance (CASB) model for SC converters is applied in this research study. It is implemented to instantaneously estimate transient values of the equivalent circuits. The proposed modeling method and analysis have been verified by comparing the modeling expressions with simulation and experiment results for different input voltages, load currents and switching frequencies. The simulation and experiment results show that the external disturbance of a single-stage SC converter could be immediately rejected by the proposed control method. The good line and load regulation are demonstrated. The proposed control method is stable and global. It can work in a wide operation range with a simple control circuit for general SC converters. [ABSTRACT FROM AUTHOR]

This paper presents an efficient numerical methodology to obtain the frequency response of switched-capacitor filters based on the circuits' differential equations. This methodology uses a non-hierarchical approach in which the non-ideal effects of the transistors (in the switches and in the amplifier) are taken into consideration, allowing the accurate computation of the frequency response, even in the case of incomplete settling in the SC branches. The accuracy is demonstrated by comparing the results obtained using the proposed methodology with those obtained using transient electrical simulation results for three different SC circuits: a first order SC passive filter, a second order SC lowpass filter, and a second order SC bandpass filter, showing that the results are in good agreement with the more time consuming electrical simulation of the circuits. [ABSTRACT FROM PUBLISHER]

Switching currents of simultaneous switching output (SSO) buffers can cause significant power-supply-induced jitter (PSIJ) and uncertainty in the output voltages. The bit error rate (BER) can be simulated by considering all possible input data patterns with a long data sequence; however, it requires large computational efforts. In this paper, the SSO waveforms are analytically calculated, including the rise time of the input voltage, and the probability density functions (PDFs) of the waveforms are analytically calculated. The PDFs of the SSO step responses are combined with the inter-symbol interference (ISI) PDF extraction. The statistical eye and BER eye diagrams obtained from the proposed method are validated with HSPICE simulations. The effects of the SSO patterns as well as the channel ISI are successfully included in the proposed method. Also, the effects of input rise time and the number of parallel SSO buffers are investigated, and the proposed method is extended for analysis of SSO buffers with the data bus inversion (DBI) coding. The method should be practically useful for design of wideband memory I/O interfaces and low-cost consumer devices by reducing the computational time of the jitter and BER drastically. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a design of traditional sequential circuits using high performance Ballistic Deflection Transistor (BDT). BDT technology was developed and experimentally proven to operate at Terahertz frequencies. Different structures of BDTs have been developed successfully to realize combinational logic functionality. Monte Carlo (MC) simulations have been extensively used to study these structures. By taking into account the effect of surface charges and dielectrics, we are able to correctly reproduce the non-linear I-V transfer characteristics, to predict scaling down behavior and to estimate the very high switching speed. We then used a three parameter Gaussian peak as a predictive model for the BDT and integrated it with Verilog AMS module to confirm the functionality of the designed circuits. Finally, we used a recently developed level-sensitive D-latch using two-BDTs structure, to explore traditional sequential circuits such as Shift Registers (SRs), Frequency Divider and Johnson Ring Counter, which play a pivotal role in many processing systems as common datapath operators. The simulation results have indicated the correct logic functionality of the implemented sequential circuits. [ABSTRACT FROM PUBLISHER]

This paper presents a physics-based mathematical model for anionic memristor devices. The model utilizes Poisson- Boltzmann equation to account for temperature effect on device potential at equilibrium and comprehends material effect on device behaviors. A detailed MATLAB based algorithm is developed to clarify and simplify the simulation environment. Moreover, the provided model is used to simulate and predict the effect of oxide thickness, material type, and operating temperatures on the electrical characteristics of the device. The parameters of the proposed model are tuned and validated using experimental data of a fabricated wire based NbO1–x junction. This device is attractive for neuromorphic and computing applications, where multilevel state is desirable. The value of this contribution is to provide a framework intended to simulate anionic memristor devices using correlated mathematical models. In addition, the model can be used to explore device materials and predict its performance. [ABSTRACT FROM PUBLISHER]

In this paper the stability and sensitivity function of three basic dc-dc converter with the consideration of circuit parasitics has been analyzed for analog and digital controller implementation. The steady state and small-signal analysis has been used to derive the mathematical expressions for uniformly sampled voltage-mode controlled converters. The effect of digital controller using the ratio of sampling to carrier frequency has been analyzed. The sampling frequency limits the voltage gain in the stepped manner and also affects the stability of the digitally controlled converter. The sensitivity function has been defined for voltage gain with respect to various system parameters. The maximum affected regions on duty ratio scale with corresponding parasitic variable have been discussed. The detailed stability analysis has been carried out for digitally implemented three basic dc-dc converters, i.e., buck, boost, and buck-boost circuits. The analytical results are verified with the simulations performed in PSCAD/EMTDC. An FPGA controller is considered as digital controller for the dc-dc converter and verification of the results through experiment. [ABSTRACT FROM PUBLISHER]

In Part I of this paper, we introduce useful analysis that leads to a simple signal flow graph (SFG), which captures the FET-R-C circuit's action completely across a wide range of design parameters. Part I focuses on the analysis of a single-path FET-R-C circuit's signal transfer characteristics and gives us guidelines for sample-and-hold (S/H) and passive sampling mixer (P-M) designs. Part II extends the analysis to multi-path FET-R-C circuit configurations, e.g., a complex $I$-$Q$ passive mixer that is common in RF applications. Then the noise and driving-point impedance analyses are carried out to provide valuable insights of practical S/H and P-M designs. [ABSTRACT FROM AUTHOR]

Designing a SPICE model is a critical step toward understanding the behavior of the resistive random access memory (RRAM) devices when integrated in memory design for the future generation storage devices. In this paper, a SPICE model is developed for the \textrmTa2\textrm{O}5/\textrm{TaO}x bi-layered RRAM. The proposed model emphasizes the impact of the change in the switching layer thickness on the device behavior at low resistance state (LRS), high resistance state (HRS), and the transitional period. The validity of the proposed model is verified through using three different sets of experimental data from \textrmPt/Ta2\textrm{O}5/\textrm{TaO}x/\textrm{Pt} RRAM with switching layer thickness smaller than 5 nm. The SPICE model reproduced all the major features from the experimental results for the SET and RESET processes and also the asymmetric and the symmetric characteristics in HRS and LRS, respectively. The proposed SPICE model matches the measured experimental results with an average error of < 11% and a maximum error of < 70%. It also showed stable behavior for its HRS and LRS regions under different types of input signals. The model is parameterized in order to fit into \textrmTa2\textrm{O}5/\textrm{TaO}x RRAM devices with switching layer thickness smaller than 5 nm, thus, facilitating the model usage. The model can be included in the SPICE-compatible circuit simulation and is suitable for the exploration of the \textrmTa2\textrm{O}5/\textrm{TaO}x bi-layered RRAM device performance at circuit level. [ABSTRACT FROM AUTHOR]

This paper presents a systematic analysis of integrated 3-level buck converters under both ideal and real conditions as a guidance for designing robust and fast 3-level buck converters. Under ideal conditions, the voltage conversion ratio, the output voltage ripple and, in particular, the system's loop-gain function are derived. Design considerations for real circuitry implementations of an integrated 3-level converter, such as the implementation of the flying capacitor, the impacts of the parasitic capacitors of the flying capacitor and the 4 power switches, and the time mismatch between the 2 duty-cycle signals are thoroughly discussed. Under these conditions, the voltage conversion ratio, the voltage across the flying capacitor and the power efficiency are analyzed and verified with Cadence simulation results. The loop-gain function of an integrated 3-level buck converter with parasitic capacitors and time mismatch is derived with the state-space averaging method. The derived loop-gain functions are verified with time-domain small signal injection simulation and measurement, with a good match between the analytical and experimental results. [ABSTRACT FROM AUTHOR]

A systematic design approach using signal flow graph (SFG) is presented in this paper, tailored for integrated reconfigurable switched-capacitor (SC) power converters. To achieve an optimal power stage, an unified signal flow graph (USFG) model is developed. System transfer function and I/O impedance can be evaluated based on it. To verify the design approach, the paper demonstrates a step-up/down reconfigurable SC power converter with five optional gain ratios. A dual-loop control scheme is employed to reconfigure the converter according to the instantaneous line/load conditions. A low-power, digital controller is designed in the subthreshold region for the feedback control loop. The converter was fabricated with a 130-nm CMOS process. Experimental results show that its output can be continuously regulated from 0.4 to 2.2 V, while allowing the input voltage to randomly vary between 0.9 and 1.5 V. The line regulation is maintained below 1.4%, with a lowest value of 0.07%. The maximum efficiency of 90.22% is measured at 0.55-V output voltage and 20-mW load. [ABSTRACT FROM PUBLISHER]

Motivated by different applications in circuits, electromagnetics, and optics, this paper is concerned with the synthesis of a particular type of linear circuit, where the circuit is associated with a control unit. The objective is to design a controller for this control unit such that certain specifications on the parameters of the circuit are satisfied. It is shown that designing a control unit in the form of a switching network is an NP-complete problem that can be formulated as a rank-minimization problem. It is then proven that the underlying design problem can be cast as a semidefinite optimization if a passive network is designed instead of a switching network. Since the implementation of a passive network may need too many components, the design of a decoupled (sparse) passive network is subsequently studied. This paper introduces a tradeoff between design simplicity and implementation complexity for an important class of linear circuits. The superiority of the developed techniques is demonstrated by different simulations. In particular, for the first time in the literature, a wavelength-size passive antenna is designed, which has an excellent beamforming capability and which can concurrently make a null in at least eight directions. [ABSTRACT FROM PUBLISHER]

We present a compact, continuous, and numerically stable version of a tantalum oxide (TaOx) memristor model which can be employed for robust and reliable simulations of large scale memristor based circuits. The original model contains a piecewise differentiable function in the memductance expression and discontinuous step functions in the state equation. Additionally, the original model does not set a proper upper bound for the state variable and may admit blowing up solutions due to an exponential power term, preventing the use of it for numerically reliable simulations. Considering these drawbacks, we modify the original model so as to i) simplify the memductance function while removing its piecewise differentiable nonlinearity, ii) include a proper window function for the ON state dynamics, which is missing in the original model, iii) modify and bound the exponential power term to prevent an uncontrollable blow-up of the solutions, and iv) apply a process called unification, allowing us to remove the step functions inherent in the model, which is a novelty in state-limited memristor models. We validate the accuracy of the proposed model via DC and transient simulations, dynamic route map analysis and a Spice implementation of an anti-series configuration, showing the applicability of the model. [ABSTRACT FROM AUTHOR]

This paper proposes a new timing storage circuit based on memristors. Its ability to store and reproduce timing information in an analog manner without performing quantization can be useful for a wide range of applications. For continuous-time (CT) digital filters, the power and area costly analog delay blocks, which are usually implemented as inverter chains or their variants, can be replaced by the proposed timing storage circuits to delay CT digital signals in a more efficient way, especially for low-frequency biomedical applications that require very long tap delays. In addition, the same timing storage circuits also enable the storage of CT digital signals, extending the benefits of CT digital signal processing (DSP) to applications that require signal storage. As an example, a 15-tap CT finite impulse response (FIR) Savitzky-Golay (S-G) filter was designed with memristor-based delay blocks to smoothen electrocardiographic (ECG) signals accompanied with high-frequency noise. The simulated power consumption under a 3.3-volt supply was 6.63 \muw. [ABSTRACT FROM AUTHOR]

Traps that are located in the gate oxide of MOSFETs have been established as a cause of low-frequency noise phenomena. Analysis of such noise is usually based on frequency domain, stationary models. It has been shown that such simplistic models produce erroneous results for circuits with time-varying bias conditions. Tian proposed an idealized trap model with the goal of capturing the nonstationary behavior of oxide traps, and were able to elucidate the experimentally observed large noise power reduction in switched MOSFET circuits which eluded any explanation obtainable with legacy stationary models. In this paper, we build on their seminal work and first identify an oversight in their model derivation which had produced an incorrect expression for the single trap noise spectrum. We next derive the correct spectrum expression, verify it against detailed idealized trap simulations and discuss its implications. The idealized trap model is amenable to analytical derivations and useful as a first stage in understanding nonstationary trap noise. We then demonstrate that noise simulations based on a detailed trap description implemented in a compact MOSFET model in a circuit simulator are needed for an accurate characterization of low-frequency noise in switched MOSFET circuits that matches experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a time domain generalized semi-analytical solution for the class-E outphasing power amplifier (OPA). Instead of assuming ideal voltage sources for active devices, the proposed class-E OPA model obtains the circuit elements by analytically solving the class-E equations for two mutually loaded active devices and numerical optimization. The analysis takes into account the dc-feed inductor, duty-cycle, switch resistances and the class-E conditions at certain outphasing angle. Three different topologies are deduced from the proposed generalized model. The design equations for the circuit elements are derived analytically using the given class-E conditions. The overall outphasing performance is obtained numerically, and the optimum design settings are determined by the desired output power and efficiency characteristics. It will be shown that the proposed class-E OPAs can ideally maintain high efficiency (>80%) at 12-dB power back-off with a static square-wave drive signal. With 5-MHz UMTS downlink signal, the ideal average efficiency is more than 80%. The spectral and modulation requirements are satisfied when the predistortion is applied to the class-E OPA. [ABSTRACT FROM AUTHOR]

Accurate modeling of magnetic tunnel junction (MTJ) is critical for design of memories such as spin-transfer-torque magnetoresistive random access memory (STT-MRAM) and spin logic circuits such as spin flip flops. This paper reviews several static and dynamic models for the MTJ and compares them for their capabilities and limitations. Furthermore, a Verilog-A model is developed to predict dynamic characteristics of the MTJ. These models are used in simulating a prototype circuit to illustrate their strengths and weaknesses. [ABSTRACT FROM AUTHOR]

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design. [ABSTRACT FROM AUTHOR]

Dynamic average-value models (AVMs) for AC-DC rectifier circuits are generally formulated in state-space form and hence are straightforward to implement in state-variable-based simulation languages. In the nodal analysis-based approach used in electromagnetic transient (EMTP-type) simulation packages, the development of AVMs requires additional effort to reformulate and interface the models with the external ac and dc networks. This paper proposes a new averaged-circuit model for three-phase line-commutated rectifiers which is directly interfaced with the ac and dc networks, thereby achieving a simultaneous solution of the respective variables in EMTP-type solution. The proposed model is verified against conventionally interfaced model, as well as detailed switching model of the original rectifier circuit. A significant improvement of numerical accuracy and stability of the solution is demonstrated even at fairly large time steps. [ABSTRACT FROM AUTHOR]

This paper presents a systematic classification of auxiliary circuit schemes for feeding fast load transients in switching power converters. The classification is based on the types of the implementation methods, practical constraints and performance. In particular, auxiliary circuits are classified according to the ways in which they are connected with the power supplies and loads, as well as the choice of control methods. Designed as a shunt output, the “intruding” type of auxiliary circuits is effective and less dissipative. Moreover, to reduce complexity, auxiliary circuits may be designed in the form of a bridge output, and employs a “non-intruding” type of control scheme. Furthermore, provision of pre-informed loading condition leads to further simplification of auxiliary circuitry and improvement of efficiency. Experimental measurements are provided to support the analysis of the properties of various types of circuits. [ABSTRACT FROM PUBLISHER]

Emerging non-volatile memories (NVM) based on resistive switching mechanism (RS) such as STT-MRAM, OxRRAM and CBRAM etc., are under intense R&D investigation by both academics and industries. They provide high write/read speed, low power and good endurance (e.g., >10^12) beyond mainstream NVMs, which allow them to be embedded directly with logic units for computing purpose. This integration could increase significantly the power/die area efficiency, and then overcome definitively the power/speed bottlenecks of modern VLSIs. This paper presents firstly a theoretical investigation of synchronous NV logic gates based on RS memories (RS-NVL). Special design techniques and strategies are proposed to optimize the structure according to different resistive characteristics of NVMs. To validate this study, we simulated a non-volatile full-adder (NVFA) with two types of NVMs: STT-MRAM and OxRRAM by using CMOS 40 nm design kit and compact models, which includes related physics and experimental parameters. They show interesting power, speed and area gain compared with synchronized CMOS FA while keeping good reliability. [ABSTRACT FROM AUTHOR]

This paper develops and experimentally demonstrates a new class of high-fidelity model-based fault detection and isolation filters for three-phase AC-DC power electronics systems. The structure of these filters is similar to that of a piecewise linear observer and in the absence of faults the filter residual converges to zero. On the other hand, whenever a fault occurs, by appropriately choosing the filter gain, the filter residual will exhibit certain geometric characteristics that allow the fault to be detected and, in certain cases, also isolated. Key advantages of these filters include fast detection of all possible component faults and the ability to capture slow degradation in individual components. In order to experimentally demonstrate their feasibility, the filters are implemented on an ultra-fast application-specific real-time processor. While the theoretical framework developed is general, the analysis, simulations, and experiments are focused on widely used power electronics systems implementing three-phase AC-DC converters that are used in, e.g., motor drive applications and distributed static compensators. [ABSTRACT FROM PUBLISHER]

Highly detailed models of power-electronic converter circuits can be slow to simulate due to the wide disparity in transient time scales. This paper presents a framework for multi-resolution simulation of switching converter circuits by providing an appropriate amount of detail based on the time scale and phenomenon being considered. In this approach, a detailed full-order model that accounts for the higher-order effects of components, parasitics, switching nonlinearity (e.g., saturated inductors), switching event detection, etc., is constructed first. Efficient order-reduction techniques are then used to extract several lower order models for the desired resolution of the simulation. The simulation resolution can be adjusted as needed even during a simulation run time. The state continuity across different resolutions and switching events is ensured using appropriate similarity transforms. The proposed high-fidelity model of converter is verified with hardware measurement and is used to verify different simulation resolutions. The proposed methodology is demonstrated to achieve orders of magnitudes improvement in simulation speed. [ABSTRACT FROM AUTHOR]

The harmonic signal rejection capability and the rejection schemes of polyphase downconverters are discussed. An analysis of a simple model of a polyphase downconverter shows that n-phase converter can reject up to (n-2)th harmonic signal, and that (n-1)th harmonic signal aliases into the desired signal. It means that the harmonic rejection is not exclusive ability of downconverters with large number of phases, and conventional downconverters with fewer phases have the ability. An example is a differential amplifier type downconverter (n=2), which has the ability of even harmonic signal rejection as common-mode signal. In this paper, the common-mode concept is extended to polyphase circuits. It is named “partial common mode,” because it does not have to be common for all node but is common for a part of nodes. The partial common-mode rejection is effective for harmonic rejection. There is the other type of harmonic rejection techniques for polyphase downconverters, i.e., signal weighting-and-summing type. Comparison between the harmonic rejection with weighting-and-summing circuit and that with the common-mode rejection circuit is discussed, too. Due to its simple structure, a 6-phase downconverter with partial common-mode rejection is attractive for practical wideband receivers. [ABSTRACT FROM PUBLISHER]

This paper proposes a new iteration-free steady-state analysis to the Class-E power amplifier (PA) in frequency-domain by extending the scope of electrical impedance. Owning to this extension, the impedances of different circuit components in the Class-E PA circuits, including the active switches, can be expressed in matrix form. Based on the conventional circuit laws, e.g., the series and parallel laws and the Ohm's law, the steady-state characteristics of a whole Class-E PA circuit can be obtained by vector and matrix manipulation. The number of harmonics involved in the calculation have effects on the computational efficiency and accuracy. The influences of some circuit conditions towards the selection of harmonic number are discussed. The proposed formulation enables fast mapping of some performance indices, e.g., the output power and conversion efficiency, under steady state, so that the changing trends of these indices with respect to the variations of specified circuit parameters can be estimated. This feature can be utilized to carry out offline optimization by tuning some passive components, or online optimization by tuning two in situ adjustable parameters, i.e., the switch driving frequency and duty cycle. The later scheme provides preliminary knowledge on the in situ tuning of Class-E PA in the load varying applications, e.g., electric process heating and wireless power link. [ABSTRACT FROM PUBLISHER]

Computation of periodic steady state in nonlinear circuits is a key issue. Power electronics converters represent an interesting class of switched nonlinear circuits. The behavior of the converter is obtained by the commutations of the electronic devices which determine the switchings among the different converter modes. Switchings can be classified as external, if forced by directly manipulable control variables, and internal if determined by state dependent conditions. The presence of internal switchings makes it difficult to know a priori the sequence of modes and also open loop steady-state behaviors are difficult to be obtained. In this paper the complementarity modeling framework is proposed as a possible approach for computing periodic steady-state oscillations in power converters with internal switchings. It is shown how linear complementarity systems can be used to model the behavior of a wide class of power converters. The discretization of such model allows to formulate a static complementarity problem whose solution provides the steady-state oscillation of the converter. It is proved that the backward zero-order-hold technique preserves passivity through the discretization and allows to determine the unique solution of the complementarity problem. A resonant converter and a dc/dc voltage-mode controlled buck converter are used as examples. [ABSTRACT FROM PUBLISHER]

This paper proposes a small-signal model for variable-switching-frequency hysteretic converters operating in continuous conduction mode (CCM) and discontinuous conduction mode (DCM). The model is capable of predicting flip-bifurcation phenomena when the hysteretic converter operates below the CCM/DCM boundary. By developing a discrete-time state-space model of the converter, the z-domain model is derived using the advanced z-transform. Such a tool is suitable to transform in the z-domain signals varying within a switching cycle. A comparison with exact simulations is provided to validate the proposed model. The propagation delay of the feedback control circuit is included due to its significant influence on the low-frequency open-loop gain. Experimental results run on a test chip including a 10-MHz TSMC 0.18\ \mu\m-process hysteretic-mode buck converter are also reported along with the model results. [ABSTRACT FROM PUBLISHER]