Search

A 10-Gb/s serial link transceiver is demonstrated using double-edged pulsewidth modulation to overcome frequency-dependent losses in electrical interconnects. Time domain modulation is discussed as a means to enhance the spectral efficiency in channels with sharp frequency roll-off similar to multilevel voltage-domain modulation such as 4-PAM. The transmitter and receiver are high-speed programmable digital-to-time and time-to-digital converters that adapt to channel bandwidth characteristics with a timing resolution of 40 ps. This paper presents a low-jitter, phase rotation architecture for cycle-to-cycle transmit pulsewidth control. The transceiver includes an elastic buffer to move data between synchronous and plesiochronous clock domains and is implemented in 45-nm CMOS SOI. Transmitter and receiver functionality is demonstrated to 10 Gb/s at a BER of under 10^-12 and is compared against NRZ schemes at the same rate. The inductor-less transmitter and receiver active circuitry respectively occupy an area of 93\,\times\,94 and 218\,\times\,160 \mum^2, and consume a total 107 mW from a 1.2 V supply. [ABSTRACT FROM PUBLISHER]

This paper presents a four channel receiver for high-speed signal conditioning. Each channel consists of a continuous time linear equalizer (CTLE) and a dual loop CDR with phase-interpolator. All channels share a single PLL that generates and distributes quadrature clock phases to each CDR for data recovery. Clock amplitude, phase INL and phase DNL are derived for IQ phase error and predict phase-dependent jitter contributions to the recovered clock. The multilane receiver was designed in 130-nm CMOS technology. The die occupies an area of 1930 \mu m by 1250 \mu m and consumes 67.9 mW per channel. It achieves a maximum data rate of 7 Gbps per channel for 0 and \pm 200~ppm clock frequency deviation. [ABSTRACT FROM PUBLISHER]

An integrate-and-dump receiver based on an active feedback integrator is demonstrated in a 45-nm SOI CMOS process. The integrate-and-dump receiver provides matched filtering for non-return-to-zero, return-to-zero, and pulse amplitude modulation digital modulation formats, resulting in high SINAD as well as inherent anti-aliasing/low-pass filtering for a 2 GS/s high linearity/high-dynamic-range optical sampling receiver. The measured SINAD is greater than 28 dBc with a sinusoidal input up to 1 GHz; the SNR is greater than 29 dBc. The 2-GS/s integrate-and-dump receiver consumes less than 100 mW. The chip area is 0.980x0.762 mm^2 including the pads. [ABSTRACT FROM AUTHOR]

A 40-Gb/s transimpedance amplifier (TIA) is proposed using multistage inductive-series peaking for low group-delay variation. A transimpedance limit for multistage TIAs is derived, and a bandwidth-enhancement technique using inductive-series \pi-networks is analyzed. A design method for low group delay constrained to 3-dB bandwidth enhancement is suggested. The TIA is implemented in a 0.13-\mu\ m CMOS process and achieves a 3-dB bandwidth of 29 GHz. The transimpedance gain is 50 \ dB\cdot\Omega, and the transimpedance group-delay variation is less than 16 ps over the 3-dB bandwidth. The chip occupies an area of 0.4 \ mm^2, including the pads, and consumes 45.7 mW from a 1.5-V supply. The measured TIA demonstrates a transimpedance figure of merit of 200.7 \Omega/\pJ. [ABSTRACT FROM PUBLISHER]