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Functional test sequences can detect defects that are not detected by scan-based tests, but overall, achieve a lower gate-level fault coverage than scan-based tests. Design-for-testability (DFT) approaches for functional test sequences cause the sequences to deviate from functional operation conditions in arbitrary ways over the entire design. This paper introduces the concept of invisible-DFT as a DFT approach for functional test sequences, where the effects of activating the DFT logic are confined to selected logic blocks. This paper develops an invisible-scan approach. Considering a single logic block, the procedure described in this paper inserts scan shift cycles into a functional test sequence while maintaining the same primary input and output sequences for the logic block. This makes the activation of the DFT logic invisible to other logic blocks. The procedure allows a limited number of primary output vectors to be corrected for this purpose. Experimental results are presented to demonstrate the increase in fault coverage that can be achieved by invisible-scan. [ABSTRACT FROM AUTHOR]

This paper describes a test compaction procedure that combines the advantages of using multicycle tests for test compaction with the advantages of using both broadside and skewed-load tests for increasing the fault coverage and achieving test compaction. The procedure is the first to combine these two concepts in a single procedure. The combination is made possible by a definition of a multicycle skewed-load test that is suggested in this paper, and complements the definition of a multicycle broadside test. Experimental results demonstrate the effectiveness of multicycle broadside and skewed-load tests in achieving test compaction for benchmark circuits. [ABSTRACT FROM AUTHOR]

A logic diagnosis procedure provides information about the defects that are present in a faulty unit as a set of candidate faults. To obtain smaller, and more accurate, sets of candidate faults, a diagnostic test generation procedure produces a test set that distinguishes fault pairs. This paper observes that large sets of candidate faults are obtained when multiple defects are present in a faulty unit, even if a diagnostic test set is used for logic diagnosis. This points to the possibility that fault pairs do not provide a complete set of targets for diagnostic test generation. This paper analyzes the conditions that cause a large set of candidate faults to be formed under a particular logic diagnosis procedure and suggests new targets for diagnostic test generation. The experimental results for benchmark circuits demonstrate that a diagnostic test set can be improved by adding diagnostic tests for the new targets. [ABSTRACT FROM AUTHOR]

This paper defines a new type of a low-power broadside test, called a reverse low-power broadside test, whose application requires design-for-testability logic. The unique feature of a reverse low-power broadside test is that it duplicates the switching activity during the second functional capture cycle of a given low-power broadside test, except that signal-transitions are reversed. Thus, the switching activity of a reverse low-power broadside test duplicates that of a low-power broadside test in every subcircuit and on every line individually. In addition, the reversed test detects different faults, and can thus increase the fault coverage of a low-power broadside test set. This paper studies the ability of reverse low-power broadside tests to increase the transition fault coverage in benchmark circuits considering functional broadside tests as well as low-power broadside tests that are not functional. [ABSTRACT FROM AUTHOR]

Test generation procedures target a variety of fault models in order to produce test sets that are effective for defect detection. This paper considers the likely scenario where two-cycle skewed-load tests are generated to detect single transition faults, and the test set is complemented with tests for single stuck-at faults that are not detected by the transition fault test set. For this scenario, this paper makes several unique observations that can be utilized to produce a single compact test set that consists only of two-cycle skewed-load tests for both fault models. The first observation is that a single-cycle test for a stuck-at fault can be transformed into a skewed-load test that is guaranteed to detect the stuck-at fault without performing logic or fault simulation. The second observation is that skewed-load tests, which are transformed from single-cycle tests for stuck-at faults, sometimes detect more transition and stuck-at faults than tests that were generated for transition faults. The third observation is that a static test compaction procedure, which is based on the modification and removal of tests, is effective in this context because it allows tests for stuck-at faults to detect more transition faults and vice versa. This paper describes a test compaction procedure based on these observations and presents experimental results for benchmark circuits to demonstrate the effectiveness of the procedure. [ABSTRACT FROM AUTHOR]

This paper defines a new type of multicycle tests called autonomous multicycle tests. Similar to multicycle scan-based tests, autonomous multicycle tests include several consecutive functional capture cycles to enhance defect detection and achieve test compaction. Unlike multicycle scan-based tests, an autonomous multicycle test set uses the same initial state for all the tests. During the functional capture cycles of a test, the primary inputs are driven by primary outputs, and the circuit operates autonomously. A test uses a scan-in operation only for the initial primary input vector, and to determine the connection between the primary inputs and outputs. It uses a scan-out operation only for the final primary output vector. This results in reduced overheads related to storage requirements and test application time compared with scan-based tests, and several unique properties that are discussed in this paper. This paper describes a test generation procedure for autonomous multicycle tests that avoids sequential test generation, and presents experimental results to demonstrate the ability of the tests to detect target faults. [ABSTRACT FROM AUTHOR]

A novel test pattern generation method for multiple dc and ac faults is presented. The fault models considered include line stuck-at, bridging, transition, and transistor stuck-open faults. All faults are transformed into stuck-at faults with some constraints in the proposed two-timeframe circuit model such that all considered faults can be represented utilizing the user-defined fault model supported currently by most commercial ATPG tools. This makes it possible to generate a compact set of patterns for both dc and ac faults in one ATPG run without needing to modify the ATPG tool. Both launch-on-capture and launch-on-shift test methods are supported. The experimental results on ISCAS’89 and ITC’99 benchmark circuits show the effectiveness of the proposed method (PM) compared to earlier PMs. [ABSTRACT FROM AUTHOR]

Excessive switching activity in the fault-free circuit can cause a fault-free circuit to fail because of increased delays. For the same reason, excessive switching activity in a faulty circuit can cause a delay fault to escape detection. This paper observes that the switching activity is higher in the presence of multiple delay faults with higher multiplicities (larger numbers of single faults that are present in the circuit together). The challenge in addressing multiple faults is related to their large number. This paper addresses this challenge by an iterative procedure that is applied to transition faults under a low-power broadside test set, and has two subprocedures: 1) the first subprocedure finds multiple transition faults with excessive faulty switching activity and 2) the second subprocedure modifies the test set so as to avoid excessive faulty switching activity for the faults found by the first subprocedure. With every additional iteration there are fewer multiple transition faults that exhibit excessive faulty switching activity. The experimental results for benchmark circuits demonstrate the levels of excessive faulty switching activity in the presence of multiple transition faults, and the possibility of reducing or even eliminating it after a small number of iterations. [ABSTRACT FROM AUTHOR]

Heterogeneous multiprocessor systems on a chips (MPSoCs) consisting of cores with different performance/power characteristics are widely used in many real-time embedded systems, where both soft-error reliability and lifetime reliability are key concerns. Although existing efforts have investigated related problems, they either focus on one of the two reliability concerns or propose time-consuming scheduling algorithms that cannot adequately address runtime workload and environmental variations. This paper introduces an online framework which is adaptive to runtime variations and maximizes soft-error reliability while satisfying the lifetime reliability constraint for soft real-time systems executing on MPSoCs that are composed of high-performance cores and low-power (LP) cores. Based on each core’s executing frequency and utilization, the framework performs workload migration between high-performance cores and LP cores to reduce power consumption and improve soft-error reliability. Experimental results based on different hardware platforms show that the proposed approach reduces the probability of failures due to soft errors by at least 17% and 50% on average compared to a number of representative existing approaches that satisfy the same lifetime reliability constraints. [ABSTRACT FROM AUTHOR]

Scan-based tests that maintain close-to-functional operation conditions are important for avoiding overtesting of delay faults while achieving the fault coverage required for avoiding test escapes. For a measurable proximity to functional operation conditions, partially functional broadside tests have a known Hamming distance between their scan-in states and reachable states. Another parameter that is important for the discussion of overtesting is the switching activity. This paper suggests a combined metric, where a reduced switching activity is taken as a safety margin that allows a higher Hamming distance between the scan-in state and a reachable state. The metric is defined such that a value of 100% or lower is preferred. To demonstrate that the metric is flexible enough to allow tests to be generated, the paper describes a test generation procedure that uses the metric. [ABSTRACT FROM PUBLISHER]

Cryptographic architectures provide different security properties to sensitive usage models. However, unless reliability of architectures is guaranteed, such security properties can be undermined through natural or malicious faults. In this paper, two underlying block ciphers which can be used in authenticated encryption algorithms are considered, i.e., light encryption device and high security and lightweight block ciphers. The former is of the Advanced Encryption Standard type and has been considered area-efficient, while the latter constitutes a Feistel network structure and is suitable for low-complexity and low-power embedded security applications. In this paper, we propose efficient error detection architectures including variants of recomputing with encoded operands and signature-based schemes to detect both transient and permanent faults. Authenticated encryption is applied in cryptography to provide confidentiality, integrity, and authenticity simultaneously to the message sent in a communication channel. In this paper, we show that the proposed schemes are applicable to the case study of simple lightweight CFB for providing authenticated encryption with associated data. The error simulations are performed using Xilinx Integrated Synthesis Environment tool and the results are benchmarked for the Xilinx FPGA family Virtex-7 to assess the reliability capability and efficiency of the proposed architectures. [ABSTRACT FROM PUBLISHER]

This paper develops a merging procedure for functional test sequences that achieves test compaction for a pool of functional test sequences by reducing the number of sequences in the pool. The procedure has the following new features: 1) in contrast to existing selection procedures, the merging procedure described in this paper increases the fault coverage of test sequences in the pool, thus enhancing the ability to reduce the number of sequences and 2) in contrast to existing procedures that concatenate or merge test sequences, the procedure described in this paper does not increase the lengths of the sequences it merges. The procedure is based on the concept of restoration of test vectors. In the context of test sequence merging, restoration consists of copying test vectors from a test sequence Tj into a test sequence Ti in order to allow Ti to detect faults that Tj detects. The merging procedure focuses on the removal of one test sequence Tj at a time by restoring test vectors from Tj into other sequences, allowing them to detect the faults that Tj detects. Experimental results for benchmark circuits demonstrate that the procedure reduces the number of sequences in a pool significantly. [ABSTRACT FROM PUBLISHER]

Contemporary and emergent automotive systems are heavily populated by complex integrated electronics. The number of safety-critical devices used in advanced driver-assistance systems or autonomous vehicles is growing with high-end models containing hundreds of embedded microcontrollers. Achieving functionally safe automotive electronics requires test solutions that might be costly to engineer. Therefore, to address challenges posed by high-quality and long-term reliability requirements, this article presents low-cost test pattern generation schemes for a scan-based hybrid logic BIST of automotive ICs. It may allow one to optimize test coverage and test time during in-system test applications. The first presented technique deploys a seed-flipping PRPG to periodically complement PRPG stages in a methodical tree-traversal manner. The second scheme is based on a seed-sorting approach that allows additional tradeoffs between test data volume and test coverage. As shown in this article, the proposed schemes can be easily integrated with a test compression environment and deployed in different modes of in-system testing, such as key-off, key-on, and periodic (incremental) online tests. Experimental results obtained for automotive designs and reported herein show improvements in test quality over conventional logic BIST schemes. [ABSTRACT FROM AUTHOR]

Two challenges are combined when compressed tests are computed for path delay faults: 1) path delay faults that are important to detect are associated with long paths, and many of these faults are undetectable and 2) it may not be possible to compress a given test for a path delay fault. This paper addresses these challenges in the context of test data compression methods that are based on a linear-feedback shift-register (LFSR). The basic approach that this paper uses modifies initially random seeds for the LFSR into seeds that produce tests for detecting target faults. This approach can find seeds even if the available tests cannot be compressed into seeds. In addition, the procedure described in this paper also selects detectable path delay faults to address the presence of undetectable path delay faults in the set of target faults. For this purpose it uses a metric that measures the similarity between target and detected path delay faults, and attempts to compute seeds that increase the values of this metric. Experimental results are presented to demonstrate the ability of the procedure to detect path delay faults in benchmark circuits. [ABSTRACT FROM AUTHOR]

The poor quality of the die stacking process for 3-D integrated circuits can result in the failure of the process in the through-silicon-vias (TSVs) in dense regions. Previous works use the same number of redundant TSVs and architectures that do not consider the TSV density. A repair architecture and an appropriate number of redundant TSVs, which are chosen considering the TSV density, are required for an improved repair rate. This paper proposes a method that demonstrates such an architecture and calculates the required number of TSVs. The method has a high repair rate for clustered faults, and wire-length problems are solved using the shift-based repair method. [ABSTRACT FROM AUTHOR]

Due to many state-holding elements in asynchronous circuits, many faults need two-pattern tests. This paper presents a test methodology (DR-scan) for dual-rail asynchronous circuits. Our design for testability is a full-scan, clock-less technique that supports both one-pattern and two-pattern tests for single stuck-at faults. DR-scan is able to test memory elements in dual-rail logic without breaking local feedback loops. To reduce test time, we choose a minimum set of selected test configurations (TCs). If there are more than one selected TCs, we need to split scan latches into multiple scan chains. To apply two-pattern tests, we partition the circuit using vertex coloring. With our test methodology, we can apply traditional full-scan automatic test pattern generation (ATPG) to generate two-pattern tests with high test coverage. Experimental results show our methodology can achieve test coverage up to nearly 94% for various asynchronous circuits. [ABSTRACT FROM AUTHOR]

A functional test sequence for a design may not be effective as a manufacturing test for a logic block in the design because it achieves a low gate-level fault coverage. This paper describes a procedure for selecting a clock sequence that increases the gate-level fault coverage of a functional test sequence when it is used for testing a subset of logic blocks. The procedure deactivates the clocks to the logic blocks in the subset when a primary input vector has a negative effect on their fault coverage. The procedure is different from earlier test generation and test compaction procedures in that it increases the fault coverage without modifying the functional test sequence. It thus preserves some of the functional characteristics and the test application process for the sequence. Experimental results for benchmark circuits are presented to demonstrate the effectiveness of the procedure. [ABSTRACT FROM AUTHOR]

It was shown earlier that certain primary input values have a negative effect on the fault coverage of a functional test sequence when they appear repeatedly in the sequence. A gate-level sequential test generation procedure based on this observation computed a primary input cube c with preferred values, and generated random functional test sequences that conformed to c with a high probability 0.5 \leq p < 1 . This procedure selected values for p out of a set of possible values, and assigned the same value of p to all the primary inputs. Motivated by the low computational complexity of this procedure, this paper addresses the selection of p and the possibility of using different values of p for different primary inputs. The goal is to increase the fault coverage and reduce the number of functional test sequences. The procedure described in this paper adjusts a functional test sequence to a circuit by complementing values that conflict with c . The procedure requires fewer functional test sequences to reach or exceed the fault coverage of the earlier procedure for benchmark circuits. The procedure can be applied to any functional test sequence or set of functional test sequences. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel post-bond through-silicon via (TSV) test method for post-bond TSV manufacture test. The proposed method can measure the RGC parameters of TSVs using switched-capacitor circuits and calibration method and detect TSV leakage fault, open fault, high-resistance fault, and delay fault based on the measured RGC parameters. The test process has a high resolution and is robust. The fault-detection effectiveness is evaluated via HSPICE simulations. The results of the TSV capacitance measurement have a relative error within 1%, the TSV resistance measurement results have a relative error within 5%, and the TSV conductance measurement results have a relative error within 8.5%. We also perform an Monte Carlo simulation to prove that even under process variation, the proposed method can obtain a TSV capacitance within an absolute error of ±3 fF, obtain a TSV resistance with a relative error of no more than 18.4%, and obtain a TSV conductance of less than 100 ${\mu \Omega }^{{-1}}$ with a relative error of no more than 13%. [ABSTRACT FROM AUTHOR]

This paper shows that existing delay-based testing techniques for power gating exhibit both fault coverage and yield loss due to deviations at the charging delay introduced by the distributed nature of the power-distribution-networks (PDNs). To restore this test quality (TQ) loss, which could reach up to 67.7% of false passes and 25% of false fails due to stuck-open faults, we propose a design-for-testability logic that accounts for a distributed PDN. The proposed logic is optimized by an algorithm that also handles uncertainty due to process variations and offers tradeoff flexibility between test application time and area cost. A calibration process is proposed to bridge model-to-hardware discrepancies and increase TQ when considering systematic variations. Through SPICE simulations, we show complete recovery of the TQ lost due to PDNs. The proposed method is robust, sustaining 80.3%–98.6% of the achieved TQ under high random and systematic process variations. To the best of our knowledge, this paper presents the first analysis of the PDN impact on TQ and offers a unified test solution for both ring and grid power gating styles. [ABSTRACT FROM PUBLISHER]

This paper introduces a novel test data compression scheme, which is primarily devised for low-power test applications. It is based on a fundamental observation that in addition to low test cube fill rates, a very few specified bits, necessary to detect a fault, are actually irreplaceable, whereas the remaining ones can be placed in alternative locations (scan cells). The former assignments are used to create residual test cubes and, subsequently, test templates. They control a power-aware decompressor and guide automatic test pattern generation to produce highly compressible test patterns through finding alternative assignments. The proposed approach reduces, in a user-controlled manner, scan shift-in switching rates with minimal hardware modifications. It also elevates compression ratios to values typically unachievable through conventional low-power reseeding-based solutions. Experimental results obtained for large industrial designs illustrate feasibility of the proposed test scheme and are reported herein. [ABSTRACT FROM AUTHOR]

Identical instances of a logic block are included in a design to improve its performance or reliability. This allows instances at close proximity to be tested by comparing their output responses, alleviating the need to know which tests will be applied, or what the fault-free response is. This paper considers an approach to online testing where the primary output sequences of identical finite-state machines that receive the same primary input sequences are compared to detect faults. To address the hardware and delay overheads of bringing one of the machines to the same state as the other before starting the output comparison process, this paper describes an initialization process where only part of the state of one machine is loaded into the other, and subsequences of their common primary input sequences are used for completing the initialization process. A unique feature of this process is that it addresses the situation where the input sequences that are applied during online testing, and the initial state for output comparison, are unknown. With this initialization process it is possible to start the output comparison process at an arbitrary point during functional operation. Experimental results for benchmark circuits demonstrate the percentages of state variables who values need to be loaded from one machine to the other, the fault coverage that can be achieved by output comparison following initialization, and the occurrence of failures in the initialization process. [ABSTRACT FROM AUTHOR]

Ternary content addressable memories (TCAMs) are special memories which are widely used in high-speed network applications such as routers, firewalls, and network address translators. In high-reliability network applications such as aerospace and defense systems, soft-error tolerant TCAMs are indispensable to prevent data corruption or faults caused by radiation. This paper shows a novel way in generating keys to cover the correct match. It proposes a novel soft-error tolerant TCAM for multiple-bit-flip errors using partial don’t-care keys (X-keys). First, this paper observes the case of single-bit-flip errors by X-TCAM. Second, it extends the X-TCAM to the case of multiple-bit-flip errors called KX-TCAM, where K stands for the maximum number of errors k . KX-TCAM corrects up to k -bit-flip errors and enhances the tolerance of the TCAM against soft errors, where k is the maximum number of bit flips in a word of a TCAM. KX-TCAM consists of a TCAM, a preprocessed don’t-care-bit index look-up memory (X look-up), and a backup error checking and correction (ECC)-SRAM. First, KX-TCAM randomly selects a search key. After that, KX-TCAM detects multiple-bit-flip errors by the generated X-keys using the X look-up. If the keys match the different locations, then a soft error is suspected and KX-TCAM refreshes the TCAM words by using the backup ECC-SRAM. Experimental results show that the soft-error tolerance capability of KX-TCAM significantly outperforms existing state-of-the-art schemes. Moreover, the hardware overhead of KX-TCAM is small due to the use of a single TCAM. KX-TCAM can be easily implemented and is useful for fault-tolerant packet classifiers. [ABSTRACT FROM PUBLISHER]

Security-sensitive usage models, such as implantable and wearable medical devices are prone to algorithmic cryptographic attacks as well as malicious implementation attacks. The cryptographic algorithms in these cryptosystems, such as lightweight block ciphers utilized in constrained applications, face significant tradeoff between the high level of security and the efficiency of their implementation metrics. For thwarting fault analysis attacks, among effective variants of active implementation attacks, and also to detect natural faults, efficient fault diagnosis schemes for these lightweight block ciphers are essential. In this paper, for the first time, we propose error detection schemes for lightweight block cipher, KLEIN, to ameliorate its error resiliency with low hardware complexity. The proposed fault diagnosis architectures are for linear and nonlinear components of this cipher. We also consider the notion of fault space transformation for lightweight cryptography and present its potential complications. The implementation of the proposed schemes through variants of Xilinx field-programmable gate arrays and the error coverage assessed with fault injection simulations show the effectiveness of the proposed schemes with acceptable footprints. [ABSTRACT FROM AUTHOR]

Scan test data compression is widely used in industry to reduce test data volume (TDV) and test application time (TAT). This paper shows how multiple scan chain expansion ratios can help to obtain high test data compression in system-on-chips. Scan chains are partitioned with a higher expansion ratio than normal in scan compression mode and then are gradually concatenated based on a cost function to detect any faults that could not be detected at the higher expansion ratios. It improves the overall test compression ratio since it potentially allows faults to be detected at the highest expansion ratio. This paper introduces a new cost function to choose scan chain concatenation candidates for concatenation for multiple expansion ratios. To avoid TDV and TAT increase by scan concatenation, the proposed method takes a logic structure and scan chain length into consideration. Experiment results show the proposed method reduces TAT and TDV by 53%–64% compared with a traditional scan compression method. [ABSTRACT FROM AUTHOR]

Memristors are an attractive option for use in future memory architectures but are prone to high defect densities due to the nondeterministic nature of nanoscale fabrication. Several works discuss memristor fault models and testing. However, none of them considers the memristor as a multilevel cell (MLC). The ability of memristors to function as an MLC allows for extremely dense, low-power memories. Using a memristor as an MLC introduces fault mechanisms that cannot occur in typical two-level memory cells. In this paper, we develop fault models for memristor-based MLC crossbars. The typical approach to testing a memory subsystem entails testing one memory cell at a time. However, this testing strategy is time consuming and does not scale for dense, memristor memories. We propose an efficient testing technique that exploits sneak-paths inherent in crossbar memories to test several memory cells simultaneously. In this paper, we integrate solutions for detecting and locating faults in memristors. We develop a power aware built-in self-test solution to detect these faults. We also propose a hybrid diagnosis scheme that uses a combination of sneak-path and March testing to reduce diagnosis time. The proposed schemes enable and leverage sneak-paths during fault detection and diagnosis modes, while disabling sneak-paths during normal operation. The proposed hybrid scheme reduces fault detection and diagnosis time by 24.69% and 28%, respectively, compared to traditional March tests. [ABSTRACT FROM PUBLISHER]

Scan design is a de facto design-for-testability (DfT) technique that enhances access during manufacturing test process. However, it can also be used as a back door to leak secret information from a secure chip. In existing scan attacks, the secret key of a secure chip is retrieved by using both the functional mode and the test mode of the chip. These attacks can be thwarted by applying a reset operation when there is a switch of mode. However, the mode-reset countermeasure can be thwarted by using only the test mode of a secure chip. In this paper, we perform a detailed analysis on the test-mode-only scan attack. We propose attacks on an advanced encryption standard (AES) design with a basic scan architecture as well as on an AES design with an advanced DfT infrastructure that comprises decompressors and compactors. The attack results show that indeed the secure chips are vulnerable to test-mode-only attacks. The secret key can be recovered within 1 s even in the presence of decompressors and compactors. We then propose new countermeasures to thwart these attacks. The proposed countermeasures incur minimal cost while providing high success rate. [ABSTRACT FROM PUBLISHER]

In a two-step defect diagnosis process, a fault detection test set is used for initial diagnosis to compute an initial set of candidate faults. When the initial set is large, diagnostic tests are generated based on the candidate faults in the set, and the set is refined based on the extended test set. This paper investigates the ability of functional broadside tests to serve as diagnostic tests for refining initial sets of candidate faults. The paper discusses the advantages of using functional broadside tests for this purpose. These advantages are related to the fact that the tests create functional operation conditions, and thus avoid nonfunctional effects that may make diagnosis less accurate. It also describes a multistep defect diagnosis process that uses functional broadside tests. Experimental results are presented to show the extent to which functional broadside tests can reduce initial sets of candidate faults. [ABSTRACT FROM PUBLISHER]

A defect diagnosis procedure is an important part of the yield improvement process. As defects become more complex, the output responses they produce differ to larger extents from the output responses of modeled faults, and they become more difficult to diagnose. Biases in the defect diagnosis procedure can also cause defects to be more difficult to diagnose. It is important to study and remove such biases in order to ensure that they do not affect the accuracy of the procedure. This paper undertakes a study of the biases of a defect diagnosis procedure and suggests a way to improve it. The study illustrates an approach by which biases in defect diagnosis procedures can be analyzed in general. [ABSTRACT FROM AUTHOR]

The security of a system-on-chip (SoC) can be compromised by exploiting the vulnerabilities of the finite state machines (FSMs) in the SoC controller modules through fault injection attacks. These vulnerabilities may be unintentionally introduced by traditional FSM design practices or by CAD tools during synthesis. In this paper, we first analyze how the vulnerabilities in an FSM can be exploited by fault injection attacks. Then, we propose a security-aware FSM design flow for ASIC designs to mitigate them and prevent fault attacks on FSM. Our proposed FSM design flow starts with a security-aware encoding scheme which makes the FSM resilient against fault attacks. However, the vulnerabilities introduced by the CAD tools cannot be addressed by encoding schemes alone. To analyze for such vulnerabilities, we develop a novel technique named analyzing vulnerabilities in FSM. If any vulnerability exists, we propose a secure FSM architecture to address the issue. In this paper, we mainly focus on setup-time violation-based fault attacks which pose a serious threat on FSMs; though our proposed flow works for advanced laser-based fault attacks as well. We compare our proposed secure FSM design flow with traditional FSM design practices in terms of cost, performance, and security. We show that our FSM design flow ensures security while having a negligible impact on cost and performance. [ABSTRACT FROM AUTHOR]

In 3-D integrated circuits (3D-ICs), through silicon via (TSV) is a critical technique in providing vertical connections. However, the yield is one of the key obstacles to adopt the TSV-based 3D-ICs technology in industry. Various fault-tolerance structures using spare TSVs to repair faulty functional TSVs have been proposed in literature for yield and reliability enhancement, but a valid structure cannot always be found due to the lack of effective generation methods for fault-tolerance structures. In this paper, we focus on the problem of adaptive fault-tolerance structure (AFTS) generation. Given the relations between functional TSVs and spare TSVs, we first calculate the maximum number of tolerant faults in each TSV group. Then we propose an integer linear programming-based model to construct the AFTS with minimal multiplexer delay overhead and hardware cost. We further develop a speed-up technique through an efficient min-cost-max-flow model. All the proposed methodologies are embedded in a top-down TSV planning framework to form functional TSV groups and generate AFTSs. Experimental results show that, compared with state-of-the-art, the number of spare TSVs used for fault tolerance can be effectively reduced. [ABSTRACT FROM AUTHOR]

This paper introduces a novel solution for building fault aware memory built-in self-test infrastructure based on rules of fault periodicity and regularity in memories and test algorithms. These periodicity and regularity rules are described via special internal structures named fault periodicity table (FPT) and test algorithm template (TAT). Three dimensions of evolution are considered as inputs for forming the mentioned structures: memory cells, multidimensional memory circuits, and memory systems for systems-on-chip where memories are distributed in different subchips. Each column of FPT corresponds to a fault nature which can be associated with a variety of different test mechanisms while each row of FPT corresponds to a fault family determined by the complexity of fault sensitization. FPT allows considering any large number of faults in one table while TAT allows constructing test algorithms without using test algorithm generation tools. Experimental results of the solution applied to both Planar-based (90/65/45/28 nm) and FinFET-based (16/10/7 nm) memory technologies are adduced also in this paper. [ABSTRACT FROM AUTHOR]

This paper presents a novel test architecture that combines the advantages of high-quality deterministic scan-based test and low-cost built-in self-test. The main idea is to record (store) all required compressed test data in a novel scan chain structure, and extract and decompress them during testing. This requires a very high compression ratio to obtain a low test data volume, that is, smaller than the number of scan cells in the circuit under test. To achieve such a high compression ratio, we propose a novel compression method that combines broadcast scan as well as a tailored single-input compression architecture. We also utilize the concept of scan chain partitioning and clock gating to reduce the test time and test power. An on-chip test controller is employed to automatically generate all required control signals for the whole test procedure. This significantly reduces the requirements on external automatic test equipment. Experimental results show that our method is well suitable for multicore designs. For example, experiments on the 8-core open-source OpenSPARC T2 processor with 5.7M gates show that all required test data for 100% testable stuck-at fault coverage can be stored in just 59.4% of the scan cells of the processor. Experimental results for transition faults are also presented, which show that more identical cores are needed in order to store all test data for transition faults. We also discuss how to extend this paper to address fault diagnosis and engineering change order problems. [ABSTRACT FROM AUTHOR]

Physical unclonable functions (PUFs) have broad application prospects in the field of hardware security. Like faults in general-purpose circuits, faults may also occur in PUFs. Fault diagnosis plays an important role in the yield learning process. Traditional fault diagnosis methods are based on comparing the fault-free responses of a design and the failing responses of chips. However, different manufactured, fault-free PUFs with the same design have different challenge-response pairs, so PUFs do not have deterministic, fault-free responses. Hence, traditional fault diagnosis methods are unsuitable for PUFs. To effectively diagnose PUFs, this paper proposes a diagnostic challenge generation method for the typical PUF: arbiter PUF. The diagnostic challenges that can deterministically or probabilistically distinguish the suspect faults of arbiter PUFs are generated. Simulation experiments on diagnosing failing arbiter PUF instances show that all the actual fault locations are accurately included in the candidate sets, and the average number of candidate locations (i.e., diagnostic resolution) is 1.585. FPGA experiments on diagnosing real PUFs show that the diagnostic accuracy is also 1, and the average diagnostic resolution is 1.602. [ABSTRACT FROM AUTHOR]

Opens are known to be one of the predominant defects in nanoscale technologies. With an increasing number of complex cells in today’s very large-scale integration designs intracell opens are becoming a larger and larger problem. Typically, these defects are modeled by transistor stuck-off faults (TSOFs) and assumed to be detected by transition delay fault (TDF) timing tests. However, tests for TDF fail to detect a high percentage of TSOFs and even tools that target them directly are not sufficient to screen all open defects. Furthermore, generated tests might be invalidated in case hazards and charge-sharing are not properly considered. In this paper, we present a waveform-accurate SAT-based automatic test pattern generation (ATPG) framework to tackle these problems. The proposed method not only allows for the generation of tests that are robust against hazards and charge-sharing, it can also be used to generate tests for faults only detectable by hazard-based activation—and hence even increase the fault coverage beyond state-of-the-art cell-aware tests. Our experimental results for the largest ITC’99, IWLS 2005 as well as larger industrial circuits mapped to the state-of-the-art NanGate 45-nm as well as NanGate 15-nm cell library using complex cells show the high efficiency and scalability of the proposed method. For example, the results show that without properly considering hazards and charge-sharing up to 17.9% of the generated tests could be invalidated. In addition, hazard-activated ATPG allows to detect an additional 10.1% of conventionally undetectable faults that could result in a very significant defective parts per million improvement. [ABSTRACT FROM AUTHOR]

Test data compression methods reduce the input test data volume by allowing compressed tests to be stored on a tester. Additional reductions in the input test data volume can be achieved if each stored test is used for producing several different tests. Skewed-load tests create a unique opportunity to expand a stored test into several different skewed-load tests by continuing to shift the scan-in state for one or more additional clock cycles. This opportunity for test data volume reduction beyond test data compression is introduced in this paper. The paper describes a procedure that starts from a given skewed-load test set. The procedure removes tests from the test set and recovers the fault coverage by applying several tests based on every stored test. [ABSTRACT FROM PUBLISHER]

Digital microfluidic biochips (DMBs) are microfluidic devices that manipulate droplets on an array of electrodes. Microfluidic operations, such as transport, mixing, and split, are performed on the electrode array to perform a biochemical application. All previous work assumes that the DMB architecture is given and most approaches consider a rectangular shape for the electrode array. However, nonrectangular application-specific architectures are common in practice. Hence, in this paper, we propose an approach to the synthesis of application-specific architectures, such that the cost of the architecture is minimized and the timing constraints of the biochemical application are satisfied. DMBs can be affected by permanent faults, which may lead to the failure of the biochemical application. Our approach introduces redundant electrodes to synthesize fault-tolerant architectures aiming at increasing the yield of DMBs. We have used a tabu search metaheuristic for this architecture synthesis problem. We have proposed a technique to evaluate the architecture alternatives visited during the search, in terms of their impact on the timing constraints of the application. The proposed architecture synthesis approach has been evaluated using several benchmarks. [ABSTRACT FROM AUTHOR]

This paper investigated the soft errors caused by particle strikes, such as high-energy neutrons, extending beyond the deep submicrometer era. Considering the structure of the layout and resulting nuclear reactions, multiple transient faults (MTFs) tend to be induced more frequently than do single transient faults (STFs), due to the effects of technology scaling. This means that the soft error rates (SER) are beyond traditional netlist-based STF analysis, which can result in serious mis-estimations. This paper proposes a layout-based soft error estimation framework, which takes into account MTFs from the device level to the circuit level. This framework comprises two systems: 1) generation and 2) propagation. In the generation system, transient faults are modeled through nuclear reactions, charge collection, and voltage transformation at the device level. The propagation system abstracts these effects from the device level to the circuit level, taking into account three masking mechanisms associated with the propagation of transient faults. Experiment results demonstrate that the SER can be underestimated by an average of 15.72% if only single (rather than multiple) transient faults are taken into account. Our results indicate that netlist-based analysis for the estimation of SERs is no longer sufficient, due to the overwhelming influence of the structural layout. Thus, using benchmark c432 , a tighter layout will result in an SER 34% higher than that generated in a looser layout. [ABSTRACT FROM AUTHOR]

Through silicon via (TSV) is the enabling technology for 3-D integrated circuit (IC) realization. To develop manufacturing tests for 3-D ICs, TSV has to be accurately modeled. Analytical methods are commonly used to develop circuit models for TSVs. These models are often difficult to develop and require some assumptions to simplify the problem. This paper presents a new method utilizing computer-aided design tools to extract circuit models for prebond and postbond TSVs. It is shown how the effects of common TSV parametric and catastrophic faults such as pinholes, voids, and open circuits affect TSV circuit models through 3-D full-wave simulations. It is also shown that the substrate conductivity has a considerable effect on the TSV fault characterization. The extracted models indicate that even a relatively large void does not alter the TSV characteristic parameters and thus voids remain largely undetected with conventional test solutions. An on-chip circuit, utilizing a delay-locked loop is presented as a test solution to detect TSV parametric faults. [ABSTRACT FROM AUTHOR]

Observation points in the combinational logic of a circuit can aid in the diagnosis of logic defects by reducing the number of indistinguished fault pairs. This paper considers the use of observation points in the combinational logic for the diagnosis of scan chain defects under an approach to test application called transparent-scan. Tests that are used for the diagnosis of scan chain defects include functional capture cycles that propagate the effects of scan chain faults through the combinational logic. Scan chain faults can thus be distinguished based on the values that are propagated in their presence to an observation point in the combinational logic. The procedure for observation point insertion considers the following parameters with respect to scan chain faults: 1) the number of indistinguished fault pairs and 2) the distances, measured in numbers of scan cells, between the faults that cannot be distinguished. With lower distances, a set of candidates for a faulty scan chain is likely to contain faults in the same vicinity of the scan chain. This facilitates failure analysis. Experimental results demonstrate the effectiveness of observation points in the combinational logic for scan chain diagnosis under transparent-scan. [ABSTRACT FROM PUBLISHER]

Although the near threshold voltage (NTV) design has achieved energy efficiency, certain challenges remain regarding its application. In this paper, we describe the analysis of thermally induced reliability concern in test process. In an NTV environment, the thermal dependency of a circuit delay is changed, and a difference in thermal constraints from that in a nominal voltage design exists. In addition, we propose a new test scheduling method for NTV circuits that alleviates the thermal constraints in system-on-chip test processes. Our simulation results show that the test time could be reduced while minimizing the reliability loss. [ABSTRACT FROM AUTHOR]

In secure cryptographic primitives, such as block ciphers, the reliability of hardware implementations needs to be closely considered because faults in the hardware implementations can potentially reduce or impact on the underlying security. In this paper, we present approaches to detect errors in hardware implementations of the inversion in GF(28). The proposed approaches are based on both nonredundant and redundant arithmetic, utilizing normal basis (nonredundant) and two redundant Galois field representations, i.e., polynomial ring representation and redundantly represented basis through tower fields. To the best of our knowledge, this is the first work focusing on the error detection architectures for redundant arithmetic-based inversion in GF(28). The presented signature-based schemes in this paper are general and can be applied to block ciphers with 8-bit S-boxes, such as Camellia, SMS4, the advanced encryption standard, and CLEFIA. We present the results of error simulations and application-specific integrated circuit implementations to demonstrate the utility of the presented schemes. Based on the specific implementation’s security/reliability objectives and the overhead/degradation tolerance for implementation/performance metrics, one can fine-tune and tailor the proposed work to achieve more reliable inversions in GF(28). [ABSTRACT FROM PUBLISHER]

Image processing circuits are expected to play an important role in Internet of Things electronic systems. For this type of circuits, errors (e.g., those due to wear out) might not be perceptible to us due to our insensitivity to small variances in images or colors. In the case that errors are acceptable (imperceptible), the systems are very likely to still be functional but with only minor performance degradation. The lifetime of the systems thus can be extended. Although there have been several attributes proposed in the literature to test acceptability of errors, these attributes do not consider human beings’ sensitivity to structural variances of erroneous images. This may result in acceptability misclassification of errors. In this paper, we take this into consideration and propose a new test method to more accurately evaluate acceptability of errors. Compared with the available attributes that can also extract the structural information of images, our method has much lower computation complexity, which is advantageous for shortening test time. This also makes our method hardware efficient. It is shown that the incurred area overhead of our method is low. The proposed method is to be applied periodically in-field to examine the reliability of the target circuit. We thus consider errors that may occur during in-field use. Single/multiple stuck-at faults and noises are considered, and a total of 161 460 erroneous images are generated. The experimental results on these diverse images show that on average the test accuracy of our method is more than 99%. [ABSTRACT FROM AUTHOR]

This paper describes a new approach to static test compaction for scan circuits that modifies tests in order to reduce the number of tests in a test set. The main contribution of this paper is a procedure referred to as restoration. In a basic step, the restoration procedure considers two tests, t \mathbf {rem} and t \mathbf {mod} , with sets of detected faults D \mathbf {rem} and D \mathbf {mod} , respectively. Starting from t \mathbf {new} = t \mathbf {mod} , and considering t \mathbf {new} as a variation of t \mathbf {rem} , the procedure restores bits of t \mathbf {rem} into t \mathbf {new} as necessary to ensure that faults from D \mathbf {rem} are detected by t \mathbf {new} . The procedure then restores bits of t \mathbf {mod} into t \mathbf {new} as necessary to ensure that all the faults from D \mathbf {mod} are detected by t \mathbf {new} . The test t \mathbf {new} is used for replacing t \mathbf {mod} , and the faults it detects out of D \mathbf {rem} are moved to D \mathbf {mod} . After several such steps, if D \mathbf {rem} becomes empty, t \mathbf {rem} can be removed from the test set. The procedure is applied to test sets that are already compacted. The results show that the procedure can achieve significant additional compaction even without considering all the tests for removal or modification. [ABSTRACT FROM PUBLISHER]

As the automotive industry enters a period of rapid evolution changing the way cars are designed and produced, the number of complex safety-critical components deployed in advanced driver assistance systems or autonomous vehicles is progressively rising with high-end models containing around 120 MCUs. These integrated circuits must adhere to stringent requirements for high quality and long-term reliability driven by functional safety standards. This requires test solutions that address challenges posed by automotive electronics. This paper presents Stellar BIST—a next generation compression scheme for in-system automotive test. The proposed solution can work with any sequential test compression. It builds on a finding that certain clusters of test vectors are capable of detecting many random-resistant faults, where a cluster consists of a parent (base) pattern and its transformed derivatives. Stellar BIST involves generating vectors based on simultaneous and multiple complements of scan slices of encodable parent patterns. The multiple complements are also skewed between successive patterns to diversify the resultant tests. The new scheme elevates compression to values unachievable through conventional reseeding-based solutions and provides significant tradeoffs between storage requirements and test application time, critical for in-system automotive applications. The experimental results obtained for industrial designs and different fault models illustrate feasibility of the proposed test scheme and are reported herein. [ABSTRACT FROM AUTHOR]

Reliability of embedded memory is critical for system-on-chips (SoCs). Aging-induced faults manifest in field, and they affect the reliability of embedded memories which occupy the most area of an SoC. By performing a proactive approach that repairs aged memory words in use, the probability of fault occurrence should be minimized. In this paper, we proposed an in-field strategy that proactively repairs aged words as well as correctable words. The reliability is enhanced further by combining an aging test, an in-field repair, and an error correction technique. An adaptive reconfiguration of the memory words, including aged words, correctable words, and uncorrectable words, is implemented with small overhead. A 3-state model that identifies memory cells as healthy, aged, or faulty is newly introduced, and the reliability evaluation using this model demonstrates the effectiveness of the proposed strategy. [ABSTRACT FROM AUTHOR]

Analog/RF built-in test (BIT) techniques are essential for reducing the very high costs of specification-based tests and for high-safety applications. The adoption of a BIT technique needs to be decided at the design stage, and this can be facilitated by estimating the test quality in terms of errors such as test escapes (${T_{E}}$) and yield loss (${Y_{L}}$). Test quality estimation at the design stage has been traditionally very difficult for analog/RF circuits due to the lack of fault models that properly cover parametric faulty behavior. In recent years, statistical simulation has been considered in combination with learning techniques for the estimation of parametric test metrics. Extreme value theory (EVT) has provided a rigorous tool for the computation of parametric test metrics. However, test metrics estimation has been limited to the use of a univariate model. In this paper, we extend this approach by using a multivariate extreme value model. We illustrate this for the evaluation of an RF LNA BIT technique using a bivariate model. [ABSTRACT FROM AUTHOR]

Traditionally, increasing logical masking probability has been used to improve the circuit reliability against single-event transients (SETs). As the very first work, this paper presents a new approach to increase the reliability of digital circuits against soft errors caused by multiple event transients (METs) by taking advantages of circuit partitioning and local logical restructuring techniques. In the proposed approach, the circuit is partitioned into various subcircuits and, then, several structures of each subcircuits which satisfy the area constraints are extracted by using a graph-based procedure. In order to select the suitable alternative between various subcircuit structures, we introduce a novel metric named global failure probability in the presence of METs (GFPM). This parameter provides an evaluation of each subcircuits contribution in the soft error rate (SER) of the given circuit making it possible to estimate the impacts of changing the structure of the subcircuits on the circuit SER. Hence, it prevents from repeatedly calculating the SER of the circuit that is very time-consuming leading to significant improvements in the optimization runtime. Experimental studies on ISCAS benchmark circuits show that the proposed approach, on average, achieves 18.4% SER reduction with 11.9% area overhead and 8.2% delay overhead comparing to the original circuit while the global SET-based SER mitigation approach and the global MET-based SER mitigation approach achieve 8.46% and 21.8% SER reduction, respectively. Besides, the proposed technique is about $580 \times $ faster than the global MET-based method. [ABSTRACT FROM AUTHOR]

Outsourcing of integrated circuit (IC) fabrication to external foundries has lead to many new security vulnerabilities, including IC piracy, overbuilding, and reverse engineering. In this regard, logic locking (LL) was introduced to protect intellectual property from such threats. In this paper, we evaluate the strength of various LL techniques, including earlier works, such as random LL (RLL) and fault analysis-based LL (FLL), against power-based side-channel attack. We have developed attacks where at least 60% of the key bits can be successfully recovered for 60% of the circuits for both RLL and FLL using a 32-bit key. However, the success rate reduces to 45% and 35% for RLL and FLL, respectively, when using a 64-bit key. We demonstrate the practicality of our proposed attack by mounting it against RLL and FLL implementations of ISCAS’85 and MCNC benchmark circuits on Spartan-6 FPGA platform. Further, we present differential power analysis (DPA) results on mutual information analysis on LL techniques that capture any dependence between the intermediate data and the captured power traces. We also formally establish that resilience to satisfiability-based (SAT) attack implies resilience to DPA attack as well for an LL technique. We validate this further via experiments on Spartan-6 FPGA on SAKURA-G development board for a recent LL technique that is known to thwart the SAT attack. [ABSTRACT FROM AUTHOR]

Most cipher implementations are vulnerable to a class of cryptanalytic attacks known as fault injection attacks. To reveal the secret key, these attacks make use of faults induced at specific locations during the execution of the cipher. Countermeasures for fault injection attacks require these vulnerable locations in the implementation to be first identified and then protected. However, both these steps are difficult and error-prone and, hence, it requires considerable expertise to design efficient countermeasures. Incorrect or insufficient application of the countermeasures would cause the implementation to remain vulnerable, while inefficient application of the countermeasures could lead to significant performance penalties to achieve the desired fault-attack resistance. In this paper, we present a novel framework called SAFARI for automatically synthesizing fault-attack resistant implementations of block ciphers. The framework takes as input the security requirements and a high-level specification of the block cipher. It automatically detects the vulnerable locations from the specification, applies an appropriate countermeasure based on the user-specified security requirements, and then synthesizes an efficient, fault-attack protected, RTL, or C code for the cipher. We take AES, CAMELLIA, and CLEFIA as case studies and demonstrate how the framework would explore different countermeasures, based on the vulnerability of the locations, the output format, and the required security margins. We then evaluate the efficacy of SAFARI in hardware and software to the design overhead incurred and the fault coverage. [ABSTRACT FROM AUTHOR]