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Detailed physics of the third quadrant electrical characteristics of 1.2-kV rated 4H-SiC accumulation (Acc) and inversion (Inv) channel MOSFETs, based on experimentally measured data and TCAD numerical simulations, are described in this paper for the first time. The power MOSFETs with various channel lengths (0.3, 0.5, 0.8, 1.1 $\mu \text{m}$) used in this paper were fabricated in a 6-in commercial foundry. Numerical simulations verified that there are two current paths in the third quadrant: 1) through the base region and 2) through the p-n body diode. This paper demonstrates that the Acc MOSFETs have a smaller third quadrant knee voltage (${V}_{{\text {knee}}})$ of −1.2 V compared with −1.9 V for the Inv MOSFETs (at ${V}_{g} = {0}$ V and room temperature). Numerical simulations show that this difference is due to a smaller potential barrier for electron transport from the drain to the source in the base region for accumulation channel devices than inversion channel devices. Acc devices are shown to have a lower voltage drop in the third quadrant. [ABSTRACT FROM AUTHOR]

The first part of this paper presented mymargin the device-level comparison of emerging materials (In0.53Ga0.47As and 2-D materials) and device architecture (NW FETs) with s-Si FinFETs. In order to further understand the performance and energy efficiency of these device options for future technology nodes, it is required to go beyond the device-level comparison by accounting for not only intrinsic but also the extrinsic parasitic elements. In this paper, we present the comparison of s-Si, In0.53Ga0.47As, and 2-D material-based n-type MOSFETs using the circuit-level figure of merits across three successive future technology nodes. The analysis incorporates both device characteristics obtained from an advanced quantum mechanical simulation tool and circuit-level comparison, which accounts for device parasitic elements and wiring load. The results show that 2-D material DG MOSFETs present a more energy-efficient device option than s-Si and In0.53Ga0.47As FinFETs in sub-0.7-V supply voltage regime and In0.53Ga0.47As nanowire (NW) FETs can outperform s-Si multi-gate (MuG) FETs and 2-D material FETs, but when considering non-idealities, s-Si NW FETs remain both faster and more energy-efficient device option. [ABSTRACT FROM AUTHOR]

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations. [ABSTRACT FROM AUTHOR]

In the domain of printed electronics (PE), field-effect transistors (FETs) with an oxide semiconductor channel are very promising. In particular, the use of high gate-capacitance of the composite solid polymer electrolytes (CSPEs) as a gate-insulator ensures extremely low voltage requirements. Besides high gate capacitance, such CSPEs are proven to be easily printable, stable in air over wide temperature ranges, and possess high ion conductivity. These CSPEs can be sensitive to moisture, especially for high surface-to-volume ratio printed thin films. In this paper, we provide a comprehensive experimental study on the effect of humidity on CSPE-gated single transistors. At the circuit level, the performance of ring oscillators (ROs) has been compared for various humidity conditions. The experimental results of the electrolyte-gated FETs (EGFETs) demonstrate rather comparable currents between 30%–90% humidity levels. However, the shifted transistor parameters lead to a significant performance change of the RO frequency behavior. The study in this paper shows the need of an impermeable encapsulation for the CSPE-gated FETs to ensure identical performance at all humidity conditions. [ABSTRACT FROM AUTHOR]

In this paper, we propose a model for estimating short-channel effects (SCEs) in the shell-doped double-gate junctionless (JL) MOSFET. The main emphasis of this paper is to estimate SCEs by effectively capturing source/drain (S/D) extensions beyond the gate edges for different values of undoped core thickness (${T}_{\textsf {core}}$), shell doping (${N}_{\textsf {d}}$), gate length (${L}_{\textsf {g}}$), and gate (${V}_{\textsf {gs}}$) and drain (${V}_{\textsf {ds}}$) biases in subthreshold regime. The threshold voltage (${V}_{\textsf {th}}$), drain-induced barrier lowering and subthreshold swing (${S}$), extracted from transfer characteristics, are in good agreement with the simulation results. Results highlight the utility of shell doping and core thickness to provide an additional degree of freedom to control SCEs. The proposed model can be useful in estimating SCEs and optimizing core–shell JL architecture for low-power applications. [ABSTRACT FROM AUTHOR]

In this paper, the threshold voltage characteristics of silicon nanowire metal–oxide–semiconductor field-effect transistor (MOSFET) with a double-layer gate structure are presented. This type of device is considered to be the most promising application of nanodevice in ultralarge-scale integration, due to several advantages such as similar operation principle as the junctionless nanowire transistor, the screening effect of the upper gate (UG) to shield the lower gate MOSFETs from external electromagnetic disturbance, the tradeoff between the short channel and the thick-gate oxide layer, and the compatible fabrication process with the conventional MOS technology. In this paper, the relations of threshold voltage versus the gate length, the UG bias, the substrate bias, the drain bias, and the temperature are measured and analyzed. Moreover, the penetration effect of the UG electric field is proposed to interpret the short-channel characteristics of the device, and a piecewise curve model is presented to reveal the underlying physics of the relation of the threshold voltage versus the drain bias. The double-layer gate structure technology enables the design of many devices, such as small-signal analog circuit units, single-electron devices, and quantum bit cells. [ABSTRACT FROM AUTHOR]

In this paper, we examine the interplay of two serious reliability issues in MOSFET devices, namely, bias temperature instability (BTI) and hot-carrier degradation (HCD). Most publications are devoted to the characterization of either BTI or HCD, and complex models have been developed to independently describe each degradation mode. However, very limited data are available on the interplay of both degradation regimes, particularly the effect of a drain bias onto the charging and discharging dynamics of oxide traps. Part I of this paper provides an extensive experimental study toward the impact of mixed-mode stress conditions on the dynamics of oxide defects. Here, we present the first microscopic modeling approach beyond a simple electrostatic approximation. We extend the existing nonradiative multiphonon theory by taking nonequilibrium processes such as full carrier distribution functions which include the effect impact ionization along the channel into account. To ultimately validate our framework, we compare simulation results and experimental data for a single-oxide defect as well as a large ensemble of traps in a MOSFET device. We show that our modeling approach accurately captures the rather puzzling measurement trends for a broad stress regime and allows developing the knowledge on how oxide defects can be affected by an increased drain stress. [ABSTRACT FROM AUTHOR]

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications. [ABSTRACT FROM AUTHOR]

In this paper, we explored the characteristic fluctuations induced by various random discrete dopants (RDDs) on gate-all-around silicon nanowire metal–oxide semiconductor field-effect transistors. A 3-D quantum-mechanically corrected transport model was employed to analyze the simulated devices. The statistical results indicate that the variation of threshold voltage ( ${V}_{\text {th}}$ ) not only can be reduced from 28.6% to 10.7% without channel doping and penetration from the source/drain into the channel, but also the variation of 3-dB frequency can be reduced from 8% to 2.7% due to the reduction of the variation of ${V}_{\text {th}}$. We reported that the high-frequency characteristic fluctuations (voltage gain and cutoff frequency) were dominated by electron mobility. This caused by RDDs from the drain extension exhibited less variability than that caused by RDDs from the source extension due to a reduced injection velocity near the S side and a negligible difference in the electron saturation velocity near the D side. This paper provides pertinent information on the design of high-frequency amplifier circuits in relation to devices with RDDs induced by variations in the semiconductor process. [ABSTRACT FROM AUTHOR]

In this paper, a ZnO-based semiconductor thin film memristor (300 nm in thickness) device is fabricated using metallic top and bottom electrodes by direct-current reactive magnetron sputter. The memristive characteristics of the device were completed by time-dependent current--voltage (I--V-t) measurements, and the typical pinched hysteresis I--V loops of the memristor were observed. This paper is continued with the designing memristor emulator circuit, which has only four MOS transistors. The proposed circuit is suitable both for emulating the fabricated memristor and for using general memristor-based applications. Any circuit blocks such as a multiplier or active element are not used in the circuit to obtain memristive characteristics. All results of the proposed memristor emulator circuit are compatible with general characteristics of the fabricated semiconductor device. The MOSFET-based proposed memristor emulator circuit is laid out in the Analog Design Environment of Cadence Software using 180-nmTSMC CMOS process parameters and its layout area is 366 μm². So as to show its performance, the dependences of the operating frequency and process corner as well as effects of radical temperature changes have been investigated in the simulation results section. [ABSTRACT FROM AUTHOR]

In this paper, a high-quality crystalline thin film (~10 nm) of titanium dioxide (TiO2-II) phase is grown on p-GaAs (100) substrate by employing the vapor--liquid--solid method. The formation of crystalline TiO2-II films is confirmed by X-ray diffraction study. A very small rms surface roughness of ~1 nm has been measured from atomic force microscopy. The capacitance--voltage characteristics of Al/TiO2-II/GaAs metal--oxide--semiconductor (MOS) capacitor indicate the growth of excellent thin film of TiO2-II phase with high effective dielectric constant of 28, 35, 65, and 14 for the as-grown and 600 °C, 625 °C, and 650 °C annealed samples, respectively. An effective oxide thickness of ~0.7 nm, a negligible hysteresis of 10 mV, very small frequency dispersion of 3.5%, and a reduced gate leakage current of ~10-13 A/μm² at +2 V are achieved due to annealing in the temperature range of 600 °C-625 °C. Thus, this paper provides a cost-effective novel alternative technique to grow high-quality TiO2-II films on GaAs substrate which may be used as the reliable high-k gate dielectrics on III-V semiconductor-based MOS devices and circuits. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the impact of gate-source/drain underlap on short-channel behavior of junctionless (JL) transistor through a quasi-analytical model and 2-D numerical simulations. The proposed five-region model for potential is developed for the symmetric mode operation of double-gate (DG) JL MOSFET in the subthreshold regime, to predict and minimize short-channel effects (SCEs) using the optimum design of underlap regions. The five-region model can be transformed into four or three regions to incorporate the possible dependence of biases, doping, and gate workfunction with the underlap length. The parameters indicating SCEs can also be extracted using an analytical approximation for sub-threshold drain current. The results from the proposed model are in reasonable agreement with simulation data. Analyses show that underlap length is a critical parameter to restrict the lateral extension of depletion region into the ungated portion. With increasing the underlap length, SCEs improve prominently for moderate doping concentration (1018 cm-3). The improvement in SCEs ceases once the device achieves the maximum lateral extension of the depletion region. This paper provides the physical insights into the optimal use of underlap region in nanoscale JL devices for suppressing SCEs. [ABSTRACT FROM AUTHOR]

In this paper, reliability issues of In2O5Sn (indium-tin oxide: a transparent material) transparent gate recessed channel (TGRC)-MOSFET has been analyzed by considering the effect of interface trap charges (both positive and negative) present at the Si/SiO2 interface. Following device, characteristics are studied in terms of static, linearity, and intermodulation figure of merits. It is found that with the amalgamation of the transparent gate indium tin oxide on conventional recesses channel (CRC) MOSFET, it exhibits improved immunity against interface trap charges in comparison to CRC-MOSFET. In addition, the influence of ambient temperature (150-300 K) along with trap charges on TGRC-MOSFET has also been explored with an aim to analyze at which temperature of the device is more stable in the presence of interface defects (trap charges). Results obtained reveal that TGRC shows improved device performance at low temperature with trap charges being less influenced. Thus, this paper demonstrates that TGRC MOSFET can act as a promising candidate for low-power linear analog applications, where low temperature is required. [ABSTRACT FROM AUTHOR]

In this paper, a p-channel vertical 4H-silicon carbide (SiC) MOSFET (SiC p-MOSFET) has been fabricated successfully for the first time as a potential candidate for the complementary inverter application. The static characteristics and the robustness, including short circuit and avalanche capabilities of the p-MOSFET, are experimentally tested. Moreover, the comparison between the p-MOSFET and similar rating n-MOSFET is carried out. The short-circuit capability is 15% higher than that of the n-channel MOSFET. Furthermore, this paper also provides the physical insights into the failure mechanism during the short-circuit transient of the p- and n-MOSFET. Meanwhile, an electro-thermal analytical model is proposed to explain the thermal distribution during this transient. Last, the avalanche withstand time of the fabricated SiC p-MOSFET is experimentally demonstrated to be 27% higher than that of the n-channel one. It is concluded that the SiC p-MOSFET could be a competitive power switch applicable for high-frequency complementary inverters. [ABSTRACT FROM PUBLISHER]

Gate dielectric damage caused by both internal and external stresses is becoming worse because of aggressive complementary metal–oxide–semiconductor (CMOS) scaling. However, conventional technologies for damage reduction using thermal annealing during fabrication have some limitations. As a result, there is a growing demand for technologies that will cure CMOS damage as a new paradigm for improving long-term reliability. This review paper reexamines self-recovery technologies, which are fully compatible with CMOS fabrication. Although self-heating has long been considered an unwanted operating side effect, it can also be favorably utilized to cure damage. Generated Joule heat arising from device operation can uniformly anneal the gate dielectric and effectively recover damage in various devices, such as conventional logic, memory, and aerospace CMOS devices, as well as thin-film transistors for displays. [ABSTRACT FROM AUTHOR]

This paper presents a modeling approach to simulate the impact of total ionizing dose (TID) degradation on low-power analog and mixed-signal circuits. The modeling approach has been performed on 180-nm n-type metal–oxide–semiconductor field-effect transistors (n-MOSFETs). The effects of the finger number, channel geometry, and biasing voltages have been tested during irradiation experiments. All Berkeley short-channel insulated gate field-effect transistor model (BSIM) parameters relevant to the transistor properties affected by TID have been modified in an algorithmic flow to correctly estimate the sub-threshold leakage current for a given dose level. The maximum error of the model developed is below 8%. A case study considering a five-stage ring oscillator is simulated with the generated model to show that the power consumption of the circuit increases and the oscillation frequency decreases around by 14%. [ABSTRACT FROM AUTHOR]

In this paper, a physics-based bias-dependent model of single-event transients (SETs) in double-gate (DG) MOSFET suitable for circuit simulation is presented. The existing approaches that use double exponential and dual double-exponential current sources to emulate these transient currents in the circuit simulators depend on the parameters extracted from TCAD device simulations. In order to capture the essential physics behind these current transients in the circuit simulations, there is a need for a physics-based bias-dependent SET current model that considers the electrostatics in the chosen device. The proposed SET current model is developed from the solution of 2-D Poisson’s equation with proper boundary conditions of DG MOSFET. It takes into account the dependence of the transient potential and drain current on linear energy transfer (LET), strike positions, drain and gate biases, device dimensions, and channel doping. The results from the model are validated with the simulation results from TCAD. The SET current model is integrated in Cadence circuit simulator and observed through simulations the voltage perturbation at the output of the CMOS inverter due to heavy ion strike on nMOS transistor in OFF state for different LETs and loads. The proposed model captures the current plateau region effect in CMOS inverter. [ABSTRACT FROM AUTHOR]

This paper presents the first analytical model for the ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) in vertical power FinFETs. The model allows to extract the channel mobility and series resistance and to separate the current conduction through the bulk fin channel and the accumulation-mode metal–oxide–semiconductor (MOS) channel. The model was validated by experiments and simulations. The extracted series resistance was verified by measuring a diode fabricated in the same wafer with the FinFETs. At the same time, simulations using the extracted channel mobility and series resistance agreed well with the experiments. The model was then used to analyze a 1200 V GaN vertical power FinFET. The main ${R}_{ \mathrm{\scriptscriptstyle ON}}$ component was identified to be from the drift layer and the substrate, while the gate-modulated channel resistance only accounts for ~13% of the total device ${R}_{ \mathrm{\scriptscriptstyle ON}}$. Our model enables parameter extraction from the dc characteristics of a single device, and therefore, provides a fast and easy way to understand, analyze, and design vertical power FinFETs. Our model can also be adjusted to allow for fast and accurate parameter extraction in other power transistors with a vertical gate-modulated channel, such as trench MOSFETs. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel compact statistical model for the low-frequency noise (LFN) of MOS devices with halo implants. The compact model is suited for the incorporation in modern models, such as BSIM, PSP, and EKV, and can be used to predict the dependence of the LFN of halo-implanted MOSFETs with bias, temperature, geometry, and technological parameters. This compact model is based on the physics-based random telegraph noise (RTN) model, previously published by our group. The previous model was simplified in analytical expressions dependent on parameters and on physical quantities already calculated in modern compact models. Following the physics-based model, the LFN compact model predicts the large bias dependence of the LFN statistics induced by the halo implants in long-channel devices. Moreover, we show for the first time that the halo implants also induce a large temperature dependence of the LFN statistics for devices operated near the weak inversion or saturation, and the proposed compact model predicts this dependence. [ABSTRACT FROM AUTHOR]

In this paper, we present two accurate physics-based models of ballistic metal–oxide–semiconductor field-effect transistors (MOSFETs), both using less than ten parameters. These models—the capacitor model and the virtual source model—are based on the Landauer–Büttiker formalism. We show that the nonthermalization of charge carriers in the channels of ballistic MOSFETs leads to two critical effects that need to be considered in the modeling: the ballistic drain-induced barrier lowering (DIBL) effect and the floating source effect. The ballistic DIBL effect is responsible for a drain voltage dependence of the DIBL parameter; the floating source effect intensifies the injection of high-energy carriers from the source as the gate voltage increases. Specifically, the analysis is carried out on devices composed of monolayer black phosphorus, a 2-D semiconductor with unique electronic and mechanical properties, which make it a promising candidate for 2-D digital logic applications. [ABSTRACT FROM AUTHOR]

Self-heating in fully depleted silicon-on-insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is experimentally studied using the gate resistance thermometry technique, in a wide temperature range from 300 down to 4.2 K. We demonstrate that below 160 K, the channel temperature increase ($\Delta {T}$) due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance. This power dependence is interpreted in terms of temperature dependent thermal conductivity. The thermal resistance dependence on the active device temperature (${T}_{\text {Device}}$) indicates that the former one is mainly driven by the thermal conductivity of the oxide layer. Moreover, based on this dependence we reconstructed the channel temperature increase for each dissipated power and ambient temperature, and we found that the calculated values were in a good agreement with the experimental ones. Results indicate that even at low temperatures, thermal resistance does not depend significantly on the silicon channel thickness (ranging from 7 up to 24 nm), whereas the buried-oxide thinning (145 and 25 nm) strongly reduces the magnitude of the thermal resistance. Finally, this paper intends to fill the gap of experimental data concerning self-heating in advanced FDSOI transistors at low temperatures, revealing limitations and perspectives that should be taken into account for future work. [ABSTRACT FROM AUTHOR]

To continue with the scaling of high-performance transistors, alternate materials and device architectures are being explored as replacements for contemporary strained-silicon (s-Si) FinFETs. While III–V materials, such as In0.53Ga0.47As, offer higher electron mobilities and injection velocities than s-Si, emerging 2-D materials and nanowire (NW) device architectures promise better immunity to short-channel effects. In this paper, we present a detailed device-level performance comparison of s-Si, In0.53Ga0.47As, monolayer black phosphorus (BP), and WS2-based planar and multigate (Fin and NW) n-MOSFETs across three successive future technology nodes. The analysis incorporates both intrinsic device characteristics obtained from an advanced quantum mechanical simulation tool and the effect of nonidealities using a physics-based analytical model. The results indicate that 2-D materials, such as monolayer BP, offers higher ON currents than s-Si and In0.53Ga0.47As for planar device architectures. However, compared to modern s-Si and In0.53Ga0.47As Fin and NW FETs, monolayer BP and WS2 double-gate MOSFETs are reported to offer lower ON currents due to the smaller footprint at scaled technology nodes. [ABSTRACT FROM AUTHOR]

A p-type shield region (p-shield) under the gate trench is typically adopted in a SiC trench MOSFET for achieving a lower oxide field and reverse transfer capacitance ( Crss) . This paper comparatively studies the effects of a grounded p-shield and a floating p-shield. Device simulations using Sentaurus TCAD are carried out in this paper to reveal the devices’ internal dynamics. The floating p-shield can effectively reduce the OFF-state oxide field as a grounded p-shield does, without degrading its static performance. However, after being switched from the OFF-state, the ON-state oxide field in the trench MOSFET with a floating p-shield (FS-MOS) is dramatically elevated. Compared with the trench MOSFET with a grounded p-shield, the FS-MOS also exhibits a higher C{{\text {rss}}} and a consequently slower switching speed. Furthermore, the FS-MOS exhibits a degradation of dynamic R{ \mathrm{ON}} during switching operation. A charge storage mechanism is then presented to explain the dynamics in FS-MOS. Upon a high V{{\text {DS}}} , holes are emitted from the floating p-shield when the parasitic p-n-p structure consisting of p-shield, p-body, and n-region between them is punched through, leaving negative charges in the floating p-shield even when the high V{{\text {DS}}} is removed. Based on this mechanism, the behaviors of the FS-MOS are well explained. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model has been developed for junctionless silicon on insulator ion-sensitive FET for pH sensing applications. The pH sensors detect the change of the hydrogen ion concentration in the aqueous solution. The modeled results show good agreement with the simulation results obtained by using Sentaurus. The electrolyte region has been considered by changing appropriate intrinsic semiconductor material in which the electron and hole charges represent the mobile ions in the aqueous solution. The effect of pH on surface potential, threshold voltage, and drain current has been investigated through model and simulations. In addition, the impact of different gate oxide materials, which act as adhesion layer, has been investigated. The pH response is defined as the amount of threshold voltage shift when the pH (in the injected solution) is varied from lower to higher values. Effect of the electrolyte region thickness on the pH sensitivity has also been discussed in this paper. [ABSTRACT FROM AUTHOR]

In this paper, circuit level analysis of the high frequency and low noise performance of an RF CMOS device with L\mathrm{ eff}= 36 nm is performed using various layout schemes. By using the modeling methodology of interconnect metals and vias, it is found that the gate parasitic capacitance from the interconnects mainly affects the degradation of high frequency and noise performance. An optimized layout scheme is proposed to reduce the gate parasitic resistance and capacitance in this paper, and the proposed layout exhibits improved RF behaviors for fT , f\mathrm {\mathrm {MAX}} , and NFmin at 26 GHz up to ~13%, ~24%, and ~18% compared with the reference layout scheme, respectively. [ABSTRACT FROM PUBLISHER]

The focus of this paper is to understand the impact of the material properties of GaN, exploited using a vertical device, in power switching by estimating switching loss. The study was performed with a cascoded current aperture vertical electron transistor (CAVET). The normally OFF device was simulated and analyzed using a Silvaco ATLAS 2-D drift diffusion model integrated to SPICE-based circuit simulator. Besides evaluating the performance space and, hence, potential application space for GaN CAVETs, this paper presents significant accomplishment in establishing a device to circuit model, thereby, offering a reliable method of evaluating GaN-based power transistors. The accuracy of the model was established through the excellent agreement of simulated data with the data sheet specs of a commercial cascoded GaN high electron mobility transistor. The model was successfully applied to compare SiC MOSFETs with GaN CAVETs. A cascoded GaN CAVET has $2\times $ faster switching time, $3\times $ lower switching loss compared with standard commercial SiC MOSFET, owing to the higher electron mobility in GaN. Operating at frequencies of megahertz with low power loss, a GaN CAVET will, therefore, lead to smaller converter size and higher system efficiency. [ABSTRACT FROM PUBLISHER]

Thin-body self-aligned InGaAs MOSFETs are fabricated on a III-V-On-Insulator structure on a silicon active substrate (III-V-OIAS). The p-type Si active substrate acts as a back gate that can modulate the threshold voltage and other electrical characteristics of the device. This paper explores the physics behind this effect through 2-D simulations and comparison with experiments. In the off-state, we find that the application of a positive body-to-source ( V\mathrm{ bs} ) voltage increases the subthreshold swing but reduces drain-induced barrier lowering. The first effect is related to the electron profile and the location of the centroid of electron charge in the channel while the second is closely associated with the modulation of a depletion region in the silicon substrate. In the on-state, the series resistance is observed to improve under positive V\mathrm{ bs} due to the increased accumulation of electrons in the extrinsic portion of the device. In addition, the channel mobility exhibits a two-branch behavior in its dependence on the average vertical electric field in the channel. This is explained by the different interfacial scattering that takes place at the front and back channel surfaces. This paper highlights the tradeoffs involved in attempting to exploit the body bias in the operation of QW-MOSFETs in III-V-On-Insulator with active substrate. [ABSTRACT FROM PUBLISHER]

In the above paper, Kim et al. present a method for extracting source and drain resistance values in MOSFETs. We explain how the proposed method corresponds to a particular case of the method already proposed by Ortiz-Conde et al. in a seminal work published in 1994 and generalized two years later, which was not cited in the above-mentioned paper. We call attention to the fact that the absence in Kim’s method of the threshold voltage dependence on body-source voltage and such disregard might eventually lead to significant errors. [ABSTRACT FROM AUTHOR]

This paper presents the simulation-based comparison between silicon (Si) and silicon carbide (SiC) MOSFETs on the single-event burnout (SEB) performance for the first time. The safe operation areas (SOAs) regarding SEB are extracted and compared between the two structures when the heavy ions with a different linear energy transfer (LET) strike the sensitive areas of the devices. It is demonstrated that benefiting from the higher doped drift region, SiC MOSFET has a larger SEB threshold voltage than Si MOSFET at low LET range. However, it is the other way around at high LET range, which is attributed to the thicker epitaxy of Si MOSFET. The introduction of buffer layer to enhance the SEB hardness is also discussed. Results indicate that a thicker buffer layer is required for SiC MOSFET to enlarge the SOA, resulting in a more serious degradation of the specific ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$). Consequently, other hardening solutions need to be further explored to ensure the safe operation of SiC MOSFET in space applications. [ABSTRACT FROM AUTHOR]

Integrated circuits operated in the near-threshold region exhibit specific merit with high energy efficiency. A near-threshold model is highly required for the circuit design. In this paper, a near-threshold drain current model is proposed based on the surface inversion layer charge model for analyzing digital circuits. The short-channel effect in deep submicrometer is also included in the model. Moreover, the delay and energy parts based on the near-threshold drain current model are derived and integrated in the model. Two process design kits (PDKs) are used for parameter extraction to demonstrate the feasibility of the proposed model. The results show that the proposed model can be used for the near-threshold circuit calculation, with the benefit of high accuracy. [ABSTRACT FROM AUTHOR]

The 2-D materials possess application perspective in semiconductor logic devices owing to their bonding free surface carrier transport. However, the scaling transistor width-induced edge issues have significantly limited their surface transport within the lateral direction, leading to effective mass increasing, and bandgap fluctuations. Therefore, it is important to find a novel 2-D material with both excellent surface transport and immunity to edge effect. In this paper, inspired by the recently discovered tellurene and its unique Te-Te bonds, the edge effect on the transport characteristics of tellurene is studied theoretically in the form of tellurene nanoribbons (TNRs). Among the four edge types, three of them exhibit semiconducting characteristic owing to the unique bonding property of Te. Simulation results demonstrate that the tetragonal edges (TEs) in zigzag TNRs (ZTNRs) almost have no influence on surface transport, resulting in minimized bandgap and effective mass variations, compared to that of graphene nanoribbons, and Si and Ge nanowires. Transport behaviors of the TE-ZTNRs are investigated using a metal–oxide–semiconductor transistor model and a multiscale simulation flow, with the calculated current densities exceeding $\textsf {1}$ mA/ $\mu \text{m}$ and the on–off ratios over $10^{\textsf {11}}$. Based on the results, an explicit prediction that the TE-ZTNRs are competitive candidates for nanoscale transistor materials is proposed. [ABSTRACT FROM AUTHOR]

In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (${V}_{\textsf {BR}}$). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (${T}_{ \mathrm{\scriptscriptstyle ON}}$) and turn-off time (${T}_{ \mathrm{\scriptscriptstyle OFF}}$) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (${E}_{\mathbf {SW}}$). [ABSTRACT FROM AUTHOR]

In this paper, a super-junction p-type lateral diffused metal–oxide–semiconductor transistor (SJ-pLDMOS) utilizing electron to enhance the current capability is proposed. The proposed SJ-pLDMOS has an n-channel in the drain region and is controlled by an auto-generated voltage signal (${V}_{\mathrm {\textsf {Gn}}}$). The voltage signal ${V}_{\mathrm {\textsf {Gn}}}$ is generated during the ON- and OFF-state of the hole current which flows across an integrated resistor (${R}\text{p}$) implemented in the p-base region. Thus, the proposed SJ-pLDMOS utilizes both hole and electron currents to significantly enhance the current capability. Simulation results show that the current capability of the proposed SJ-pLDMOS without any conductivity modulation effect is comparable with that of a super-junction nLDMOS (SJ-nLDMOS). The total power loss of the proposed super-junction pLDMOS (SJ-pLDMOS) is reduced by about 26.7% and 18% compared with that of the SJ-nLDMOS and Triple Resurf nLDMOS (TR nLDMOS) at a rated load current density of $25~\mu \text{A}/\mu \text{m}$ , respectively. [ABSTRACT FROM AUTHOR]

In this paper, a novel superjunction (SJ) MOSFET embedded with an ultrasoft reverse-recovery body diode is proposed and studied by simulation. The device has a composite assistant layer, which consists of a highly doped n-buffer region and an extended p-pillar region, under the SJ layer. The assistant layer provides residual carriers during the reverse-recovery procedure and smoothens the current. Simulated results show that the soft factor is upgraded from 0.04 to over 0.3 when the depth of the assistant layer increases from $0~\mu \text{m}$ to that of the SJ layer. The increment of the specific ON-resistance is less than 10% if the concentration of the n-buffer region is 25 fold that of the n-pillar region. [ABSTRACT FROM AUTHOR]

Using TCAD simulations, the silicon carbide metal–oxide–semiconductor field-effect transistor with p-type floating islands (SiC FLIMOSFET) is systematically investigated in this paper. The doping concentration (NFLI), length (L), and position (D1) of floating islands are optimized according to breakdown voltage (BV), electric field distribution, and on-resistance. The results show that $\text{N}_{\textsf {FLI}} = \textsf {1} \times \textsf {10}^{\textsf {17}}$ cm $^{\textsf {-3}}, \textsf {L}= \textsf {2.5}\,\,\mu \text{m}$ , and $\textsf {D1}=9.0\,\,\mu \text{m}$ are superior values for FLI structure considering tradeoff between BV and on-resistance. With the same BV capacity, the on-resistance of SiC FLIMOSFET is decrease by 32% comparing to the conventional SiC VDMOSFET. Besides, the dynamic property shows 16.5% reduction of FoM $\text{R}_{\textsf {on}}\cdot \textsf {Q}_{\textsf {GD}}$ in the SiC FLIMOSFET. Significantly, comparing to the conventional structure, the electro-thermal simulation indicates that the SiC FLIMOSFET has a higher robustness under short-circuit condition owing to the reduction of thermal stress in SiC/SiO2 interface. All the results show that the SiC FLIMOSFET has a good potential in SiC power device. [ABSTRACT FROM AUTHOR]

Near-interface traps (NITs) with energy levels aligned to the conduction band and spatially located close to the SiO2/SiC interface are responsible for significant degradation of the channel-carrier mobility in 4H-SiC MOSFETs. In this paper, we investigate fast trapping and detrapping of the conduction-band electrons by NITs with energy levels localized between 0.13 and 0.23 eV above the bottom of the conduction band. The trapping and detrapping times were estimated to be in the range between the resolution limit of tens of nanoseconds and $1~\mu \text{s}$ by measuring the current through n-type MOS capacitors in response to a ramped voltage in the accumulation region. [ABSTRACT FROM AUTHOR]

This paper presents a low-temperature process to transfer devices on ultrathin silicon layers from a parent substrate to a foreign substrate or stack. MOS devices were fabricated on silicon-on-insulator (SOI) wafer. The device wafer was then temporarily bonded on a carrier wafer. The handle layer was etched and the remaining ultrathin silicon device layer of ~1.4 $\mu \text{m}$ was transferred to a foreign substrate using permanent bonding. Here, we explored two different bonding approaches, namely, 1) the gold–indium (Au–In) transient liquid phase (TLP) bonding and 2) the epoxy bonding. We demonstrate the advantages of epoxy bonding method over the TLP method. The unique characteristic of this epoxy bonding approach is its capability to vertically stack multiple thin silicon layers. Furthermore, we demonstrate three-layer stacking of the ultrathin silicon layers with functional metal–oxide–semiconductor field-effect transistors in each layer. Electrical characterization results of nMOS/pMOS devices in each layer is presented and compared for before and after transfer. Changes in measured device performance before and after stacking are studied using simulations. The maximum process temperature in this approach is 150 °C, which is considerably lower than those reported in the literature. This result demonstrates the feasibility of multilayer low-temperature stacking. [ABSTRACT FROM AUTHOR]

Due to outstanding properties of silicon carbide (SiC) and unipolar current conduction mechanism, the active chip size of SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) is significantly shrunk, which significantly improves switching performance. However, the termination region cannot be scaled down due to the existence of high breakdown electric field enclosing active region. Therefore, a SiC MOSFET switching loss model considering termination region effect is proposed in this paper with revealing physical insights into termination region during switching process. Furthermore, through theoretical analysis, model establishment, and simulation results, the loss breakdown under various blocking voltages (800, 1000, and 1200 V) for 1-, 3-, and 6-A current rated devices is obtained. ${E}_{\textsf {term}}$ and ${E}_{\textsf {acti}}$ as intrinsic loss of turn-on process make a significant contribution to the total switching loss under fast gate drive condition. The model shows that the turn-on and turn-off losses are under and overestimated, respectively, by using the commonly used electrical measurement. The loss from termination region aggravates the underestimation of turn-on loss and overestimation of turn-off loss further. The proposed loss estimation equation could provide accurate loss to help choose device and design power circuit for power electronic community. The results also raise new perspective to edge termination of efficient/reliable SiC MOSFET for device people. [ABSTRACT FROM AUTHOR]

In this paper, we present physical insights into the role of substrate on the anomalous frequency behavior of small-signal transconductance and output conductance in the ultrathin body and buried oxide fully depleted silicon-on-insulator MOS transistors. Using the simple dc analysis, we attribute this anomalous behavior to the negative feedback originating from both minority and majority carriers in the substrate at different frequency ranges. Through measurements and detailed TCAD simulations, we have shown that back-gate bias and substrate doping strongly modulate the frequency behavior of transconductance and output conductance. It is finally proposed that circuit/device designers can smartly use the back-gate bias and substrate doping to minimize the substrate effect and improve the frequency response of the device intrinsic gain. [ABSTRACT FROM AUTHOR]

In this paper, we propose a misaligned double-gate p-i-n impact ionization MOS (MIMOS) with a deliberate misalignment between the top and bottom gates. The presence of a misaligned bottom gate leads to band-to-band-tunneling of electrons at the source-intrinsic region interface and increases the number of carriers for impact ionization. The electric field redistribution provides a longer transport path for the carriers. Therefore, carriers gain higher kinetic energy, and the impact ionization rate is enhanced in the MIMOS. This results in a significantly lower avalanche breakdown voltage compared to conventional single-gate IMOS structure. Using calibrated 2-D simulations, we demonstrate that MIMOS exhibits a steep subthreshold slope (~6 mV/dec) at a significantly low-supply voltage of (${V}_{\text {DS}}= {0.59}$ V), which is ~48% lower than that of the corresponding single-gate IMOS (${V}_{\text {DS}}= {1.15}$ V). [ABSTRACT FROM AUTHOR]

In this paper, we have comprehensively studied the performance boosts of both nLDMOS and pLDMOS under the mechanical strain. The electrical properties of LDMOS under the uniaxial tensile and compressive strains along the channel direction are examined thoroughly. We find that the uniaxial tensile strain benefits the nLDMOS, and the uniaxial compressive strain benefits the pLDMOS. Because the mechanical strain affects carriers’ transportation in bulk Si and inverted channel distinctly, the strain effects are strongly correlated with the gate voltage, drain voltage, and devices’ dimensions. It is found that the LDMOS with the longer gate length is more preferred for the strain. The piezoresistance coefficients of both nLDMOS and pLDMOS under the uniaxial strain are evaluated for the first time. It is also shown that the mechanical strain can enhance the drain current without the degradation of the breakdown voltage, which suggests a downshift of the ON-resistance versus breakdown voltage curve. [ABSTRACT FROM AUTHOR]

In this paper, a dual-gate laterally double-diffused metal–oxide–semiconductor (DG-LDMOS) device with shallow trench isolation (STI) and sinker at the source side has been proposed. STI and sinker help to provide isolation and reduce the leakage current, respectively, in the device. This is an improvement over a single-gate (SG) LDMOS device when only one gate is used and no STI and sinker are there. The study of both the devices has been carried out using the ATLAS SILVACO simulator. In the simulation studies, all the dimensions and doping parameters of both devices have been kept the same except gate length and channel doping. The distance between two gates of DG-LDMOS device has been kept smaller. This has been done to overcome the island and overlapping issues. The simulation studies have shown a significant improvement in DG-LDMOS device parameters in comparison to the SG-LDMOS device. The DG-LDMOS device provides high breakdown voltage, low ON-resistance, high $f_{\sf {T}}$ and $f_{\sf {max}}$ , low drain-induced barrier lowering, and better output conductance as compared to conventional SG-LDMOS device. These features make the DG-LDMOS device an excellent candidate for RF applications. [ABSTRACT FROM AUTHOR]

The state-of-the-art RF and millimeter-wave circuits design requires accurate prediction of the nonquasi-static (NQS) effects at high frequency for all levels of channel inversion. This paper provides a practical insight to help high-frequency performance assessment of ultrathin body and box fully depleted silicon-on-insulator MOSFETs through a powerful frequency normalization scheme. Frequency dependence of small signal characteristics derived from experimental S-parameters is analyzed and reveals that the transconductance efficiency (${g}_{\textsf {m}}/{I}_{\textsf {D}}$) concept, already adopted as a low-frequency analog figure-of-merit (FoM), can be generalized to high frequency, including under asymmetric operation. We report that the normalized frequency dependence of the generalized transadmittance efficiency (${y}_{\textsf {m}}/{I}_{\textsf {D}}$) FoM only depends on the mobility and inversion coefficient. In addition, this approach is also used to extract essential parameters such as the critical NQS frequency ${f}_{\textsf {NQS}}$. [ABSTRACT FROM AUTHOR]

In this paper, analytical gate capacitance models for a large-signal compact model of AlGaN/GaN high-electron mobility transistors are proposed. Different from the MOSFET devices, different depletion regions on either side of the gate are fully considered for high-voltage GaN devices. The depletion regions are bias-dependent to implement the capacitance models into the large-signal compact model. A transfer function is proposed to characterize the switching behavior of the capacitances between on- and off-states, which is essential to describe all the states of a device, for example, operating at Class-B. Different from previous works, the current saturation phenomenon is taken into account in determining the intrinsic capacitances which are induced by nonstatic channel charge. The capacitance models can be easily implemented into the virtual-source-based model to accurately predict the S-parameters and large-signal output characteristics. [ABSTRACT FROM AUTHOR]

This paper presents the analyses on the self-sustained oscillation of superjunction MOSFET intrinsic diode. At first, the characteristics of the self-sustained oscillation for the superjunction MOSFET intrinsic diode are identified by the double-pulse switching test. The test results show that the self-sustained oscillation with significant self-amplification phenomenon can be triggered during the reverse recovery transient of superjunction MOSFET intrinsic diode. Based on the Sentaurus TCAD simulation, the self-sustained oscillation is reproduced. The simulation results reveal the root cause of the self-sustained oscillation. Due to the snappy reverse recovery of superjunction MOSFET intrinsic diode, the steep slope of diode snap off current can generate high voltage across the common source inductance, which drives the gate–source voltage and turns on the high-side MOSFET. The unexpected MOSFET turn-on can, in return, enhance the steepness of the current slope when the diode snap off. This leads to a positive feedback process and self-sustained oscillation is generated. In the end, based on the theoretical analyses and experimental results, the necessary methods that can suppress the oscillation are presented. [ABSTRACT FROM AUTHOR]

A compact model for tunnel diode body contact (TDBC) silicon-on-insulator (SOI) n-MOSFETs was developed in this paper. The compact model is implemented in Verilog-A to simulate the dc and radio frequency (RF) performance of a TDBC SOI MOSFET. The TDBC SOI MOSFETs are successfully fabricated and are used to measure important transistor electrical parameters. The investigation results reveal that TDBC structure suppresses floating body effects (FBEs) as well as T-gate body (TB) contact structure and shows significant improvement in RF performance without introducing additional parasitic capacitances compared with the TB device. Kink phenomena and an abnormal subthreshold swing originating from FBEs are sufficiently suppressed. It is demonstrated that the TDBC SOI MOSFETs provide a promising concept for digital, analog, and RF applications. The outputs from this analytic model are in fair agreement with the TDBC experimental data, which validates the effectiveness and robustness of the compact model for TDBC SOI technology. Finally, good accuracy ensures that the proposed model is applicable for the implementation in circuit simulation tools. [ABSTRACT FROM AUTHOR]

The degradations of electrical parameters for double-trench silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) under repetitive avalanche stress are investigated in this paper. The injection of hot holes into the bottom oxide of the gate trench during avalanche process is demonstrated to be the dominant degradation mechanism, while the channel is rarely influenced by the stress. The injected holes attract extra electrons in the SiC layer along the SiC/SiO2 interface, decreasing the ON-state drain–source resistance (${R}_{{dson}}$). Due to this reason, the threshold voltage (${V}_{{th}}$) of the device also reduces slightly. Moreover, other than static electrical parameters, dynamic characteristics including the gate–drain capacitance (${C}_{{gd}}$) and the switching characteristics of the device also degrade. After being stressed by repetitive avalanche stress, the depletion region beneath the bottom of the gate trench gets thinner, leading to the increase in ${C}_{{gd}}$ , which further influences the switching behaviors. The turn- ON and turn- OFF switching times of the device are calculated. It illustrates that the repetitive avalanche stress results in an obvious delay in the turn- OFF procedure, but hardly influences the turn- ON behaviors of the double-trench SiC MOSFET. [ABSTRACT FROM AUTHOR]

A lumped-circuit nonquasi-static (NQS) model, that is applicable for both large-signal transient simulations and a small-signal ac analysis, is developed in this paper. An improved physical equivalent circuit, capturing NQS effects in the millimeter waveband, is derived using a transmission line model, by incorporating the high-frequency longitudinal gate electrode and a channel distributed RC network. The proposed model is implemented in a BSIM-BULK MOSFET model and validated with dc and RF data, obtained from technology computer-aided design device simulations and experimental data. The proposed model is in very good agreement with the data up to ${50}{f}_{t}$. The transient currents, for a gate-voltage switching rate of ${5}\times {10}^{{10}}$ V/s, show excellent match with the data. The dc, transient, and ac simulations using the proposed model are much faster than a 10-segmented MOSFET model. This shows that the proposed model is better than other computationally complex compact models, for most RF applications. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate experimentally a photodetector based on silicon-on-insulator substrate. The photosensing diode is formed in the substrate induced by the backgate bias instead of doping. TCAD simulation is conducted to confirm that the field-induced junction performs similarly as the doped p-n junction in terms of photodetection. A simplified process flow with low process temperature is developed to fabricate the device, which can save implantation step and reduce the cost. The photoresponses of the device under various biases, light intensities, and wavelengths are studied systematically with both experiment and TCAD simulation. Responsivity up to 1150 A/W is achieved experimentally. In addition, the response spectrum can be modulated by the back gate bias, which is a very attractive feature for multiband photodetection application. The field-induced photodiode in the substrate modulates the threshold voltage of the MOSFET at top Si layer as efficiently as the doped junction, confirmed by TCAD simulation. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the impact of spacer dielectrics on the ultrascaled silicon gate-all-around junctionless transistor in the ballistic regime based on the in-house 3-D quantum simulator that self-consistently solves mode-space nonequilibrium Green function formalism and Poisson’s equation. Then, the impact of device parameters, such as lengths of source/drain region and channel, channel width, and nanowire direction, on the static performance is also discussed in detail. An available range of spacer dielectric constant is further selected. Results show that the high-k spacer introduced in the ultrascaled junctionless transistor can effectively enhance the direct-current performance of the device and suppress the variation of drain current and subthreshold characteristics induced by the aforementioned device parameters. It will be a great benefit for the junctionless device with a gate-all-around structure as the scaling continues to approach the end of MOSFETs. [ABSTRACT FROM AUTHOR]