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Inverter delay is often evaluated as $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ , where ${C}$ is the load capacitance, ${V}_{\text {dd}}$ is the supply voltage, and ${I}_{\text {eff}}$ is the effective drive current derived by approximating the inverter switching trajectory with a linear model. The ${I}_{\text {eff}}$ model utilizes high and low drain currents conventionally measured in wafer acceptance tests and does not require extraction of any parameters. Ease of use combined with reasonable accuracy (~15%) is the main reason for wide application of $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ delay metrics. However, $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ expression produces large errors when applied to another two important basic circuits: NAND and NOR. This is because NAND and NOR circuits contain transistor series connections not accounted for in the inverter model. In this paper, an analytical solution for the transistor series connection influence on the discharge/charge operation in NAND/NOR circuits is provided. The model for NAND/NOR effective drive current (denoted as ${I}_{\text {stack}}$) developed in this paper maintains simplicity of the original ${I}_{\text {eff}}$ expression. It requires only one additional measurement of the linear current. Model accuracy was assessed by comparing to extensive SPICE delay simulations of NAND and NOR circuits designed using state-of-the-art MOS technologies. Comparison results show that $\textit {CV}_{\text {dd}}/{I}_{\text {stack}}$ equation provides ~15% accuracy for NAND/NOR circuits in line with $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ accuracy for inverter. In an era of emphasis on low-power design, the developed model presents convenient means of exploring design space when optimizing circuit supply voltage for low-power operation. [ABSTRACT FROM AUTHOR]

In this paper, the impact of charge transfer doping on the variability of multiwalled carbon nanotube (MWCNT) local interconnects is studied by experiments and simulations. We calculate the number of conducting channels of both metallic and semiconducting carbon nanotubes as a function of Fermi level shift due to doping based on the calculation of transmission coefficients. By using the MWCNT compact model proposed in Part I of this paper, we study the charge transfer doping of MWCNTs employing Fermi level shift to reduce the performance variability due to changes in diameter, chirality, defects, and contact resistance. Simulation results show that charge transfer doping can significantly improve MWCNT interconnect performance and variability by increasing the number of conducting channels of shells and degenerating semiconducting shells to metallic shells. As a case study on an MWCNT of 11 nm outer diameter, when the Fermi level shifts to 0.1 eV, up to ~80% of performance and standard deviation improvements are observed. Furthermore, a good match between experimental data and simulation results is observed, demonstrating the effectiveness of doping, the validity of the MWCNT compact model and proposed simulation methodology. [ABSTRACT FROM AUTHOR]

This paper proposes a semianalytical model to estimate short-channel effects for independent gate operation in double-gate (DG) junctionless (JL) MOSFET incorporating gate-to-source/drain underlap, through the solution of Poisson’s equations in the subthreshold regime. The model also accounts for the asymmetry in device operation through variation in gate oxide thicknesses, gate work functions, and underlap lengths. Subthreshold drain current, threshold voltage, and subthreshold swing, evaluated from the channel potential, show reasonable agreement with simulation data. Results suggest the use of negative back gate bias and longer underlap length to reduce off-current. This paper highlights the role of doping, underlap length, and back gate bias in tuning the threshold voltage. This model serves as a generic formulation (within limits) with different asymmetries to estimate, design, and optimize self-aligned DG JL transistors for subthreshold logic applications. [ABSTRACT FROM AUTHOR]

This paper investigates the temperature dependence of random telegraph noise (RTN) in 3-D NAND Flash technologies. Experimental results on memory arrays reveal an increase of RTN when temperature is reduced, which is mainly attributed to the growth of the amplitude of the fluctuations arising from RTN traps. A direct proof of this growth is provided by directly monitoring some RTN waveforms arising from single traps in cells out of either memory arrays or test elements. In order to explain this evidence, the TCAD model for polysilicon NAND strings presented in Part I of this paper is adopted and extended to address the amplitude of the threshold-voltage shift coming from the trapping of a single electron at different positions in cell channel. Numerical results successfully reproduce the experimental trends with temperature and allow to explain them in terms of stronger nonuniformities in polysilicon inversion when temperature decreases. In particular, the reduction of temperature makes the string currentmore controlledby the polysilicon grain boundaries, increasing, in turn, the amplitude of the RTN fluctuations arising from traps placed on or close to them. [ABSTRACT FROM AUTHOR]

In this paper, we present the operation principle of an organic metal–insulator–semiconductor (MIS) capacitor where the organic semiconductor is undoped. In spite of a low charge concentration within the semiconductor, this device exhibits a capacitance variation with respect to the applied gate voltage yielding the capacitance–voltage characteristics similar to that of a traditional MIS capacitor based on the doped semiconductor. A physics-based model is developed to derive the charge concentration, surface potential, and the capacitance of the organic MIS capacitor. The model is validated with TCAD simulation results as well as with experimental data obtained from the fabricated organic MIS capacitor consisting of poly(4-vinylphenol) and poly(3-hexylthiophene-2, 5-diyl) as an insulator and a semiconductor, respectively. [ABSTRACT FROM AUTHOR]

Compact flicker noise models used in SPICE circuit simulators are derived from the seminal BSIM unified noise model. In this paper, we show that use of this model can give anomalous bias dependence of input referred noise. In addition, we find that the state-of-the art flicker noise models are not adequate to capture the drain bias dependence of flicker noise in short channel devices. In this paper, we address both the issues with a new compact model. [ABSTRACT FROM AUTHOR]

In the above paper, Kim et al. present a method for extracting source and drain resistance values in MOSFETs. We explain how the proposed method corresponds to a particular case of the method already proposed by Ortiz-Conde et al. in a seminal work published in 1994 and generalized two years later, which was not cited in the above-mentioned paper. We call attention to the fact that the absence in Kim’s method of the threshold voltage dependence on body-source voltage and such disregard might eventually lead to significant errors. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel generalized multiparticle drift-diffusion (mp-DD) model capable to overcome some limitations imposed by the classic drift-diffusion model by taking into account multiple carrier populations. We demonstrate the model’s ability and flexibility in simulating systems from different application contexts. We conclude that the developed mp-DD model allows investigating a wide range of complex mechanisms, such as subband charge transport calculation or intersystem crossing (ISC), which are crucial for the understanding and design of organic and inorganic semiconductor devices largely employed for both photovoltaics and light emitting applications. [ABSTRACT FROM AUTHOR]

Integrated circuits operated in the near-threshold region exhibit specific merit with high energy efficiency. A near-threshold model is highly required for the circuit design. In this paper, a near-threshold drain current model is proposed based on the surface inversion layer charge model for analyzing digital circuits. The short-channel effect in deep submicrometer is also included in the model. Moreover, the delay and energy parts based on the near-threshold drain current model are derived and integrated in the model. Two process design kits (PDKs) are used for parameter extraction to demonstrate the feasibility of the proposed model. The results show that the proposed model can be used for the near-threshold circuit calculation, with the benefit of high accuracy. [ABSTRACT FROM AUTHOR]

Silicon carbide (4H-SiC) devices experiencing avalanche conditions can reach temperatures above 1500 K. Simulation of impact ionization in devices should, therefore, include models valid up to such high temperatures. However, calibrations of impact ionization coefficients are available only up to 580 K, and simulations of switching show deviations from measurements at higher temperatures. In this paper, a more accurate model based on the underlying physics of high temperature and anisotropic avalanche generation is proposed. This model enables calibrations performed at room temperature along the ${c}$ -axis to be more precisely extrapolated to any temperature of interest in 2-D device simulations. The model provides an excellent fit to the measurements of breakdown voltages during unclamped inductive switching tests of power MOSFETs, enabling a more accurate prediction of ruggedness. The more comprehensive physics included in the model makes it also applicable to other wide bandgap semiconductors such as GaN, diamond, and Ga2O3, which also exhibit a high critical electric field. [ABSTRACT FROM AUTHOR]

In this paper, uniformly doped drift region of silicon carbide (SiC) super-junction (SJ) MOSFET is replaced with vertical variable doping profile (VVD) to achieve a better tradeoff between breakdown voltage (BV) and specific ON-resistance (${R}_{\text {sp,on}}$). While it is known that the SJ device consists of two vertical columns of n- and p-type, SJ VVD feature lies in increasing the doping concentration from top to bottom in the N-column and vice-versa in the P-column within the drift region. The proposed SJ VVD allows $\text {R}_{{\text {sp, on}}}$ to reduce further due to increased average doping concentration in conducting N-column and BV to increase further due to shifting of an electric field from corners to the center of the drift region. BV and ${R}_{\text {sp,on}}$ improved by 10% in an SJ VVD MOSFET and these parameters follow linear relationship similar to SJ MOSFET. The 2-D numerical simulations from Synopsys TCAD are used for investigating the static and dynamic characteristics of the device. In addition to 30% improvement in Baliga figure of merit, 35% improvement is obtained over SJ MOSFET in turn on and turn off switching energies for a clamped inductive circuit at 1200 V–20 A. Improved dynamic characteristics of SJ VVD can be attributed to reduction in gate charge (${Q}_{g}$) and miller capacitance (${c}_{\text {rss}}$) compared to SJ MOSFET. [ABSTRACT FROM AUTHOR]

This paper presents a commercial or industrial view of III–V compact models for circuit design. We contrast the requirements of III–V modeling to those of silicon. The differences in requirements are strongly rooted in the applications that III–V devices are used in the end user of III–V models and the differences in the “ecosystems” of the technologies. These differences create both challenges and opportunity for the III–V modeling community. [ABSTRACT FROM AUTHOR]

A compact model for tunnel diode body contact (TDBC) silicon-on-insulator (SOI) n-MOSFETs was developed in this paper. The compact model is implemented in Verilog-A to simulate the dc and radio frequency (RF) performance of a TDBC SOI MOSFET. The TDBC SOI MOSFETs are successfully fabricated and are used to measure important transistor electrical parameters. The investigation results reveal that TDBC structure suppresses floating body effects (FBEs) as well as T-gate body (TB) contact structure and shows significant improvement in RF performance without introducing additional parasitic capacitances compared with the TB device. Kink phenomena and an abnormal subthreshold swing originating from FBEs are sufficiently suppressed. It is demonstrated that the TDBC SOI MOSFETs provide a promising concept for digital, analog, and RF applications. The outputs from this analytic model are in fair agreement with the TDBC experimental data, which validates the effectiveness and robustness of the compact model for TDBC SOI technology. Finally, good accuracy ensures that the proposed model is applicable for the implementation in circuit simulation tools. [ABSTRACT FROM AUTHOR]

Considering the demand of III–V multigate (MUG) transistors for next-generation CMOS technologies, a compact model is required to test their performance in different circuits. The low effective mass and highly confined geometry of these MUG devices demand the use of computationally expensive coupled Poisson–Schrödinger (PS) solver for terminal charges and surface potential. In this paper, we propose an approximation, which decouples the PS equations and enables the development of a computationally efficient analytical model. The surface potential and semiconductor charge equations for III–V low effective mass channel cylindrical nanowire (NW) transistors are derived using the proposed approximation. The proposed model is physics-based and does not include any empirical parameters. The accuracy of the model is verified across NWs of different sizes and materials using the data from the 2-D PS solver and found to be accurate. [ABSTRACT FROM AUTHOR]

Electrolyte-gated field-effect transistor technology is an attractive candidate for printed low-power electronics due to its high field-effect mobility and extremely low-voltage operation. Relying on an additive process, inkjet-printed devices display large process variations due to ink-substrate interactions, sensitivity to environmental conditions, such as temperature and humidity, as well as intrinsic variations of the ink. All of these sources of variations may display themselves in non-Gaussian distributions as suggested by our experiments. In this paper, we therefore propose a generic methodology for variability modeling of printed transistors, based on the Gaussian mixture model, which can be used to model any arbitrary distribution of the transistor model parameters. The proposed methodology was tested on two different data sets and has been used to predict the behavior of a measured printed security circuit as well as transistor dc characteristics. [ABSTRACT FROM AUTHOR]

In this paper, we describe an improved SPICE model for the negative capacitance field-effect transistor (NCFET). According to the law of conservation of charge, the model is built based on the relationship between the gate charge of the MOSFET and the charge reserved by the ferroelectric layer and includes the parasitic resistance and capacitance into consideration. Based on the model, the drain-induced barrier lowering (DIBL) and the negative resistance (NR) of the NCFET are analyzed. Finally, taking two well-known analog blocks (the current mirror and the latch comparator) for example, impacts of the DIBL effect and the NR property on analog circuit performances are discussed. Thanks to utilization of the NR feature, not only can impacts of the DIBL effect and the channel-length modulation (CLM) effect be alleviated to improve the mirroring accuracy, but also the comparison speed of the latch comparator be accelerated. [ABSTRACT FROM AUTHOR]

Gate-commutated thyristors (GCTs) are subject to uneven impedances along the current path from GCT circles to the gate contact, which leads to current redistribution between the GCT circles during turn-off. The current redistribution inequality significantly limits the maximum controllable current of GCTs. This paper presents an optimization method for GCT cell arrangement design to minimize the current redistribution inequality. First, the whole GCT wafer model is applied to calculate the inequality of the current redistribution. The whole GCT wafer model is a hybrid model built by physics-based GCT cell models connected with lumped parameter models. The GCT cell models applied here are improved compact models with multiple physical mechanisms, while the lumped parameter models represent the uneven impedances of the GCT circles along the GCT wafer. In order to measure those impedances, a set of physical concentric contact rings are developed. Finally, the Tabu search (TS), a heuristic algorithm, is applied to optimize the GCT cell arrangement. Using the optimization method based on TS, an optimized set of GCT cell numbers for a 4-in GCT wafer is obtained, reducing the inequality of the current redistribution by 20%. [ABSTRACT FROM AUTHOR]

An analytical surface-potential-based drain current model of dynamic-depletion (DD) polysilicon (poly-Si) thin-film transistors (TFTs) is proposed in this paper. In the 1-D Poisson equation, total charge density is reformulated by an effective charge density, which allows a closed-form surface potential calculation scheme. Different boundary conditions between partial depletion and full depletion are calculated and unified into one back-gate potential in the DD mode, which allows a unified-form surface potential calculation scheme. Combining with Gauss’s theory, we explicitly solve a closed- and unified-form surface potential of DD poly-Si TFTs. Based on the solution of the surface potential, the drain current is derived analytically from the Pao–Sah integration. Furthermore, our solution is verified by numerical results and experimental data, respectively. As a result, such a model can accurately predict I–V characteristics of DD poly-Si TFTs and provide computational efficiency for TFT process optimization and circuit simulations. [ABSTRACT FROM AUTHOR]

The accurate calculation of switching voltage (${V}_{s}$) is necessary for the reliable and low-power operation of monolithic 3-D (M3D) CMOS-nanoelectromechanical (NEM) hybrid reconfigurable logic circuits because ${V}_{s}$ corresponds to the operating voltage (${V}_{\text {dd}}$) of NEM memory switches. In this paper, based on the Euler–Bernoulli equation, the physics-based analytical model is proposed to determine ${V}_{s}$. The accuracy of the proposed model is verified by both the finite-element analysis and experimental results. Our proposed model shows >3% error compared with experimental data. Also, the design guidelines of NEM memory switches are presented in terms of minimum ${V}_{s}$ (${V}_{s\_{}{m}}$) and device dimensions. [ABSTRACT FROM AUTHOR]

This paper presents a generalization of the charge-based model for ultrathin junctionless double-gate (JLDG) field-effect transistors (FETs) by including quantum electron density. The analytical derivation relies on a first-order correction to the infinite quantum well. When restricting the analysis to the first and second quantized states, the free carrier charge distribution and the current in an ultrathin body JLDG FETs are in agreement with numerical TCAD simulations in all the regions of operation, i.e., from deep depletion to accumulation and from linear to saturation. [ABSTRACT FROM AUTHOR]

In this paper, a new model is successfully introduced to describe an ion-sensitive field-effect transistor in a TCAD tool. To model this device accurately, the model should evaluate surface charge density behavior of electrolyte and insulator interface as well as ion concentration according to different pH values. Performance and accuracy of the model have been examined through assessing parameters such as sensitivity and signal-to-noise ratio (SNR). The effect of silicon active layer thickness on the sensitivity and SNR and its maximum condition and relevance to silicon thickness are investigated. Results show that the model can predict the device responses accurately, in accordance with experimental reports. The proposed model reveals that although the top oxide to buried oxide capacitance ratio does not change the SNR; the silicon active layer thickness can affect it efficiently. [ABSTRACT FROM AUTHOR]

This paper compares two different analytic solutions to the 2-D potential in double-gate MOSFETs in subthreshold: Green’s function method and scale length model. Both models produce closed-form potential functions for every point in Si based on rigorous approaches to Poisson’s equation with boundary conditions. It is shown that despite the vastly different mathematical equations, the ${I}_{\textsf {ds}}$ – ${V}_{\textsf {gs}}$ characteristics generated from each model are completely consistent with each other and with Technology Computer Aided Design (TCAD). Testing examples include undoped and highly doped cases of both polarities, junction and junctionless. Also included is a case of severe short-channel effects. [ABSTRACT FROM AUTHOR]

In spite of the reporting of several mathematical approaches dealing with the behavior of the superjunction MOSFET’s specific resistance, a study for the asymmetrical pillar (when the width of the n-pillar and the p-pillar are not the same at a given cellpitch) has not been carried out yet. When the width of one of the pillar (say n-pillar) is modified, the doping concentration (say donor) should be changed to maintain a charge balance condition. This in turn, changes the width of the depletion region, due to the parasitic JFET effect and as a result the effective on-state conduction path. This raises the question whether the best tradeoff between the specific on-state resistance and the breakdown voltage could be achieved by employing the conventional assumption of the same width of the n and p pillars. This paper clarifies the best option for the width of each pillar when designing a superjunction MOSFET and adapts the figures of merit to take into account the asymmetrical superjunction cell. [ABSTRACT FROM AUTHOR]

This paper presents the quantum analytical model, based on the self-consistent solution of 1-D Schrödinger equation and 2-D Poisson’s equation for the ultrascaled dual-material double-gate (DMDG) silicon-on-nothing MOSFET structure. The quantum mechanical effects (QMEs) have been incorporated in our model to derive the analytical current expressions for the first time ever. Extensive calculations have been carried out to analyze the QMEs on such device performance parameters, like electric field, transconductance, drain conductance, and voltage gain. A comparative analysis based on the drain current has been presented in this paper for the classical and for the quantum model. The authenticity of our proposed quantum model for the DMDG structure is verified by the agreement among the results obtained from the analytical model as well as simulations. [ABSTRACT FROM AUTHOR]

With shrinking transistor dimensions into sub-50-nm regime, statistical variability (SV) causes a great impact on the drain current and threshold voltage of nano-MOSFETs. In this paper, with emphasis on the propagation delay time of an inverter in 35-nm technology node, we have first introduced a strategy to take SV into account in four existing compact models using different number of statistical sets. For each model under study, we identified effective parameters of analytical equations which can be utilized to replicate the impact of SV. Moreover, we analyzed the statistical distribution and correlation of those effective parameters and their impact on the propagation delay time in each model. The results of these statistical CMs are compared with the accurate “atomistic” model, and it is shown that using this approach we can predict the propagation delay time standard deviation with less than 0.2%, 4.1%, 4.8%, and 4.7% errors in different models. However, the mean values of the propagation delay time stay almost constant even by employing statistical sets of single parameters. Furthermore, we study the impact of changing the load capacitance and the supply voltage on the statistical behavior of four models in the presence of SV. [ABSTRACT FROM AUTHOR]

This paper presents an effective current model ( ${I}_{\textsf {eff}}$ ) for a near-threshold voltage (NTV) inverter and two-input NAND/NOR gates. The proposed model is validated by 2-D technology computer-aided design mixed-mode device simulations and HSPICE simulations at two different technology nodes. When compared with our model, the existing nominal supply voltage ${I}_{\textsf {eff}}$ models fail to estimate an inverter/NAND/NOR gate performance in the NTV regime. The proposed model is also validated for process, voltage, and temperature variations. Performance variation due to layout-dependent effects (LDEs) and inverse narrow width effect (INWE) are significant in the NTV regime. Therefore, the model is validated while considering LDEs. We show that due to LDEs and INWE, the value of ${I}_{\textsf {eff}}$ per unit width is a function of the device width and the number of fingers. To account for this effect, a systematic methodology is presented to optimize a circuit performance in the NTV domain. An inverter chain with ${C}_{\textsf {out}}/{C}_{\textsf {in}}=\textsf {2000}$ designed employing our methodology results in 3.2%, 35%, and 30% improvement in the delay, energy per operation, and total transistor width, respectively, as compared with existing methodologies. Similarly, data paths resized using the proposed methodology result in a significant performance improvement when compared with their conventionally designed counterparts. [ABSTRACT FROM AUTHOR]

The analysis of retention characteristics is essential for reliability assessment of any type of flash memory. A high-k (HK) material in the Interpoly dielectric (IPD) stack is known to improve the program-erase characteristics and makes the control oxide thicker for better retention time; however, it also brings-in defects along with it, creating undesirable charge loss path that plays a significant role in retention. Accurate modeling of this leakage process is important for optimizing the architecture that is less prone to oxide defects and exhibiting improved charge retention. In this paper, we present a physical model considering all possible charge leakage mechanisms that include inelastic tunneling through multiple traps in addition to direct tunneling (DT). The trap capture process is modeled as an inelastic process from nanocrystal (NC) to trap state, while the trap-to-trap tunneling is calculated by Bardeen's Transfer Hamiltonian approach. The trap emission process and DT from the spherical NC are modeled by computing the lifetime of quasi-bound states with very small decay widths in the finite-element setup. We show that a single trap model in HK cannot explain the retention characteristics. We propose a new asymmetric IPD structure that show significant improvement in retention time. [ABSTRACT FROM AUTHOR]

This paper proposes a novel kinetic velocity model (KVM) for the drift-diffusion (DD) transport approach to describe ballistic effects. It also presents a simulation study of the ballistic effect in short-channel InGaAs and silicon FETs. Monte Carlo and subband Boltzmann transport equation results as well as DD simulations using the simple gate length-dependent ballistic mobility proposed in the literature and the KVM model are compared and discussed. Basic concepts, such as the Matthiessen rule and Fermi-Dirac statistics, are analyzed with a view on ballistic transport in devices in the linear and saturation regimes. [ABSTRACT FROM AUTHOR]

This paper presents a compact analytical I – V model for short-channel double-gate transition metal dichalcogenide filed-effect transistors in the subthreshold region. A closed-form expression is proposed for the characteristic length in the scale length approach, which is based on physical device parameters. It is then used to find the channel potential and drain current in the subthreshold region. This model is verified with the numerical results of a nonequilibrium Green’s function (NEGF) simulator. There is good agreement between the results of the proposed model and the numerical NEGF simulations in the subthreshold region, while it captures the effects of the device’s physical parameters. [ABSTRACT FROM PUBLISHER]

Flexibleelectronics based on thin-film transistors (TFTs) are promising in the area of Internet of Things and wearable devices, where the pseudo-CMOS logic is widely used in the unipolar TFT circuits. Though plenty of device models exist, analytical circuit-level models are still absent, preventing the further development of design and analysis of flexible TFT circuits. In this paper, we derive the noise margin (NM), delay, and power models for pseudo-CMOS logic circuits. Furthermore, we simplify thosemodels formanual analysis and design optimization. Allmodels are validated by SPICE simulations, where the device model and its parameters are extracted from the fabricated self-assembled monolayer organic TFTs. The average errors for NM, delay, and power models are 3%, 10%, and 3%, respectively. In addition, we exploit the delay models in a voltage-controlled oscillator design and its linearity of frequency characteristic is optimized with the proposed models, demonstrating their effectiveness. [ABSTRACT FROM PUBLISHER]

A physics-based compact model for double-gate polysilicon thin-film transistors (TFTs) with a doped channel is proposed in this paper. Through the effective charge density approach, the electrostatic potential is solved explicitly from the Poisson’s equation without using the conventional regional approach. The resulting single-piece electrostatic potential equation, which does not consist of the intermediate parameter, offers clear physics meaning and good accuracy, particular when the TFT operates in the transition region. The TFT’s drain current model is then developed by integrating the electrostatic potential equation analytically with the Pao-Sah equation. Finally, the model is verified by numerical and experimental data. Such a compact model is highly suitable for circuit simulations. [ABSTRACT FROM PUBLISHER]

The field of flexible electronics is rapidly evolving. The ultrathin chips are being used to address the high-performance requirements of many applications. However, simulation and prediction of changes in response of device/circuit due to bending induced stress remains a challenge as of lack of suitable compact models. This makes circuit designing for bendable electronics a difficult task. This paper presents advances in this direction, through compressive and tensile stress studies on transistors and simple circuits such as inverters with different channel lengths and orientations of transistors on ultrathin chips. Different designs of devices and circuits in a standard CMOS 0.18- \mu \textm technology were fabricated in two separated chips. The two fabricated chips were thinned down to 20~\mu \textm using standard dicing-before-grinding technique steps followed by post-CMOS processing to obtain sufficient bendability (20-mm bending radius, or 0.05% nominal strain). Electrical characterization was performed by packaging the thinned chip on a flexible substrate. Experimental results show change of carrier mobilities in respective transistors, and switching threshold voltage of the inverters during different bending conditions (maximum percentage change of 2% for compressive and 4% for tensile stress). To simulate these changes, a compact model, which is a combination of mathematical equations and extracted parameters from BSIM4, has been developed in Verilog-A and compiled into Cadence Virtuoso environment. The proposed model predicts the mobility variations and threshold voltage in compressive and tensile bending stress conditions and orientations, and shows an agreement with the experimental measurements (1% for compressive and 0.6% for tensile stress mismatch). [ABSTRACT FROM PUBLISHER]

In this paper, thermal stability and phonon transport of 22-nm fully depleted silicon on insulator (FD-SOI) MOSFET is investigated. On the one hand, we havedemonstrated that the single-phase-lag(SPL) model is able to predict the phonon transport in 22-nm FD-SOI MOSFET. On the other hand, we have investigated the role of the spacer between source, drain, (S/D) and gate of the MOS transistor for the increasing of the temperature. An electrothermal model based on nonlinear SPL equation coupled with an electric model has been investigated. To solve the proposed model, we have performed a numerical study based on the finite element method. The proposed model has been validated on the basis of available results. We found that the present model is able to predict the phonons and electrons transport in nano FD-SOI-MOSFET compared with the DPL model. In a technological viewpoint, we found that the distance between S/D and gate has an important role for the increasing of the temperature. [ABSTRACT FROM AUTHOR]

In this paper, we present a compact model for surface potential and drain current in transition metal dichalcogenide (TMD) channel material-based n-type and p-type FETs. The model considers 2-D density of states and Fermi–Dirac statistics along with drift-diffusion transport model and includes velocity saturation and trap state effects. The developed model has been implemented in Verilog-A and is applicable for symmetric double gate as well as top-gated TMD-on-insulator FETs. The presented model is extensively validated with simulation as well as experimental data for different TMD materials-based FETs and shows excellent agreement with both the simulation and the experimental data. We further validate the model at circuit level using experimental data of MoS2 FET-based inverter. [ABSTRACT FROM AUTHOR]

This paper presents an analytical model of drain current in a silicon tunnel FET with a circular gate (CG TFET). The method involves the bifurcation of the complete geometry into a rectangular gate conventional TFET, and the CG TFET itself based on the number of solvable regions of the CG TFET. The 2-D Poisson equation is solved on the regions of focus of each structure, and both the substructures are mathematically connected through conditions of continuity to arrive at the solution for the original geometry. The effect of the circular gate is considered by segregating the circular region into a number of rectangular segments, and solving the Poisson equation on each of them. The model takes into account the effect of drain on channel potential, bandgap narrowing, and quantum correction. The model is validated by comparing the results with outputs from a TCAD simulation tool. [ABSTRACT FROM PUBLISHER]

In this paper, we have proposed a new analytical model for FETs working in the quasi-ballistic regime. The model is based on a calculation of the charge density along the channel which is then used to solve Poisson’s equation to get the variation of the channel potential. This is then used to calculate the ballistic and drift-diffusive components of the current. The model is capable of accurately predicting the terminal $I$ – $V$ characteristics for all drain and gate biases and includes short-channel effects. It takes length scaling into account and can be used for the full range of devices starting from complete drift diffusive to completely ballistic. The model has been verified with data for high electron mobility transistors (degenerate) and common multigate and nanowire FETs (nondegenerate) proving its ability to take different geometries into consideration. It can be easily implemented as a compact model and used for SPICE circuit simulations. [ABSTRACT FROM AUTHOR]

A computationally efficient analytical model to accurately predict the electrical characteristics of wrap-gate carbon nanotube FETs (CNTFETs) is proposed and described in this paper. A wrap-gate structure offers an ideal geometry with minimum body thickness and maximum control over the channel as well as improved device scalability. The parasitic effects present in a real device are incorporated into an ideal wrap-gate device model, and the Poisson–Schrödinger equations are solved self-consistently to obtain the potential and carrier density at the top of the barrier. Exact analytical expressions, such as CNTFET density-of-states are used for approximately evaluating the integral expressions. Finally, the drain current is obtained for near-ballistic transport in the device. The electrical characteristics from our model are validated with recently reported experimental results from the literature, demonstrating good accuracy when the device is on. The subthreshold characteristics are underestimated and offer scope for improvement. Various performance metrics, including threshold voltage and subthreshold swing, and on-current are within 2–11% error. The proposed model can thus be used to study the performance of wrap-gate CNTFETs under various parametric conditions, and extended to circuit simulation models, such as SPICE. [ABSTRACT FROM PUBLISHER]

This paper demonstrates that collector current ( IC ), dc current gain ( \beta ), cutoff frequency ( f_{T} ), and maximum oscillation frequency ( f_{\max } ) of bipolar transistors (BJTs) can be improved by uniaxial stress. A unified modeling approach that includes a piezoresistive model for changes in mobility and a deformation potential model for changes in intrinsic carrier concentration was used to analyze the stress effects. This approach provides clear insight into the dominant effects of stress on BJT parameters. Experimental results of uniaxial in-plane normal stress are compared with simulation results. Our analysis reveals that for a vertical npn, substantial enhancement in \beta , f_{T} and f_{\max } can be achieved using a uniaxial in-plane compressive or out-of-plane tensile stress. In a vertical pnp, considerable improvement in \beta , f_{T} , and f_{\max }$ are minimal. These results show that stress analysis/prediction for different current-stress orientations can be performed with this model and the outcome can be used as a guide for strain engineering in BJTs. [ABSTRACT FROM PUBLISHER]

In this paper, we have developed a model for the surface potential and the drain current of a dual-material double-gate (DMDG) junctionless FET (JLFET) transistor. A finite-differentiation method has been used to decompose the 2-D Poisson’s equation into two 1-D equations, which allows the modeling of the DMDG structure as two individual single-material double-gate JLFETs. The two 1-D models are then combined using appropriate boundary conditions to provide a simple solution to the complex 2-D Poisson’s equation. The proposed model has been verified for different values of doping concentration ( ND ), oxide thickness ( T\mathrm{ ox} ), and channel thickness ( T\mathrm{ si} ) against the numerical simulations. [ABSTRACT FROM AUTHOR]

This paper presents an analytic $I$ – $V$ model for short-channel MOSFETs made of 2-D semiconductor material. First, a subthreshold current model is formulated based on the solutions to 2-D Poisson’s equation with negligible mobile charge. Next, a velocity saturation model is developed under the framework of a drift and diffusion long-channel model. These two models are then unified into an all region, short-channel $I$ – $V$ model with both drain induced barrier lowering and velocity saturation effects. Ballistic currents, including the intraband tunneling and the above-the-barrier transport, have been examined and compared with the thermionic currents. [ABSTRACT FROM AUTHOR]

In this paper, an analytical potential-based model in the subthreshold regime for short-channel junctionless cylindrical surrounding-gate MOSFETs is proposed as the source/drain depletion effect considered. The threshold voltage ( V\textrm {th} ), subthreshold slope, and drain-induced barrier lowering are also correspondingly derived, which give explicit explanations of the short-channel effects on junctionless MOSFETs in the subthreshold regime. The compact model is verified by the numerical simulation, and the results match well. [ABSTRACT FROM AUTHOR]

This paper presents an accurate and computationally efficient method to calculate the drain–source saturation voltage V\mathrm{ dsat} of dual-gate (i.e., four-terminal) junction field-effect transistors. The method accounts for velocity saturation and for channel thickness modulation by any combination of MOS or p-n junction gates. In three iterations, it achieves an error of less than 2%. Our algorithm converges significantly faster than the direct application of the Newton–Raphson method because of careful selection of an initial value and the leverage of the convex and concave nature of the curves whose intersection defines V\mathrm{ dsat} . The method is applied to both the exact model for I\mathrm{ ds} and an approximated form based on mid-point-potential linearization, and is verified by comparison with numerical simulation. [ABSTRACT FROM AUTHOR]

We present here and in the companion paper (Part II) a general framework for the modeling of semiconductor device variability through the physics-based analysis of the small-change sensitivity. We consider a very general class of dynamic device operation, i.e., the periodic or quasi-periodic large signal (LS) time-varying regime, and we evaluate the sensitivity of both dc and harmonic components of the device dynamic working point with respect to process or physical device parameters. The proposed technique is based on the linearization of the physics-based device model around a nominal parameter, and extends to the dynamic case the already established Green’s function approach to the numerically efficient dc sensitivity analysis. As an example of application, we consider a class A GaAs MESFET microwave power amplifier; the sensitivity of the LS working point with respect to doping and gate work function variations is evaluated through the proposed approach and compared with the result of repeated LS amplifier analyses, showing that the numerically efficient small-change sensitivity approach provides reliable predictions for parameter variations up to 10% of the nominal value. [ABSTRACT FROM PUBLISHER]

A compact model for the single-poly multitime programmable (MTP) memory cells is presented in this paper for the first time. It is based on the charge balance approach, while the traditional old model is on the fixed capacitive coupling approach. The proposed cell model has been implemented by Verilog-A and integrated into commercial SPICE simulator. The model supports both dc and transient analyses, and the simulated results are consistent very well with those from device simulation and measurement, whereas the results by the traditional old model deviate substantially. Furthermore, the comprehensive optimization of the MTP cells is made feasible thanks to the new model, such as device size, high voltage ramp rate, and reliability prediction. As a result, this compact cell model will be very useful for the designers to evaluate and optimize a single-poly MTP cell. [ABSTRACT FROM AUTHOR]

Based on the thermionic emission theory, a charge transfer model has been developed which describes the charge transfer process between a pinned photodiode and floating diffusion (FD) node for CMOS image sensors. To simulate the model, an iterative method is used. The model shows that the charge transfer time, barrier height, and reset voltage of the FD node affect the charge transfer process. The corresponding measurement results obtained from two different test chips are presented in this paper. The model also predicts that other physical parameters, such as the capacitance of the FD node and the area of the photodiode, will affect the charge transfer. Furthermore, the model can be extended to explain the pinning voltage measurement method and the feedforward effect. [ABSTRACT FROM AUTHOR]

In this paper, we model the geometric component in a charge pumping (CP) technique of polycrystalline silicon thin-film transistors (poly-Si TFTs). This model is based on both remaining carrier types when the device transits from accumulation to inversion and vice versa. Therefore, it depends on gate length ( L ) and width ( W ) as well as on gate signal rise ( t\!f ) and fall time ( t\!f ). The proposed model shows good agreement with the experimental data. We have shown that the geometric component due to the remaining carriers, when poly-Si TFT transits from inversion to accumulation, is very small compared with that due to the transition from accumulation to inversion. Consequently, a new analytic CP model, depending on gate width, is developed for n-channel poly-Si TFT. [ABSTRACT FROM PUBLISHER]

A detailed presentation of the latest version of Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of ultrathin body and BOX fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this paper, compact modeling of intrinsic currents and charges, including all physical effects required to describe decananometer transistors, is detailed. This model is valid for all independent double-gate architectures, very accurate and feature excellent predictability over technological parameters. [ABSTRACT FROM AUTHOR]

In this paper, a compact fractional-order equivalent circuit model is developed to characterize three types of metamaterial transmission lines (T-lines): 1) composite right-/left-handed transmission line T-line; 2) split ring resonator T-line; and 3) complimentary split ring resonator T-line, all designed in 65-nm CMOS process at millimeter-wave frequency region. With the consideration of frequency-dependent dispersion loss and nonquasistatic effect, the proposed fractional-order equivalent circuit model can compactly characterize the measured results with good agreement up to 325 GHz. [ABSTRACT FROM AUTHOR]

The purpose of this paper is to characterize and model the self-heating effect (SHE) of multifinger n-channel MOSFETs (nMOSFETs). The amount of SHE is small enough not to be analyzed for single-finger bulk CMOS devices. However, SHE should be considered for multifinger nMOSFETs that are mainly used for RF-CMOS applications. The SHE mechanism was analyzed based on a 2-D device simulator. SHE model equations are derived and implemented in the BSIM6 model with Verilog-A language used in a SPICE simulator. The model improves speed and accuracy of multifinger nMOSFETs simulations. To extract thermal resistance and capacitance, an advanced ac conductance method using a vector network analyzer is developed to obtain $I_{{\textrm {ds}}}$ – $V_{{\textrm {ds}}}$ measurement without increasing temperatures with the proposed model and extracted parameters, excellent agreement has been obtained between measurements and simulations in dc and S-parameter domain, whereas the original BSIM6 shows inconsistency between the static dc and the small signal ac simulations due to the lack of SHE. Unlike the widely used subcircuits-based SHE models, including Silicon-On-Insulator MOSFET and power MOSFET models, the proposed SHE model can converge in large-scale circuits even for transient simulations. [ABSTRACT FROM AUTHOR]

This paper investigates the heat transfer and temperature distribution as well as electric fields in a 10-nm MOSFET and insulator region silicon-on-insulator MOSFET (IR-SOI-MOSFET). An electrothermal model based on a dual-phase-lag model coupled with a second-order temperature-jump boundary condition and drift–diffusion (D-D) model has been elaborated. The D-D model is used to take into account that the heat source by Joule effect and the width of the channel depends on the electrical fields. The finite-element method has been employed to generate the numerical results. The model has been validated on the basis of available numerical results. It is found that once the Fourier law ceases to be valid, our model is able to predict the phonon transport and electrical properties in nanostructures. In a technological viewpoint, the IR-SOI-MOSFET is more thermally efficient compared with a classical SOI-MOSFET. [ABSTRACT FROM AUTHOR]