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Resistive random access memory (ReRAM) is often considered as a strong candidate for storing the weights in non-von Neumann neuromorphic computing systems. This paper studies how nonideal memory characteristics, which include programing error, read fluctuation, and retention, affect the inference accuracy of the analog ReRAM neural networks by incorporating memory characteristics extracted from 1-Mb ReRAM into a simulated inference-only neural network. This paper also shows that the different layer in the network can tolerate different amount of such imperfects. We learned four key points: 1) the conductance range of memory with less relative fluctuation is preferred for designing the weight-conductance mapping; 2) the control of programing error is essential for high inference accuracy; 3) retention-induced conductance drift can be fatal to the neuromorphic system. A compensation scheme is proposed in this paper which can effectively recover the inference accuracy; and 4) for multilayer networks, avoiding weight errors in the front layers can help to maintain the inference accuracy by reducing calculation error which may otherwise accumulate and pass down the networks. The concepts and approaches of this paper can also be applied to evaluate other types of nonvolatile memories for artificial neural networks. [ABSTRACT FROM AUTHOR]

The introduction of metal nanocrystals (NCs) has been confirmed to improve electrical uniformity of oxide-based resistive random access memory (RRAM) devices significantly; however, the current reports do not systematically elucidate the relationship between the size/distribution of NCs and the electrical uniformity of RRAM devices. In this paper, we focused on the impact of metal NCs size and areal density on the resistive switching (RS) performances of oxide RRAM by atomic layer deposition (ALD) based on the experimental results and theoretical calculation. The dependence of ALD cycles of 50–130 during Pt or CoPtx NCs growth on the RS parameters of Al2O3 or HfO2 memory units has been evaluated systematically. The RRAM embedded Pt or CoPtx NCs shows the trends: with increasing ALD cycles, the forming voltage, set/reset voltage, the resistance in off and on state, and ${R}_{ \mathrm{\scriptscriptstyle OFF}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ratio entirely first decrease, then flatten, and increase later with a minimum value at about 100 cycles. Although all metal NCs with various sizes enhance the electric field strength compared to at the planar region, only metal NCs with proper NCs size and areal density (9 nm/6– $10\times 10^{\textsf {11}}$ /cm2 in this paper) can effectively produce stronger localized electric field at the tip of metal NCs, leading to optimal RS behavior. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate a tunable Schottky diode based on amorphous indium–gallium–zinc–oxide (a-IGZO) film with high performance for rectifying circuit and bipolar one diode-one resistor (1D1R) crossbar applications. By modulating the oxygen content in the a-IGZO film, the device shows adjustable behavior. Under the high oxygen content condition, the device displays outstanding diode features with a large rectification ratio up to 108 at ±1 V and a high forward current density of 100 A/cm2 at ±1 V when used Cu as the top electrode. The thermionic emission model is proposed to explain the Schottky diode behavior. And by utilizing the superior rectifying performance, we successfully demonstrate the dynamic rectifying application. In addition, we combine the optimized Schottky diode device with the bipolar-type resistive random access memory (RRAM) device to investigate the Schottky diode device in 1D1R crossbar application. As a result of its tunable nature and low processing temperature, the a-IGZO Schottky diode is a promising element for rectifying circuit and bipolar 1D1R crossbar applications. [ABSTRACT FROM AUTHOR]

In this paper, the transition rate (TR) from the high-resistance state to the low-resistance state of a HfO2-based resistive random access memory (RRAM) is investigated. The TR is statistically characterized by applying constant voltage stresses in the range from 0.45 to 0.65 V. It is found that TR follows a voltage dependence which closely resembles the one exhibited by metal-insulator-semiconductor / metal-insulator-metal structures when subjected to constant voltage stress, but with remarkably different fitting parameters. This result suggests a common underlying mechanism in both evolutionary behaviors. Furthermore, the investigation provides additional evidence supporting the micro-structural changes in the oxide after the forming step as well as the role played by the atomic species during the SET event. [ABSTRACT FROM AUTHOR]

Recently, 2-D cross-point array of resistive random access memory (RRAM) has been proposed for implementing the weighted sum and weight update operations to accelerate the neuro-inspired learning algorithms on chip. This paper aims to extend such 2-D cross-point array to 3-D vertical array for storing and computing the large-scale weight matrices in the neural network. Considering the fabrication and 3-D integration of analog synapses (i.e., multilevel RRAM devices) are premature at this stage, we propose using today’s available digital or binary RRAM devices for implementing a ternary neural network, which aggressively reduces the weight precision to ternary levels (+1, 0,−1) for the weighted sum in both feedforward and backward inference, while the multiple 3-D layers could serve for accumulating the small errors in a higher precision format for weight update. Compared to the 2-D implementation, the proposed 3-D vertical implementation shows larger read/write margin for weighted sum/weight update, smaller latency, and energy consumption for weight update. This paper demonstrates the attractiveness for building a monolithic 3-D neuromorphic hardware platform. [ABSTRACT FROM PUBLISHER]

This paper addresses the design challenges of simulating the 3-D vertical-resistive random access memory (V-RRAM) toward MB-level. The interconnect IR drop and sneak paths are known to be the limiting factors for building large-scale V-RRAM arrays. The previous approach to evaluate the write/read margin of V-RRAM was based on the exhaustive SPICE simulations, which prohibits the design exploration to MB-level as it takes huge amount of computation resources. In this paper, a quasi-analytical model is proposed, which aims to reduce the simulation time and the required memory usage. Through the validation with the SPICE simulation results, the proposed model shows a similar accuracy. Based on the proposed quasi-analytical model, the worst case data pattern of 3-D V-RRAM with large array size up to 4 MB is analyzed. The results show that it is more efficient to increase the number of stack layers than expanding the horizontal array size to achieve large subarray size. [ABSTRACT FROM AUTHOR]

This paper investigates material modifications induced by cosputtering indium-tin oxide (ITO) with gadolinium (Gd) at two different power levels. In addition, resistance switching (RS) properties were also verified for use as an insulator in resistive random access memory (RRAM). Comparison of scanning electron microscope (SEM) measurements for the two different cosputtering powers indicated significant changes of the ITO surface. Transparency was also verified by an N&K analyzer measurement, with results indicating a constant in transparency induced by the lower power Gd doping, indicating potential for transparent applications. Furthermore, the mole fraction ratio defined by X-ray photoelectron spectroscopy reveals a Gd2O3 peak, a likely reason for the ITO thin film becoming less conductive. This ITO/Gd:ITO/TiN RRAM can exhibit stable and robust RS characteristics at a lower forming voltage. In addition, lower operating voltages, including both SET and RESET voltages, can be obtained. Reliability tests including endurance and retention were carried out to confirm its RS stability. The RS mechanism of this ITO/Gd:ITO/TiN device was also investigated with the current–voltage (${I}$ – ${V}$) fitting method. Moreover, temperature effects were also applied to verify the high-resistance state (HRS) mechanism. Finally, a conduction model was proposed to clarify the RS characteristics and confirm that the ITO/Gd:ITO/TiN device is appropriate for data storage. [ABSTRACT FROM AUTHOR]

This paper investigates the issues of oxygen accumulation and variation in the high-resistance state of HfO2-based resistive random access memory (RRAM), with improvement attained by inserting a thin oxygen-vacancy-rich layer of indium-tin-oxide (ITO) film. By acting as the oxygen ion reservoir, this ITO thin film on the TiN electrode can further stabilize resistance switching (RS) characteristics. In terms of reliability, ac endurance, and retention tests confirm stable RS characteristics for the Pt/HfO2/ITO/TiN device. Finally, a conducting model was proposed to explain the influence of the ITO thin layer and clarify the physical mechanism of electrical improvements. [ABSTRACT FROM AUTHOR]

Resistive random access memory (ReRAM), a new emerging nonvolatile memory technology based on changes in electrical resistivity of a dielectric film, offers promising advantages such as scalability, fast switching, and low operation voltage. However, for ReRAM to become a successful technology, it is necessary to accurately control the stochastic nature of the conductive nanoscale filaments (CNFs) that governs the resistive switching (RS) behavior of the device and limits its long-term stability and reliability. In this paper, we developed a highly scalable nanostructured/textured electrode that is composed of an array of Al nanotips based on an anodic aluminum oxide template. The nanotips improve the RS characteristics by intensifying the electric field at the apex of each nanotip which is demonstrated using numerical simulations. The localized electric field induces the repetitive nucleation/ formation/rupture of the CNFs in a more controlled fashion compared to a flat Al electrode. As a result, the nanotip sample exhibits uniform and reduced forming/reset voltages as low as 4.70 ± 0.98V/1.00 ± 0.19 V, stable endurance, and long-term retention. As a result, we were able to achieve ultralow-power and error-free operation of 100 cells covering a large area, significantly demonstrating improved uniformity and reliability compared to devices made using flat Al electrodes. This universal bottom-up strategy of self-organized nanostructured-electrodes provides a pathway toward large-scale, highly reliable, and RS memory devices. [ABSTRACT FROM AUTHOR]

In the study of resistive random access memory using GeTeOx film as the switching layer, the device performed excellent property of bipolar resistive switching (BRS), which could be gradually transformed to the complementary resistive switching (CRS) by varying SET process current compliance. The conductive filament conduction mechanism of BRS could be verified by electrical characteristics and reliable data fitting. Through increasing current compliance of the SET process, CRS could be achieved due to higher activity of oxygen vacancies originated from the intensified thermal effect. This paper was beneficial to understand the switching mechanisms of BRS and CRS and provide a method to realize interconversion. Moreover, it was also a potential and promising device to be applied in the neurosynaptic biomimetic field. [ABSTRACT FROM AUTHOR]

In this paper, the read margin (RM) and write power (WP) of 3-D vertical resistive random access memory (VRRAM) are analyzed by considering the variation in RRAM cell (self-rectifying cell) characteristics. To demonstrate the cell variation effect on a large 3-D VRRAM array, we develop a modified lumping method in HSPICE simulator and show that this method substantially reduces the computation time while maintaining high accuracy. Read and write performances including cell variation are investigated according to various array sizes and RRAM characteristics. A large distribution of cell current reduces the RM but hardly affects the WP. Moreover, in 3-D VRRAM with a small number of wordline (WL) layers, a large on/off ratio (RHRS/RLRS) is advantageous for improving the RM and reducing the variation effect. In contrast, a large on/off ratio has little effect on the RM in 3-D VRRAM with many WL layers. This difference occurs because the increased leakage induced in the half-selected cells mainly affects the RM, and the half-selected cells are located in the selected vertical pillar in 3-D VRRAM. [ABSTRACT FROM AUTHOR]

An intentionally introduced interface layer in the resistive random-access memory (RRAM) devices play an important role in the improvement of resistive switching characteristics. In this paper, the resistive switching characteristics of ZrO2-based RRAM devices by inserting a thin TiO2 interface layer between electrodes and ZrO2 resistive switching layer were investigated. Compared with the Cu/ZrO2/Pt and Cu/ZrO2/TiO2/Pt devices, the Cu/TiO2/ZrO2/Pt and Cu/TiO2/ZrO2/TiO2/Pt devices showed much improved programing voltages, including lower forming voltage and lower set voltage. Moreover, the reset current was also improved. These results indicate that the TiO2 interface layer between the anode electrode and the resistive switching layer plays an important role in improving device performance. [ABSTRACT FROM AUTHOR]

The switching properties of Te and TeTiW top electrodes (TEs) on TiW/SiN/TiN resistive switching memory devices are explored in this paper. The TeTiW TE device exhibits more favorable bipolar resistive switching behavior because of the decrease in binding energy after its use. This finding is confirmed through X-ray photoelectron spectroscopy analyses. The filament of the TeTiW TE device is metal like after forming, and the reset process corresponds with the thermal-dissolution mechanism. A physical model based on a Te filament is constructed to explain such phenomena. The TeTiW TE device provides the excellent endurance of more than 104 cycles, with an ON/OFF ratio of 500. The improvement can be attributed to the filament’s robustness during the forming and set processes, which prevent its diffusion even at high temperature. The device also features long retention for up to 104 s at 225 °C without stress, and 104 s at 85 °C with stress of −0.3 V. Therefore, it has high potential for high-density nonvolatile memory applications. [ABSTRACT FROM AUTHOR]

In this paper, we report about the derivation of a physics-based compact model of random telegraph noise (RTN) in HfO2-based resistive random access memory (RRAM) devices. Starting from the physics of charge transport, which is different in the high resistive states and low resistive states, we explore the mechanisms responsible for RTN exploiting a hybrid approach, based on self-consistent physics simulations and geometrical simplifications. Then, we develop a simple yet effective physics-based compact model of RTN valid in both states, which can be steadily integrated in state-of-the-art RRAM compact models. The RTN compact model predictions are validated by comparison with both a large experimental data set obtained by measuring RRAM devices in different conditions, and data reported in the literature. In addition, we show how the model enables advanced circuit simulations by exploring three different circuits for memory, security, and logic applications. [ABSTRACT FROM AUTHOR]

Resistive random access memory is known as a type of nonvolatile memory. An abnormal volatile memory characteristic of a normal ZnSnO resistive memory is first demonstrated in this paper. Although the ${I}$ – ${V}$ curves exhibit a normal and stable resistive switching memory behavior, the resistance state is found to be only determined by the initial applied voltage along with the voltage sweep direction. It is set/reset processes free. Namely, it is volatile. The resistance states are found to be dominated by trap-assisted tunneling, trap-controlled space-charge-limited conduction, and hopping transport. Different resistance states are related to different carrier transport mechanisms. Each resistance state can independently and repeatably appear for over 1000 voltage sweeps. The ratio of the high-resistance state to the low-resistance state is $\sim 3\times 10^{2}$. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) is among the most mature technologies for next generation storage class memory with low power, high density, and improved performance. The biggest challenge toward industrialization of RRAM is the large variability and noise issues, causing distribution broadening which affects retention even at room temperature. Noise and variability can be addressed by enlarging the resistance window between low-resistance state and high-resistance state, which requires a proper engineering of device materials and electrodes. This paper presents an RRAM device technology based on silicon oxide (SiOx), showing high resistance window thanks to the high bandgap in the silicon oxide. Endurance, retention, and variability show excellent performance, thus supporting SiOx as a strong active material for developing future generation RRAMs. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the link between various resistive memory (RRAM) electrical characteristics: endurance, window margin (WM), and retention. For this purpose, several RRAMs are characterized using various resistive layers and bottom electrodes. By focusing on one technology and optimizing programming conditions (current, voltage, and time), we establish a tradeoff between endurance and WM. Then, by changing memory stack, we demonstrate the correlation between endurance plus window marging improvement and retention degradation. Studying this last feature from a material point of view, we analyze different oxides by density functional theory. We realize a systematic review for possible exchanges of species between resistive layer and Cu-based top electrode and study their diffusion. This provides insights on conductive filament composition in different stacks. Combining previous experiments and simulations, we propose a link between memory characteristics and material microscopic parameters, through the ion energy migration barrier. Finally, we extract how endurance, WM, and retention are correlated to material properties and electrical parameters in order to choose the suitable material for a defined application using the RRAM technology. [ABSTRACT FROM AUTHOR]

A versatile multiphysics simulation packet for investigating different resistive random acces memories (RRAMs) is developed in this paper. Heat transfer, electrical conduction, and ion migration in such heterogeneous structure are all taken into consideration. Three fully coupled partial differential equations are solved using our self-developed finite-difference algorithm, where Scharfetter–Gummel method is adopted to simulate ion migration with fast convergence achieved. This packet is validated in comparison with the commercial software based on the finite-element method. With its implementation, complete and clear pictures for crosstalk effect in vertically integrated RRAM are captured and compared, where the effects of key physical and geometrical factors are characterized and understood. Some useful suggestions to mitigate its unfavorable influences are given. [ABSTRACT FROM PUBLISHER]

This paper investigated the performance of flexible resistive random access memory devices based on simple spin-coated sol–gel-derived strontium titanate nickelate (STN) thin films on polyethylene terephthalate substrate. A high on/off ratio of 10^5 and a uniform current distribution were demonstrated. The strong bonding between bidentate ligands of nickel (II) acetylacetone and titanium metal ion enabled the chelation effect, which contributed to the stability of the STN thin film, especially for moisture resistivity. Fourier transform infrared spectroscopy analysis was utilized to examine the effects on the resistive switching behaviors after 90 days under an atmospheric environment according to the chelation effect of the STN thin films. The devices were fabricated on a flexible plastic substrate, and they exhibited excellent durability upon repeated bending tests. They demonstrated good potential application for flexible and low-cost memory devices. [ABSTRACT FROM PUBLISHER]

3-D integrations are unavoidable task for new emerging memories, including resistive switching random-access memory (RRAM), in order to overcome the market-leading nand flash. However, an RRAM crossbar array (CBA) suffers severe read margin degradation due to the sneak current, which becomes even more critical as the memory density increases with the 3-D integration. In this paper, we extend the two-port readout scheme for a 2-D CBA, proposed in our previous work, to the 3-D vertical structure. A closed-form expression of the operating principle is derived, and HSPICE simulation using a $32\times 32\times8$ vertical RRAM CBA considering practical circuit parameters verifies feasibility of the two-port scheme to the 3-D CBA. [ABSTRACT FROM AUTHOR]

Resistive random access memory (RRAM) is a promising candidate for next generation nonvolatile memory technology. In this paper, electrothermal simulation in 3-D RRAM arrays is performed by using our in-house developed finite difference algorithm, which is validated by comparing the simulated temperature distribution with its counterpart obtained by commercial software. Both crossbar RRAM array and vertical RRAM array are studied comprehensively with careful consideration of the temperature-dependent constitute parameters. Simulations show that the temperature and thermal crosstalk are sensitive to the size and shape of conductive filament, which can further limit the scaling potential of RRAM array through affecting its reliability, such as retention time, current leakage, and so on. Scaling behavior of 3-D RRAM array is studied, and optimization guidance for reducing thermal crosstalk is proposed. The fabrication inaccuracy resulted cell offset has also been examined for investigation of thermal crosstalk. [ABSTRACT FROM PUBLISHER]

This paper investigates the characteristics of applying indium–tin oxide (ITO) with and without nitride gas (N2) as the insulator in resistive random access memory (RRAM). After cosputtering an ITO target with N2 as the insulator and capping the same ITO material as the top electrode, the device exhibits rectifier and resistance switching characteristics before and after the forming process, respectively. The Schottky diodelike rectifier mechanism was also verified by various temperature measurements. Furthermore, robust resistance switching at a positive forming voltage, smaller than that required during negative bias forming, can be achieved. Both positive and negative forming processes are examined with current fitting results, which show different dominant mechanisms when using positive or negative biases. All these mechanisms have also been verified by temperature effect experiments, which confirmed the dominant conduction mechanisms. This, in combination with the fact that the positive forming voltage itself is smaller than the negative forming voltage, and decreases with device scale down, provides two highly beneficial results. This good performance achieved by using ITO with N2 suggests significant progress of RRAM and remarkable potential applications. [ABSTRACT FROM PUBLISHER]

This paper proposes low power consumption resistance random access memory (RRAM) devices with indium–tin-oxide (ITO) electrodes. The development of the Internet of Things (IoT) is a trend in future technology, but the bottleneck in IoT development is high power consumption; therefore, targeting low-power-consumption memory is crucial for the IoT. ITO-capped RRAM devices have been shown to exhibit outstanding performance and low power consumption, and here, we propose an oxygen accumulation mechanism by analyzing device characteristics. We find that the conduction current mechanism will be affected by oxygen absorbance in the ITO electrode. During the forming and set processes, oxygen ions will be propelled into the ITO electrode due to its oxygen vacancy-rich property; therefore, we find Schottky emission both at high-resistance state and low-resistance state and that the device exhibits an automatic current compliance property. Varied stop-voltage measurements were carried out to verify the device mechanism. Because of its capability for oxygen storage, the thick ITO layer was confirmed to affect the characteristic due to a difference in oxygen gradient. A new structure and novel material are proposed, based on the devices with ITO electrodes to improve performance and reduce power consumption. [ABSTRACT FROM PUBLISHER]

A comprehensive physical model on the resistive switching (RS) behaviors of bilayered TaOx-based RS access memory [resistive random access memory (RRAM)] is presented. In the model, the effects of the generation and recombination (G-R) of oxygen vacancies ( $V_{{\rm{O}}}$ ), phase transition (P-T) between Ta2O5 and TaO2, and the interaction (I-A) between Ta2O5 and TaOx layers are involved to explain the RS behaviors based on ab initio calculations. An atomistic Monte Carlo simulation method based on the model is developed to investigate the dynamic physical processes and reproduce the experimental phenomena. The impacts of G-R and P-T as well as the I-A effects on the RS behaviors of a bilayered Ta2O5/TaOx structure and the device performances are identified. This paper indicates that the G-R effect dominates the RS behaviors, and self-compliance is due to the I-A effect. Based on the simulations, the optimization guidance of a bilayered TaOx-based RRAM is presented. [ABSTRACT FROM AUTHOR]

In this paper, we present a compact model for metal–oxide-based resistive random access memory (RRAM) devices with bipolar switching characteristics. The switching mechanism relies on the dynamics of conductive filament growth/dissolution in the oxide layer. Besides the dc and pulsed $I$ – $V$ characteristics, the model also captures the RRAM retention property and the temperature dynamics. The model parameters and the device variations are calibrated from the experimental data of IMEC HfOx-based RRAM devices. The model has been implemented in Verilog-A, which can be easily adapted into the SPICE simulator for the circuit-level analysis. As case studies, we demonstrate the model’s applications on the programming scheme design of the 1-transistor-1-resistor array, as well as the design space exploration of the 1-selector-1-resistor cross-point array toward megabit-level. [ABSTRACT FROM PUBLISHER]

We study in detail the impact of alloying HfO2 with Al (Hf1–xAl2xO2+x) on the oxide-based resistive random access memory (RRAM) (OxRRAM) thermal stability through material characterization, electrical measurements, and atomistic simulation. Indeed, migration of oxygen atoms inside the dielectric is at the heart of OxRRAM operations. Hence, we performed comprehensive diffusion barrier calculations in HfO2, Hf1–xAl2xO2+x, and Hf1–xTixO2 relative to the oxygen vacancy ( Vo ) movement involved in low-resistance state ( R\mathrm{\scriptscriptstyle ON} ) thermal stability. Calculations are performed at the best level using ab initio techniques. This paper provides an insight on the improved R\mathrm{\scriptscriptstyle ON} stability of our Hf1–xAl2xO2+x-based RRAM devices and predicts the degraded retention of Hf1–xTixO2-based RRAM measured in the literature. Our theoretical calculations link the origin of R\mathrm{\scriptscriptstyle ON} retention failure to the lateral diffusion of oxygen vacancies at the constriction/tip of the conductive filament in HfO2-based RRAM. [ABSTRACT FROM PUBLISHER]

Resistive-switching memory (RRAM) is attracting a widespread interest for its outstanding properties, such as low power, high speed, and good endurance. A crucial concern for RRAM is the current fluctuation, which induces significant broadening of resistance levels in single-bit and multilevel applications. This paper addresses low-frequency fluctuations focusing on $1/f$ and random telegraph noise contributions in intrinsic, i.e., typical, cells. The current fluctuations are studied in both the time and frequency domains, and the analytical models are presented to predict the resistance broadening for different RRAM states. Finally, the resistance dependence of noise and broadening is studied with the support of a 3-D finite-element model. [ABSTRACT FROM AUTHOR]

Noise in resistive switching memory (RRAM) is among the main concerns due to its impact on the reliability of single-bit and multilevel cell devices. Although noise in typical RRAM cells is understood fairly well, the statistics of noise and the presence and impact of statistical tails in the current fluctuation is what mostly affects the RRAM reliability at the array level. This paper addresses current noise in RRAM arrays, focusing on high-resistance state distribution and its broadening with time. We highlight two main contributions to the tail behavior, namely, random walk (RW) and random telegraph noise (RTN) with random start and stop. We provide evidence for a time decay of RW amplitude with time, which we explain by time-dependent stabilization of defects. We finally develop a statistical Monte Carlo model for noise, which is capable of explaining the broadening of the resistance distribution based on a physical description of RW and RTN components. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate three key features of oxide-based nano-oscillators: 1) the observation of threshold switching and filamentary oscillations in TaOx; 2) the highest frequency achieved by oxide-based oscillators; and 3) a study with linear (resistor) and nonlinear (transistor) ballasts to clearly understand the role of filament dynamics in scaling. These oscillators show frequency tunability over the range of 20 kHz–250 MHz, with 250 MHz being the highest reported frequency for this class of oscillators. Different types of ballasts show frequency tunability using two distinct methods: 1) by tuning the channel resistance of the transistor and 2) by increasing the rail voltage across the ballast–device pair. This sheds new light on the oscillator dynamics for dense oscillator arrays aimed at oscillatory neural networks and other applications. [ABSTRACT FROM AUTHOR]

In this paper, the nonlinear switching mechanism of the Ti/HfO2/Al2O3/TiN crossbar structure resistive random access memory device with good reliability is investigated. The nonlinearity of the device can be revealed by inserting a large bandgap of an Al2O3 thin layer between the TiN bottom electrode and the HfO2 switching film. The nonlinear switching mechanism caused by Flower–Nordheim tunneling involves the tunneling barrier of the Al2O3 layer. Besides, the nonlinear behavior is also sensitive to the thickness of the inserting Al2O3 layer. A high nonlinear factor of 37, large endurance more than 10^4 , and good retention properties are achieved in the Ti/HfO2/Al2O3 (1-nm)/TiN structure. [ABSTRACT FROM AUTHOR]

This paper investigates the impact of cell variability on the read performance of the one-selector one-resistor (1S1R) cross-point array. A variability-aware array-sizing analysis methodology is introduced, considering three independent variability sources, namely, the data pattern randomness, the selector variability, and the resistive switching element (RSE) variability. By analyzing the impact of each variability factor separately, we show that the data pattern randomness is not an important contributor for the read margin (RM) degradation. While the intrinsic RSE variability reflected in the narrowing of the ON/OFF RSE window degrades the RM, the selector variability adds to this further, mainly affecting the ON-state readout current, and causing extra RM degradation. To accommodate cell variability and guarantee acceptable read performance, additional cell performance margin is required. The 1S1R requirements are extrapolated for 1-Mb array, assuming variability-affected cells. It is found that, with a typical selector variability, a minimal RSE window of 5 and a selector half-bias nonlinearity of $\sim 8000$ are required to achieve at least 10% RM. [ABSTRACT FROM AUTHOR]

3-D resistive switching random access memory (RRAM) is a promising candidate for high-density nonvolatile memory applications, as well as for monolithic 3-D integration interleaved with logic layers. In this paper, we develop a methodology for assessing and optimizing large-scale 3-D RRAM arrays. A systematic study on the intrinsic switching behaviors and optimization of 3-D RRAM arrays is performed, combining device measurements and 3-D array simulations. The dependence of programming voltage on array size, cell location and pulse parameters, statistical properties of operating 3-D RRAM arrays, and subthreshold disturbance on RRAM cells is experimentally investigated. Optimization guidelines for the performance and reliability of 3-D RRAM arrays from device level to architecture level are presented: 1) an optimized 1/ $n$ architecture for 100-kb 3-D RRAM arrays can improve write margin by 69.6% and reduce energy consumption by 75.6% compared with a conventional full-size array design; 2) a strategy of prioritizing storage location for reliable operation is presented; and 3) an optimal hopping barrier of oxygen ions is found to improve array immunity to disturbance. [ABSTRACT FROM PUBLISHER]

This paper investigates the impact of threshold switching (TS) selector characteristics on the one-selector one-resistor (1S1R) cross-point array performance. TS selector parameter requirements are extracted for 1 Mb array, considering 1S, 1R cell compatibility, read/write margin, and power consumption constraints. The SPICE simulation results show that the threshold voltage ( V\mathrm {\mathbf {th}} ) and the ON-state resistance ( Rs ) are important selector parameters. Low V\mathrm {\mathbf {th}} eliminates 1R disturb issue during the read operation, but this comes at the expense of losing full cell nonlinearity (NL) during the write operation. Increase of V\mathrm {\mathbf {th}} and Rs improves the full cell NL and alleviate read disturb issue. However, these reduce 1S1R read window and additional voltages are required for both read and write operations. Compared with selector with nonabrupt current-voltage ( $I$ – $V$ ) characteristics, the TS selector is more favorable for the low-voltage operation. Finally, different reported TS selectors are evaluated, and the improvement directions are suggested. [ABSTRACT FROM PUBLISHER]

This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in storage-class memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM. [ABSTRACT FROM AUTHOR]

In this paper, the use of HfO2-based oxide-based resistive memory (OxRAM) devices operated in binary mode to implement synapses in a convolutional neural network (CNN) is studied. We employed an artificial synapse composed of multiple OxRAM cells connected in parallel, thereby providing synaptic efficacies. Electrical characterization results show that the proposed HfO2-based OxRAM technology offers good electrical properties in terms of endurance ( > 10^8 cycles), speed (<10 ns), and low energy (<10 pJ), and thus being well suited for neuromorphic applications. A device physical model is developed in order to study the variability of the resistance as a function of the stochastic position of oxygen vacancies in 3-D. Finally, the proposed binary OxRAM synapse has been used for CNN system-level simulations. High accuracy (recognition rate > 98%) is demonstrated for a complex visual pattern recognition application. We demonstrated that the resistance variability and the reduced memory window of the OxRAM cells when operated at extremely low programming conditions (<10 pJ per switching event) have a small impact on the performances of proposed OxRAM-based CNN (recognition rate 94%). [ABSTRACT FROM AUTHOR]

In this paper, we investigate the random telegraph noise (RTN) in hafnium-oxide resistive random access memories in high resistive state (HRS). The current fluctuations are analyzed by decomposing the multilevel RTN signal into two-level RTN traces using a factorial hidden Markov model approach, which allows extracting the properties of the traps originating the RTN. The current fluctuations, statistically analyzed on devices with a different stack reset at different voltages, are attributed to the activation and deactivation of defects in the oxidized tip of the conductive filament, assisting the trap-assisted tunneling transport in HRS. The physical mechanisms responsible for the defect activation are discussed. We find that RTN current fluctuations can be due to either the coulomb interaction between oxygen vacancies (normally assisting the charge transport) and the electron charge trapped at interstitial oxygen defects, or the metastable defect configuration of oxygen vacancies assisting the electron transport in HRS. A consistent microscopic description of the phenomenon is proposed, linking the material properties to the device performance. [ABSTRACT FROM AUTHOR]

A model of resistive random access memory (RRAM) cells aimed at providing an optimal programming/erase scheme in which the timing and biasing can be accurately optimized is proposed and implemented. To expedite technology development with an emphasis on ICs, a predictive model to capture the physical operation of every memory cell is needed. Although a number of compact RRAM models have been developed, this paper further considers the time-dependent reset process and the heat transfer in the conductive filaments. These phenomena are becoming critical in scaled memory cells and need to be carefully addressed. Due to the physical nature of the model, model parameters can be straightforwardly calibrated, relying on limited measurement data. The compact model is implemented using Verilog-A, and it is flexible for different circuit simulators. [ABSTRACT FROM PUBLISHER]

All resistive switching memory devices face a critical voltage-time dilemma, as they require fast write at moderate voltage together with disturb immunity at lower (read) voltage. In this paper, excellent voltage-time characteristics are demonstrated on a 90-nm CMOS-friendly W/Al2O3/TiW/Cu conductive-bridging memory cell. The switching voltage was evaluated in the large write pulsewidth range between 10 ns and 10 s, from which a very low slope of $\sim 75$ mV/decade was extracted. These characteristics allow, on the one hand, a fast switching (10 ns) at <3 V, and, on the other hand, excellent voltage-disturb immunity extrapolated to ±0.5 V for 10 years. Both constant-voltage-stress and read-endurance tests supported these predictions. By means of conductive-atomic-force microscopy tomography, the hourglass shape of the Cu filament was evidenced. Both the more distributed electrical field induced by this shape along the filament and the analysis of a charge-transfer (redox) reaction as rate-limiting mechanism in the switching process are discussed as the origins of this excellent disturb immunity. [ABSTRACT FROM AUTHOR]

Logic gates based on the resistive switching random access memory (RRAM) allow normally-off digital computing because of the nonvolatile nature of the RRAM switch [1]. An extremely small area consumption can be achieved because of the 2–terminal structure of the RRAM switch and its capability of 3-D stacking. However, the details of RRAM organization within the array must be thoroughly investigated. This paper discusses the array organization and the select/unselect schemes of the RRAM logic circuits. We demonstrate a 1-bit adder to support the high functionality of RRAM logic. These results support RRAM as a promising technology for nonvolatile logic circuits beyond CMOS. [ABSTRACT FROM AUTHOR]

Recently, spin-transfer torque magnetic random access memory (STT-MRAM) has been considered as a promising universal memory candidate for future memory and computing systems, thanks to its nonvolatility, high speed, low power, good endurance, and scalability. However, as technology scales down, STT-MRAM suffers from serious process variations and thermal fluctuations, which greatly degrade the performance and stability of STT-MRAM. In general, the optimization and robustness of STT-MRAM under process variations often require a hybrid design flow and multilevel codesign strategies. In this paper, we quantitatively analyze the impacts of process variations and thermal fluctuations on the STT-MRAM performances from physics, technology, and circuit design point of views. Based on the analyses, we found that readability is becoming the newest challenge for deeply scaled STT-MRAM due to the conflict between sensing margin and read disturbance. To deal with this problem, a novel reconfigurable design strategy from device, circuit, and architecture codesign perspective is then presented. Finally, a conceptual hybrid magnetic/CMOS design flow is also proposed for STT-MRAM in deeply scaled technology nodes. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) relies on the voltage-driven formation/disruption of a conductive filament (CF) across a thin insulating layer. Due to the 1-D structure of the CF and discrete nature of defects, the set and reset states of the memory device generally display statistical variability from cycle to cycle. For projecting cell downscaling and designing improved programming operations, the variability as a function of the operation parameters, such as the maximum current in the set process and maximum voltage in the reset process, need to be evaluated and understood. This paper addresses set/reset variability, presenting statistical data for HfOx-based RRAM and introducing a physics-based Monte Carlo model for switching statistics. The model can predict the distribution of the set state as a function of the compliance (maximum) current during set and distribution of the reset state as a function of the stop (maximum) voltage during reset. Numerical modeling results are finally presented to provide additional insight into discrete fluctuation events. [ABSTRACT FROM AUTHOR]

A key concern for resistive-switching random access memory (RRAM) is the read noise, due to the structural, chemical, and electrical modifications taking place at the localized current path, or conductive filament (CF). Read noise typically appears as a random telegraph noise (RTN), where the current randomly fluctuates between ON and OFF levels. This paper addresses RTN in RRAM, providing physical interpretations and models for the dependence on the programming and read conditions. First, we explain the RTN dependence on the compliance current during set transition in terms of the size-dependent depletion of carriers within the CF. Then, we discuss the bias dependence of the RTN switching times and amplitude, which can be explained by Joule heating and Poole-Frenkel barrier modifications arising from the electrostatics of the RTN fluctuating center. [ABSTRACT FROM AUTHOR]

This paper presents a physics-based compact model for the program window in HfOx resistive random access memory devices, defined as the ratio of the resistances in high resistance state (HRS) and low resistance state (LRS). This model allows extracting the characteristics of the conductive filament (CF) in HRS. For a given forming current compliance limit, the program window is shown to be correlated to the thickness of the reoxidized portion of the CF in HRS, which can be modulated by the reset voltage amplitude. On the other hand, the statistical distribution of the memory window depends exponentially on the barrier thickness variations that points to the critical role of reset conditions for the performance optimization of RRAM devices. [ABSTRACT FROM AUTHOR]

A highly transparent resistive random access memory with a configuration of multilayer graphene (MLG)/ Dy2O3 /indium tin oxide (ITO) structure is demonstrated in this paper. The fabricated device is transparent, with 80% transmittance at 550 nm. The MLG/ Dy2O3 /ITO device shows unipolar resistance switching with a low operation current (<100~\muA) , low operation voltage (<1~V) , low power consumption (<100~\muW) , high resistance ratio (>10^4) , fast switching speed (<60~ns) , reliable data retention, and promising cycle endurance properties (>200~cycles) , which makes a step toward the realization of low-power transparent electronics for next-generation nonvolatile memory application. The MLG/ Dy2O3 /ITO device exhibited typical filamentary-conduction-type resistive random access memory behavior and no forming process is required. High resistance state (HRS) increases with a reduced device area while low resistance state (LRS) is insensitive to the device sizes. Moreover, Raman spectra obtained in pristine state, HRS, and LRS indicate that the lower power consumption of MLG/ Dy2O3 /ITO device is attributable to the formation of oxygen graphene layers. [ABSTRACT FROM AUTHOR]

The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I–V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation. [ABSTRACT FROM PUBLISHER]

The goal of neuromorphic engineering is to build electronic systems that mimic the ability of the brain to perform fuzzy, fault-tolerant, and stochastic computation, without sacrificing either its space or power efficiency. In this paper, we determine the operating characteristics of novel nanoscale devices that could be used to fabricate such systems. We also compare the performance metrics of a million neuron learning system based on these nanoscale devices with an equivalent implementation that is entirely based on end-of-scaling digital CMOS technology and determine the technology targets to be satisfied by these new devices. We show that neuromorphic systems based on new nanoscale devices can potentially improve density and power consumption by at least a factor of 10, as compared with conventional CMOS implementations. [ABSTRACT FROM AUTHOR]

In this paper, key aspects of the electroforming in resistive-RAM cells with \HfO2 are addressed. Specifically, transient measurements were performed on extremely short timescales to characterize systematically the forming time as a function of the voltage pulse amplitude, temperature, electrode materials, and device area. An analytical model was developed, accounting for the investigated experimental parameters. Impact of the forming (and SET) waveform on read disturb is also investigated. [ABSTRACT FROM AUTHOR]

Resistive-switching random access memory (RRAM) devices utilizing a crossbar architecture represent a promising alternative for Flash replacement in high-density data storage applications. However, RRAM crossbar arrays require the adoption of diodelike select devices with high on–off -current ratio and with sufficient endurance. To avoid the use of select devices, one should develop passive arrays where the nonlinear characteristic of the RRAM device itself provides self-selection during read and write. This paper discusses the complementary switching (CS) in hafnium oxide RRAM, where the logic bit can be encoded in two high-resistance levels, thus being immune from leakage currents and related sneak-through effects in the crossbar array. The CS physical mechanism is described through simulation results by an ion-migration model for bipolar switching. Results from pulsed-regime characterization are shown, demonstrating that CS can be operated at least in the 10-ns time scale. The minimization of the reset current is finally discussed. [ABSTRACT FROM AUTHOR]

This paper reports on comprehensive analytical and numerical circuit analyses on the read margin of the one selector–one resistor (1S1R) resistive-switching crossbar array. These analyses are based on the experimental characteristics of the 1S1R cells and provide a valuable insight into their potential for ultrahigh-density data storage. Three read schemes, namely, one bit-line pull-up (One-BLPU), all bit-line pull-up (All-BLPU), and partial bit-line pull-up (Partial-BLPU), are investigated. In contrast to the One-BLPU scheme, the All-BLPU scheme can realize a large crossbar array of 16 Mb, even when the line resistance is nonnegligible because the effective resistance at the sneak current path is substantially less sensitive to the array size. Additionally, the Partial-BLPU scheme can be used to reduce power consumption if random read access is desirable. Finally, the effects of line resistance on the read and write margins are discussed. [ABSTRACT FROM AUTHOR]

In this paper, we study the effect of highly doped n^+/p^+ Si as the bottom electrode on unipolar RRAM with Ni-electrode/\HfOx structure. With heavily doped p^+-Si as the bottom electrode, RRAM devices illustrate the coexistence of the bipolar and the unipolar resistive switching. Meanwhile, by substituting heavily doped n^+-Si, the switching behavior changes to that of the self-rectifying unipolar device. The asymmetry and rectifying reproducible behavior in a n^+-\Si/HfOx/\Ni device resulted from the Schottky barrier of defect states in the \SiOx/\HfOx junction and n^+ Si substrate, but this behavior is not seen for the p^+-Si bottom electrode case. With rectifying characteristics and high forward current density observed in the \Ni/HfOx/\n^{+}\Si device, the sneak current path in the conventional crossbar architecture was significantly suppressed. We believe that the proposed structure is a promising candidate for future crossbar-type RRAM applications. [ABSTRACT FROM AUTHOR]