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${p}$ -channel GaN field-effect transistors (FETs) with a SiNx/GaON gate stack have been demonstrated with enhanced stability within a wide range of voltage bias and temperature. In this letter, the gate leakage characteristics and reliability of this unconventional staggered gate stack are investigated. At relatively low gate voltages, the gate current is suppressed owing to the buried-channel structure and the presence of GaON that presents an effective hole barrier. With more negative gate biases, the gate leakage was found to be dominated by the transport of holes that spillover from the ${p}$ -channel through the SiNx via Poole-Frenkel emission. Based on this gate leakage mechanism at large gate bias, $\sqrt {{\mathrm {E}}} $ model was used for gate lifetime prediction. The maximum applicable ON-state gate voltage of −7.3 V is obtained for a 10-year lifetime with a 1% gate failure rate. [ABSTRACT FROM AUTHOR]

In this work, we study the gate leakage mechanisms of E-mode p-n junction/AlGaN/GaN (PNJ) high electron mobility transistors (HEMTs), which have been shown to deliver low gate leakage and wide safe operating gate-bias range. The intrinsic gate leakage through the PNJ-gate was found to be limited by the transport of holes through the p-GaN layer, which occurs via Poole-Frenkel emission and phonon-assisted tunneling in low and high gate bias region, respectively. In addition, lateral leakage current and the role of variable hopping process (VRH) are also discussed. Gate leakage current models based on the revealed mechanisms can quantitatively reproduce the gate-leakage behavior in the entire relevant range of gate biases and temperatures. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a GaN-based $\textit {p-n}$ junction gate (PNJ) HEMT featuring an ${n}$ -GaN/ ${p}$ -GaN/AlGaN/GaN gate stack. Compared to the more conventional ${p}$ -GaN gate HEMT with a Schottky junction between the gate metal and ${p}$ -GaN layer, the $\textit {p-n}$ junction can withstand higher reverse bias at the same peak electric-field as the depletion region extends to both the ${n}$ -side and ${p}$ -side, while exhibiting lower leakage current. The PNJ-HEMT shows a positive threshold voltage (${V}_{\text {TH}}$) of 1.78 V, a small gate leakage $(\sim 10^{-3}$ mA/mm @ ${V}_{\text {GS}} = {10}\,\, \text {V}$). In particular, a large forward gate breakdown voltage of 19.35 V at 25 °C and 19.70 V at 200 °C was achieved with the PNJ-gate HEMT. [ABSTRACT FROM AUTHOR]

Low-loss reverse-conducting normally- OFF double-channel AlGaN/GaN power transistor with the built-in Schottky barrier diode (SBD) has been systematically studied. This device features the MOS-gate section and SBD-anode section paralleled to an interdigital layout along the gate width direction. A common access region that conducts current at both forward and reverse ON-states is employed, which is beneficial to reduce the conduction loss. With a MOS-HEMT/SBD finger width of ${4}~\mu \text{m}/2~\mu \text{m}$ and a total width ratio of 2:1, the device exhibits a threshold voltage of +0.8 V at a drain current of ${10}~\mu \text{A}$ /mm and a low forward ON-resistance of $12.1~\Omega \cdot \text {mm}$. The Schottky metal contacts 2-DEG directly, which results in a low reverse turn-on voltage of −0.6 V (at −1 mA/mm) and low reverse ON-state voltage of −1.7 V (at −50 mA/mm). A leakage suppression MOS field plate (FP) is applied to shield the Schottky contact from the strong electric field, leading to a low OFF-state leakage current of 14 nA/mm at +100-V drain bias and a high breakdown voltage (BV) of +698 V. The finger width and the number of fingers should be optimized. A narrow finger width benefits the current sharing at the access region, while the increasing number of fingers introduces more Schottky depletion regions along the gate width direction that degrade ${R}_{ \mathrm{\scriptscriptstyle ON}}$. [ABSTRACT FROM AUTHOR]

Under reverse-bias stress (i.e., OFF-state stress with ${V} _{\text {GS}} < {V}_{\text {TH}}$) with high drain voltage, ultraviolet (UV) illumination and larger negative gate bias are found to accelerate the positive shift in threshold voltage (${V}_{\text {TH}}$) of enhancement-mode GaN MIS-FETs with fully recessed gate. These results suggest a hole-induced degradation mechanism. In the absence of UV illumination, holes could be generated by impact ionization in the high electric-field region, which is initiated by electrons injected from the source through the buffer layer. With a larger negative gate bias, more holes will flow to the gate side and pass through the silicon nitride (SiNx) gate dielectric, as SiNx does not present any energy barrier to holes. The enhanced hole transport through the dielectric under large negative gate bias could accelerate new defects generation and therefore result in the larger positive threshold voltage shifts. [ABSTRACT FROM AUTHOR]

In this paper, we carried out a systematic comparison between the enhancement-mode GaN-based fully recessed metal-insulator-semiconductor field-effect transistors (MIS-FETs) and partially recessed MIS-high-electron-mobility transistors (MIS-HEMTs) with the same gate dielectric stack (LPCVD-SiNx/PECVD-SiNx) that has delivered promising long-term reliability and stability. Despite a moderately larger on-resistance (${R}_{ \mathrm{ON}}$), the MIS-FETs deliver superior ${V}_{\text {TH}}$ uniformity and thermal stability. Under long-term gate bias stress, both the MIS-HEMT and MIS-FET deliver similar small positive-bias temperature instability, while the negative-bias temperature instability of the MIS-HEMT is much larger than that of MIS-FET. The MIS-FET also delivers a higher ${V}_{\text {TH}}$ stability than the MIS-HEMT under dynamic gate bias stress. It is suggested that the differences in ${V}_{\text {TH}}$ stability mainly originate from the different spatial separation between the trap states and the conducting channel, with it being larger in MIS-HEMT than in MIS-FET. [ABSTRACT FROM AUTHOR]

An MOS field plate-protected Schottky-drain (gated Schottky-drain) is successfully integrated on a double-channel AlGaN/GaN MOS-HEMT to provide reverse blocking capability. The leakage suppression MOS field plate is deployed on the etched upper GaN channel layer after a barrier fully recess process, leading to a low reverse OFF-state leakage current of −20 nA/mm (at −100 V). The drain metal is deployed adjacent to the MOS field plate, contacting the upper MOS-channel and lower heterojunction channel from the sidewall. A metal-2DEG Schottky contact with a low turn-ON voltage of 0.5 V is achieved. Since the lower channel (below the MOS field plate) is separated from the etched surface of upper GaN channel layer, a high-conductivity MOS-gated channel with a sheet resistance of 806 $\Omega$ /Square is obtained. The device exhibits a threshold voltage of +0.6 V (at $10~\mu \text{A}$ /mm and +1.9 V from linear extrapolation) and an ON-resistance of ~18 $\Omega {\cdot} \text {mm}$. Besides, a high forward (and reverse) breakdown voltage of 790 V (and −656 V, all at $10~\mu \text{A}$ /mm) is achieved. [ABSTRACT FROM AUTHOR]

In this work, characterizations are conducted to investigate the threshold voltage (VTH) stability of the normally‐off GaN metal–insulator–semiconductor (MIS‐) field‐effect transistor (FET) with fully recessed gate structure and highly reliable low‐pressure chemical vapor deposition SiNx gate dielectric. We conducted bias‐temperature instability (BTI) tests under both positive and negative gate bias. We demonstrated the highly stable VTH of the high‐performance MIS‐FETs with small BTI, which benefits from the effective interfacial protection layer. More specifically, combining the BTI tests and drain current 1/f noise analysis, we present extensive investigation of the physical origins of BTI. According to the experimental evidence and analysis, we ascribe the VTH instability to the trapping/detrapping of the pre‐existing trap states located at the SiNx/GaN interface and/or in the gate dielectric. [ABSTRACT FROM AUTHOR]

In this letter, we investigated the threshold voltage V\text {TH} stability under reverse-bias step-stress in the E-mode LPCVD-SiNx/PECVD-SiNx/GaN MIS-FET. Under the OFF-state reverse-bias stress with the same net gate-to-drain voltage ( V\text {GD} ), the V\text {TH} shift shows an obvious dependence on the negative gate bias. With a V\text {GS} of 0 V, the V\text {TH} shift is small and recoverable, while the V\text {TH} shifts are substantially larger with more negative gate bias ( V\text {GS}=-20 V). This larger V\text {TH} shifts caused by the negative V\text {GS} can be explained with a hole-induced degradation model. An important indication revealed by this model is that negative gate bias should be well confined in high-power switching applications of GaN E-mode MIS-FET for a stable V\text {TH} . [ABSTRACT FROM PUBLISHER]

An AlGaN/GaN double-channel Schottky barrier diode (DC-SBD) with dual-recess gated anode is demonstrated in this letter. The DC-SBD features two recess steps. The deep one cuts through two channels, and the anode metal contacts 2DEG directly from the sidewall of the recessed heterostructure. The shallow one terminates at the upper channel layer and is located adjacent to the Schottky contact. A MOS field plate is placed on the shallow recess region to pinchoff the underlying channels, so the off-state leakage current of the DC-SBD can be suppressed. Since the lower channel is separated from the etched surface, the field-effect mobility beneath this MOS structure shows a high peak value of 1707 cm2/( \text V\cdot \text s ). The DC-SBD with an anode-to-cathode length ( L\text {ac} ) of 15~\mu \textm exhibits a turn-on voltage ( V\text {T} ) of ~0.6 V (at 1 mA/mm), a leakage current of 7.8 nA/mm (at −100 V), and a breakdown voltage of 704 V (at 1~\mu \textA /mm). The double-channel design also allows both the deep and shallow recesses to be terminated at GaN layers that results in high uniformity of V\text {T} . [ABSTRACT FROM PUBLISHER]

In this paper, we report a systematic study of the nitridation effects on GaN surface by first-principles calculations and X-ray/ultraviolet photoemission spectroscopy (XPS/UPS). According to the calculated electronic structures, two surface bands (i.e., the upper band and the lower band) can be seen within the bandgap for the typical surface configurations that may occur in the experimental condition as a result of surface reconstruction. By the deployment of sufficient nitridation, the energy positions of the lower band are modified toward the valence band by ~1 eV, resulting in the overlapping of the lower surface band with the valence band. Meanwhile, the upper surface band is also modified toward the valence band, but by a smaller amount. The modification to the positions of the surface bands is furthermore manifested by XPS/UPS spectra characterization performed on GaN sample that underwent surface treatment with low-energy remote N2 plasma. The theoretical and experimental results insightfully proclaim the nitridation effects on material properties at atomic level, and support a surface-state ionization model for the GaN band-edge (3.4 eV) emission in metal-AlGaN/GaN Schottky-on-heterojunction diode under forward bias. [ABSTRACT FROM PUBLISHER]

Dynamic ON-resistance ( \mathrm RON ) of 650-V GaN-on-Si lateral power devices with a floating Si-substrate termination is investigated. Compared with the grounded substrate termination, the floating substrate could deliver smaller dynamic \mathrm RON under higher drain bias (> 400 V) switching operation, but leads to larger dynamic \mathrm RON under low-drain bias (< 400 V). The underlying physical mechanisms are explained by the tradeoff between charge storage in the Si substrate and electron trapping effect in the GaN buffer layer. [ABSTRACT FROM AUTHOR]

Developing effective technique to protect the etched- GaN surface from the degradation in a high-temperature (i.e., at ~ 780°C) process, such as low-pressure chemical vapor deposition (LPCVD), is essential for fabricating normally-off GaN MIS-FETs with high-quality dielectric/GaN interface and highly reliable gate dielectric. In this letter, we developed an approach of obtaining such a protection layer using oxygen-plasma treatment followed by in situ annealing prior to the LPCVD-SiNx deposition. A sharp and stable crystalline oxidation interlayer (COIL) between the LPCVD-SiNx and etched-GaN was successfully formed. The LPCVD-SiNx/GaN MIS-FETs with COIL deliver normally-off operation with a VTH of 1.15 V, small on-resistance, small hysteresis, and thermally stable VTH . [ABSTRACT FROM AUTHOR]

In this letter, we demonstrate an integrated process that illustrates the compatibility of AlN/SiNx passivation with high-performance (i.e. low leakage and high breakdown) low-pressure chemical vapor deposition (LPCVD) SiNx gate dielectric for GaN-based MIS-HEMT. It is shown that the AlN/SiNx passivation structure maintains its superior capability of suppressing the current collapse after enduring high temperature of 780 °C during the LPCVD-SiNx deposition. The AlN/SiNx passivation is shown to be significantly better than the LPCVD-SiNx passivation by delivering small dynamic $R_{{\mathrm{\scriptscriptstyle ON}}}$ degradation, especially under high drain bias switching with $V_{{\mathrm{DS}}} > 100$ V. [ABSTRACT FROM PUBLISHER]

A low on-resistance normally-off GaN double-channel metal–oxide–semiconductor high-electron-mobility transistor (DC-MOS-HEMT) is proposed and demonstrated in this letter, which features a 1.5-nm AlN insertion layer (ISL) located 6 nm below the conventional barrier/GaN interface, forming a second channel at the interface between the AlN-ISL and the underlying GaN. With gate recess terminated at the upper channel, normally-off operation was obtained with V\mathrm {th} of +0.5 V at I\mathrm {DS}= 10 ~\mu \text{A} /mm or +1.4 V from the linear extrapolation of the transfer curve. The lower heterojunction channel is separated from the etched surface in the gate region, thereby maintaining its high field-effect mobility with a peak value of 1801 cm2/( \textV\cdot \texts ). The on-resistance is as small as 6.9 \Omega \cdot \text mm for a DC-MOS-HEMT with LG/L\mathrm {GS}/L\mathrm {GD} = 1.5/2/15~\mu \text{m} , and the maximum drain current is 836 mA/mm. A high breakdown voltage (>700 V) and a steep subthreshold swing of 72 mV/decade are also obtained. [ABSTRACT FROM AUTHOR]

In this paper, we systematically investigated the leakage and breakdown mechanisms of the low-pressure chemical vapor deposition (LPCVD) silicon nitride thin film deposited on AlGaN/GaN heterostructures. The LPCVD-SiNx gate dielectric exhibits low leakage and high breakdown electric field. The dominant mechanism of the leakage current through LPCVD-SiNx gate dielectric is identified to be Poole–Frenkel emission at low electric field and Fowler–Nordheim tunneling at high electric field. Both electric-field-accelerated and temperature-accelerated time-dependent dielectric breakdown of the LPCVD-SiNx gate dielectric were also investigated. [ABSTRACT FROM PUBLISHER]

In this letter, silicon nitride (SiNx) film deposited at 780 °C by low-pressure chemical vapor deposition (LPCVD) was employed as gate dielectric for GaN-based metal–insulator–semiconductor high-electron-mobility transistors. The LPCVD-SiNx exhibit improved gate dielectric performance than the plasma enhanced chemical vapor deposition-SiNx, including smaller forward and reverse gate leakage, and higher forward gate breakdown voltage. [ABSTRACT FROM AUTHOR]