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This paper proposes a power-up calibration scheme to mitigate the offset of a capacitive-gain chopper instrumentation amplifier (CCIA), thus suppressing the offset-induced output ripple. In this design, the first stage of the error amplifier is formed by multiple identical slices. Before normal operation, the offset polarity of each slice is determined by reusing the second stage of the amplifier as a comparator. With such polarity information, slices of the first stage are regrouped to achieve a statistical offset reduction. The proposed amplifier has been fabricated in a standard $0.18~\mu \text{m}$ CMOS process with an area of 0.57 mm2, achieving an average peak-to-peak output ripple of 58 mV. The amplifier consumes $1.53~\mu \text{W}$ with a 1.2 V supply. Compared to the state-of-the-art, the calibration time of the proposed scheme is much shorter (14 clock cycles) and the overhead logic consumes no static power after calibration. In addition, the slicing technique provides an extra degree of freedom to the amplifier for bandwidth and noise scaling. [ABSTRACT FROM AUTHOR]

This paper presents a transimpedance-to-noise optimization approach for design of a resistive shunt-feedback TIA. This optimization offers an enhancement in the transimpedance and a noise performance very close to the theoretical minimum noise of the TIA. In addition, the transimpedance-to-noise optimization approach results in a small front-end FET size which enables a further reduction in power and area. Moreover, this approach enables using a fewer number of stages in the receiver chain which makes a high PSRR feasible and obviates the necessity for using an offset cancellation circuitry. Building on this approach, a fully differential analog front-end including a resistive shunt-feedback TIA and a post amplifier (PA) for time-of-flight (ToF) Lidar receivers is designed and implemented, achieving 94dB Ω transimpedance gain, 71nA input-referred rms noise current, −3dB bandwidth of 340MHz, and power supply rejection ratio (PSRR) of more than 87dB in a 0.11 μm CMOS process. The associated DC power consumption is 19.4mW with V DD of 1.8V. Moreover, a push-pull buffer with 1V output swing is integrated for driving 50 Ω loads, such as off-chip time discriminators, which also additionally amplifies the signal with a gain of 5dB while consuming an extra 20.9mW of DC power. The whole chip (excluding pads) occupies 210 μm × 110 μm in area. [ABSTRACT FROM AUTHOR]

This paper presents a sensor readout integrated circuit (ROIC) using a capacitively coupled instrumentation amplifier (CCIA)-embedded continuous-time ΔΣ modulator (CT ΔΣM) incorporating chopping artifact rejection. Chopping is an essential technique for suppressing the offset and 1/ƒ noise. However, the chopping artifacts in the modulator loop degrade the in-band noise, linearity, and loop stability. In the proposed design, chopping aliasing is avoided by setting the chopping frequency (ƒch) same as the sampling frequency (ƒs). The chopping ripple is mitigated using the ripple reduction loop (RRL), and the shaped quantization noise-folding resulting from the RRL is prevented by minimizing the loop gain and bandwidth of the RRL. The residual ripple and spikes are filtered out using the alias rejection band of CT ΔΣM. The third-order loop filter enables sufficient noise-shaping with a low oversampling ratio (OSR). The chip is implemented in a 180-nm CMOS process with an active area of 1.65 mm2, drawing 232.2 μA at a 1.8 V supply. The proposed capacitively coupled (CC)-CT ΔΣM has a 19.4 nV/√Hz input-referred noise density, 1.9 μ V offset, 0.08% gain error, 16 ppm integral nonlinearity (INL), and 140 dB common-mode rejection ratio (CMRR) within an input range of 60 mVpp. With −110.1 dB total harmonic distortion (THD), excellent dynamic linearity performance is achieved owing to the CCIA-integrated design and chopping artifact rejection technique. [ABSTRACT FROM AUTHOR]

A fast-transient, current-efficient low-dropout regulator (LDO) with super transconductance cell (STC) is proposed in this paper. By adopting advanced current amplifier (CA) and dynamic biasing (DB) techniques for the error amplifier (EA), the feedback loop bandwidth can be significantly extended without increasing much quiescent power, which reduces output voltage spikes and response time greatly. Moreover, dynamic reference control (DRC) with robust loop stability is embedded in the LDO to adaptively adjust voltage reference during transient so as to further enhance the slew rate of EA, realizing significant enhancement for the transient performances. This circuit has been implemented in a 0.35 μm CMOS process and occupies an active chip area of 456 × 278 μm2. Experimental results show that it is able to provide 100mA load current at 200mV dropout voltage, with current efficiency of 99.88%. The output voltage spike under maximum load current change in 20ns edge time is less than 11.2mV with a 0.054 μs response time. The power-supply rejection (PSR) at 100kHz is −75.6dB. [ABSTRACT FROM AUTHOR]

The ability to process time-encoded signals with high fidelity is becoming increasingly important for the time domain (TD) circuit techniques that are used at the advanced nanometer technology nodes. This paper proposes a compact oscillator-based subsystem that performs precise filtering of asynchronous pulse-width modulation encoded signals and makes extensive use of digital logic, enabling low-voltage operation. First- and second-order primitives are introduced that can be used as TD memory or to enable analogue filtering of TD signals. These structures can be modeled precisely to realize more advanced linear or nonlinear functionality using an ensemble of units. This paper presents the measured results of a prototype fabricated using a 65-nm CMOS technology to realize a fourth-order low-pass Butterworth filter. The system utilizes a 0.5-V supply voltage with asynchronous digital control for closed-loop operation to achieve a 73-nW power budget. The implemented filter achieves a maximum signal to noise and distortion ratio of 53 dB with a narrow 5-kHz bandwidth resulting in an figure-of-merit of 8.2 fJ/pole. With this circuit occupying a compact 0.004-mm2 silicon footprint, this technique promises a substantial reduction in size over conventional Gm-C filters, whilst additionally offering direct integration with digital systems. [ABSTRACT FROM AUTHOR]

This paper presents a 0.4-V ultra-low power (ULP) third-order active-RC complex band-pass filter (CxBPF) for Bluetooth low energy receivers prototyped in a 180 nm CMOS process. The ULP is reached by using single-stage inverter-based operational transconductance amplifiers (OTA) instead of two or more stages OTA. The effects of the low voltage gain and resistive loading are reduced by using a process and temperature robust negative transconductor connected to the virtual ground. The ultra-low voltage operation is reached by using only two stacked transistors and PMOS bulk forward bias. The CxBPF operates well down to 0.4V power supply and the experimental results present power dissipation of only $10.9~\mu \text{W}$ /pole, 1 MHz bandwidth centered at 2 MHz, image rejection rate of 34 dB, and 12.7 fJ FoM. [ABSTRACT FROM AUTHOR]

This paper presents two new line-coding schemes, integrated pulse width modulation (iPWM) and consecutive digit chopping (CDC) for equalizing lossy wireline channels with the aim of achieving energy efficient wireline communication. The proposed technology friendly encoding schemes are able to overcome the fundamental limitations imposed by Manchester or pulse-width modulation encoding on high-speed wireline transceivers. A highly digital encoder architecture is leveraged to implement the proposed iPWM and CDC encoding. Energy-efficient operation of the proposed encoding is demonstrated on a high-speed wireline transceiver that can operate from 10 to 18 Gb/s. Fabricated in a 65-nm CMOS process, the transceiver operates with supply voltages of 0.9 V, 1 V, and 1.1 V. With the help of the proposed iPWM encoding, the transceiver can equalize over 27-dB of channel loss while operating at 16 Gb/s with an efficiency of 4.37 pJ/bit. The design occupies an active die area of 0.21 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a receiver front end with improved blocker handling implemented in a 65-nm CMOS technology. Since close-in blockers are challenging to reject at RF, the receiver features a baseband (BB) notch filter, which effectively sinks close-in blocker current directly from the output of an LNTA and passive mixer structure. The notch-filter frequency can be tuned to match the blocker offset frequency, and the measurements indicate a significant improvement in the overall front-end interference robustness, while sensitivity remains unaffected. To optimize notch performance, the BB impedance is analyzed in detail. The front-end RF range is 750 MHz–3 GHz with an RF channel bandwidth of 20 MHz corresponding to 10-MHz BB bandwidth. The notch frequency is programmable from 16, which is less than one octave from the channel edge, up to 160 MHz. The gain-compression improvement is upto 9 dB, while IIP2 can be increased by more than 26 dB without calibration and IIP3 is 1 dBm. The current overhead for the notch function is between 7.5 and 30 mA, but it only exists under strong blocker conditions as the notch filter can be switched OFF if strong blockers are absent. The total front-end current consumption excluding the notch filter varies with LO frequency from 31 to 44 mA from a 1.2-V supply. [ABSTRACT FROM AUTHOR]

This paper presents a 2.3 GS/s 12-way time-interleaved pipelined-SAR ADC achieving 1.1 GHz input bandwidth with 47.4 dB signal-to-noise distortion ratio (SNDR). Here, we propose a hierarchical interleaving with passively shared sub-sampling front-end to eliminate the timing skews, thus avoiding the timing calibration for design simplicity as well as better area and power efficiency. To provide a fast signal transfer with good power efficiency to the sub-ADCs, the power and bandwidth trades off by using the passive sharing or active buffers are analyzed according to our developed mathematic model. The analysis is based on two scenarios: noise and matching limited sampling. Moreover, we propose a boosting-capacitor-sharing technique to enhance the compactness of the time-interleaved bootstrapped sampling front-end, which is particularly critical when omitted the time calibration in this design. Measurement results on a 65 nm CMOS prototype operated at 2.3 GS/s and 1.2 V supply show 31 mW total power consumption with a SNDR of 47.4 dB @Nyquist leading to a FOM of 69 fJ/conv.step. [ABSTRACT FROM AUTHOR]

This paper presents a CMOS broadband millimeter wave power amplifier (PA) based on magnetically coupled resonator (MCR) matching network. The MCR matching network is analyzed theoretically. Design method for MCR-based broadband PA is proposed. For the PA’s output matching network, the inductance ratio should be equal to the load/source resistance ratio to achieve broadband impedance transformation. And the coupling coefficient ( $k$ ) of the MCR can be determined from the no gain ripple condition. Fabricated in 65-nm CMOS process, the PA chip achieves 32.9% peak power added efficiency, 15.3-dBm saturated output power ( $P_{\mathrm {sat}}$ ), and 12.9-dBm output 1-dB compression point ( $P_{\mathrm {1\,dB}}$ ). The fractional bandwidth of the PA is 63.3% from 21.6 to 41.6 GHz, which covers the full Ka-band (26.5 to 40 GHz). [ABSTRACT FROM AUTHOR]

An 8.5-Gb/s/link non-contact multi-drop bus is presented. The signal reflections that limit the data rates of conventional multi-drop bus interfaces are dramatically reduced by using transmission line couplers at each signal branching point. As an energy-equipartitioned technique provides the same signal level to every port, wider receiver margin is achieved. The data rate is improved by 1.8 times compared to the most advanced multi-drop bus interface. The theoretical analysis and design techniques of energy-equipartitioned transmission line couplers are discussed in this paper. The design methodologies were verified through simulations performed by using a full-3D EM-simulator and experiments with FR4 test boards. Due to the low-cut characteristics of the couplers, the low-frequency components are cut off so that differentiated pulses arrive at the receiver input point. A receiver detects and recovers the received pulses by integrating them using hysteresis characteristics. The design techniques of the transceiver for the transmission line couplers are also discussed in this paper. The proposed methods were verified by using a test chip fabricated with a 90-nm CMOS process. Experiments with a prototype of an eight-drop multi-drop bus system confirmed BER < 10^-14 at a data rate of 8.5-Gb/s/link. The measured timing margin at the far-end module was 0.49-UI at a BER of 10^-12. The power consumption of the transceiver was 75.6-mW at a supply voltage of 1.2-V. [ABSTRACT FROM PUBLISHER]

The systematic design analysis of a hybrid optoelectronic limiting receiver is presented. The limiting receiver was designed in the IBM 130-nm CMOS process and side-by-side wire bonded to a commercial high-speed InGaAs/InP PIN photodiode. The CMOS die and the optical die were chip-on-board (COB) mounted on the Printed Circuit Board. Partition between small signal in the linear region and large-signal in the limiting region is emphasized. The signal edges can get sharpened in the limiting region although the front-end circuit is bandwidth-limited. When tested with a PRBS-31 pattern, the prototype achieved a bit-error rate of 10^-12 at the sensitivity level of −3.2-dBm Mach-Zehnder Modulator optical modulation amplitude at 4 Gb/s. Conclusions derived from this paper can provide insights to guide other optical limiting receiver design and testing at higher speeds. [ABSTRACT FROM PUBLISHER]

A wideband CMOS low-noise amplifier (LNA) with multiple resonant frequencies is demonstrated in this article. A common source (CS) with inductive degeneration topology is widely employed in LNA circuit design to decouple the input impedance from the noise figure (NF). Since CS with inductive degeneration topology only achieves a single resonant frequency, it generally has narrow bandwidth performance. Through impedance transformation analysis of the matching circuit, a shunt resonator combined with inductive degeneration topology employed for input impedance transformation is carefully constructed to form multiple resonant frequencies. By placing resonant frequencies further apart from each other, impedance fluctuations within a wideband frequency range can be alleviated. In addition, the noise performance of this topology is the same as that of a conventional CS source-degenerated structure. The proposed LNA for the whole K/Ka Band is implemented in a commercial 65-nm CMOS process. It occupies 0.28 mm2. Under a 1.0 V voltage supply, the LNA achieves 3-dB gain bandwidth of 28 GHz from 16.5 GHz to 44.5 GHz. Within the whole 3-dB bandwidth, the gain is larger than 15.5 dB, the NF is less than 4.8 dB with a minimal value of 2.72 dB, and the input 1-dB gain compression point (IP1dB) varies from −24 dBm to −12 dBm. [ABSTRACT FROM AUTHOR]

The continuous-time pipeline (CTP) analog-to-digital converter is an emerging technique that combines the benefits of pipelining with continuous-time operation. Prior-art multistage CTP ADCs have employed stages with identical transfer functions. This work proposes the use of non-identical (and appropriately chosen) transfer functions for different stages of the pipeline. We investigate the benefits of this approach when compared with conventional techniques. We also demonstrate that the sharp filtering offered by a multi-stage CTP can be exploited to implicitly decimate the output sequence of the converter. This is accomplished by clocking the back-end ADC at a lower rate, and by appropriately modifying the digital reconstruction filters. The implicit-decimation theory is supported with measurement results from a three-stage CTP designed in a 65nm CMOS process. The converter achieves 70.4dB SNDR in a 100MHz bandwidth with its front-end operating at $f_{s}\,{=}\,800$ MHz, while the back-end samples at $f_{s}/2$. [ABSTRACT FROM AUTHOR]

The influence of coupling of oscillators in phase-locked loops (PLLs) was studied here. Particularly, numerical analyses based on nonlinear differential equations of the self- and mutual coupling systems were performed and compared with the results of the linear approximation model under synchronous conditions. The analysis revealed that coupling using the reference clock caused greater PLL instability than that caused by self-coupling for a given coupling strength. This shows that the phase error of mutual coupling exhibits the same behavior as that of reference-clock coupling in the single PLL under synchronous conditions, and the noise sensitivity of mutual coupling is twice that of the reference-clock coupling. In addition, the phase error of mutual coupling in the quasi-synchronous condition strongly depends on the relationship between the frequency difference of the two PLLs and the PLL bandwidth. We designed and fabricated the test circuits for theoretical verification using the 0.18- $\mu \text{m}$ standard CMOS process. From the measurements, adjustment of the timing difference between the two PLLs is effective in mitigating mutual coupling under synchronous conditions. Moreover, we implemented mutual injections between two oscillators in the test circuit and confirmed their effectiveness. The proposed methods will be useful for achieving the compact and effective cancellation of the mutual coupling between PLLs. [ABSTRACT FROM AUTHOR]

This paper presents a 5-GS/s 12-way 10-b time-interleaved successive approximation register (SAR) ADC for direct sampling receivers. Proper signal and clock distribution along the multiple channels are utilized to mitigate interchannel bandwidth and timing mismatches. A digitally assisted calibration is introduced to remove the interchannel offset, gain, and timing mismatch. The T-type bootstrapped sampling switches minimize the interchannel crosstalk among top-plate sampling SAR channels and the signal-dependent leakage current during SAR conversion cycles. The power efficiency of this ADC is significantly improved by many design techniques. The merged capacitor switching algorithm leads to high switching efficiency and a smaller area. The modified reference voltage scheme optimizes input common-mode voltage of the comparators. The optimal subradix-2 capacitive DAC results in low-power reference buffers and higher conversion speed. This ADC achieves 49-dB SNR, 52-dB THD, and 42-dB SNDR up to Nyquist frequency at 5 GS/s, consumes 76 mW from 1 V supply, and occupies 0.57 mm $^{{ {2}}}$ in 28 nm CMOS technology. The implemented architecture also demonstrates high scalability to advanced CMOS technology nodes and has even higher power efficiency potential. [ABSTRACT FROM AUTHOR]

In this paper, a generic combiner design technique is developed for class-E outphasing transmitters. The design procedure starts with calculation of the combiner network parameters that guarantee high efficiency switch mode operation of the PAs in each branch. Recently developed continuous class-E modes theory is then utilized to create an additional degree of freedom for calculation of the combiner network parameters. This additional degree of freedom along with duty cycle control provides an important possibility for achieving high average efficiency over a large bandwidth. A CMOS-GaN outphasing transmitter prototype is realized for experimental verification. The prototype provides drain efficiencies higher than 60% at 6 dB back-off across 750–1050 MHz band. Further, the peak output power remains nearly flat versus frequency, where the variation across the band is ±0.18 dB around 44 dBm. [ABSTRACT FROM AUTHOR]

A low-power continuous-time delta-sigma modulator (CTDSM) incorporating a multi-bit feedback-assisted quantizer (FBAQ) is presented in this paper. The proposed multi-bit quantizer is placed in a negative feedback loop to reduce the signal swing at its input. As a result, the number of comparator required for signal quantization is reduced. Furthermore, the modulator is optimized for low-voltage swing operation, in which the excess-loop-delay compensation is embedded without requiring additional hardware. With a 240-MHz sampling clock, this CTDSM achieves a peak SNDR of 68.3 dB and a dynamic range of 71 dB over a 5-MHz signal bandwidth. Fabricated in a 90-nm CMOS process, this chip consumes 4.6 mW from a 1-V supply, which corresponds to a figure of merit (FoM) of 216 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

A fully integrated optical-to-wireless modulator for low-cost fiber-optical backhaul links is presented in this paper. In the receiver, a CMOS photodetector with a bandwidth of 0.5 GHz is integrated to perform optical-to-electrical conversion. A gain-boosted inverter based transimpedance amplifier achieves a high gain-bandwidth product without using inductive peaking. The two-stage equalizer compensates the photodetector bandwidth and extends the operation data rate to 4 Gb/s. The wireless modulator directly up-converts and modulates the baseband I/Q NRZ data to a QPSK signal centered at 60 GHz. Realized in 65-nm CMOS, the optical front-end achieves -3-dBm optical input sensitivity at 4 Gb/s with 10^\mathrm -12 BER. The modulator produces -7.2-dBm output power with -12-dB EVM at a bit efficiency of 19.6 pJ/b. This design demonstrates that a small form factor and low cost optical-to-millimeter-wave modulator can be realized to support future fiber-wireless networks. [ABSTRACT FROM AUTHOR]

This paper describes a power and area-efficient forwarded-clock (FC) receiver and includes an analysis of the jitter tolerance of the FC receiver. In the proposed design, jitter tolerance is maximized according to the analysis by employing a delay-locked loop (DLL) based de-skewing. A sample-swapping bang-bang phase-detector (SS-BBPD) eliminates the stuck locking caused by the finite delay range of the voltage-controlled delay line (VCDL), and also reduces the required delay range of the VCDL by half. The proposed FC receiver is fabricated in 65-nm CMOS technology and occupies an active area of 0.025 mm2. At a data rate of 12.5 Gb/s, the proposed FC receiver exhibits an energy efficiency of 0.36 pJ/bit, and tolerates 1.4-\textUI\mathrm{pp} sinusoidal jitter of 300 MHz. [ABSTRACT FROM AUTHOR]

This paper describes the design and implementation of a linear optical receiver front-end for short range optical communication applications in 0.13-\mu\textm CMOS technology. While conventional optical receivers are typically implemented using limiting amplifiers (LA), emerging optical systems are expected to employ advanced modulation schemes, which require preserving the signal envelope. The proposed linear optical receiver architecture utilizes super-Gm transimpedance amplification with common-mode restoration and constant settling time automatic gain control (AGC) with background illumination cancellation to preserve the signal linearity while tolerating capacitance up to 15 pF for large area photo-detectors. Linearity aware design of transimpedance amplifiers (TIA), variable gain control (VGA), and post amplifiers (PA) are discussed before introducing an exponential generator based on the parasitic BJTs available in the used technology. Consuming 40 mW from a 1.2 V supply in the presence of ∼15 pF input capacitance, the circuit achieves a binary modulation data rate of 5 Gbps with an input sensitivity of \sim 65\ \mu\textA maintaining a bit-error rate (BER) < 10^-12. S-parameter measurements show a constant −3 dB bandwidth of 2.5 GHz for a wide dynamic range of ∼45 dB (30–75 \textdB\Omega) with dB-linearity error better than ±1 dB. To demonstrate the optical functionality of the architecture, an external photodiode (PDCS70T-GS) is directly wirebonded to the chip. Optical measurements confirm a sensitivity of −9.5 dBm (\textBER < 10^-12) at a highest data rate of 5 Gb/s (\lambda = 680\ \textnm). The noise and linearity performance of the receiver is verified using input referred integrated noise and 1 dB-compression point measurements for different gain settings. [ABSTRACT FROM AUTHOR]

This paper discusses novel architectures and circuit techniques for DPLLs. These include: methods to have a wide temperature range in the digitally controlled oscillator (DCO) for ring-oscillator based DPLLs, re-circulating time to digital converter (TDC) architecture to support a large input phase error range, efficient, modular, divider architectures that provide 50% output duty cycle, while allowing dynamic programmability of the division ratio, and fractional DPLL approaches for spur cancellation and low power operation. The techniques described in the paper have been used to build DPLLs for serializer-deserializer (SerDes), processor clock generation, and wireless connectivity applications in 65 nm and 45 nm CMOS. These implementations are briefly discussed and representative silicon results are presented. [ABSTRACT FROM AUTHOR]

This paper presents an inductorless 0.13-\mum CMOS TIA structure that is a modified version of a regulated cascode (RGC) TIA. An immittance converter is incorporated to reduce power consumption while increasing transimpedance gain. Measured 3-dB bandwidth is 7 GHz, sufficient for 10-Gb/s operation, in the presence of 250 fF capacitance at the TIA input, representative of typical CMOS photodiode capacitance. The transimpedance gain of the single-stage TIA is 50 dB\Omega, and the group-delay variation is less than \pm19 ps over the 3-dB bandwidth. The circuit occupies an active area of 180\ \mum\times 90\ \mum and consumes 7 mW from a 1.5-V supply. The measured average input-referred current noise of the TIA is 31 pA/\sqrtHz. Simulations and analysis show that the proposed single-stage TIA architecture is capable of achieving improvement in the transimpedance limit over a single-stage RGC TIA designed for the same data rate and the same input photodiode capacitance. A comparison of measurement results to published TIAs also demonstrates the competitive performance of the proposed TIA in terms of the TIA transimpendance gain, bandwidth, area, and power consumption. [ABSTRACT FROM PUBLISHER]

The past several years have successfully brought all-digital techniques to the RF frequency synthesis, which could arguably be considered one of the last strong bastions of the traditionally-analog design approaches. With their high sensitivity and high dynamic range requirements, the RF circuits have long had a good excuse to avoid any possible source of digital switching activity. With the constant scaling of CMOS feature size and the merciless push for integration, the existence of almost free and powerful digital logic could not go unnoticed. Hence, the environment was ripe to transform the RF functions into digital realizations, as well as to apply digital assistance to help with the performance of RF circuits. This paper revisits the digitization journey of the traditional charge-pump PLL that has resulted in an all-digital frequency synthesizer with the best-in-class RF performance while occupying only a fraction of the silicon area and consuming a fraction of the power. The paper also offers a few novel techniques to further improve area, current consumption, testability, and reliability of frequency synthesizers. [ABSTRACT FROM PUBLISHER]

This paper describes and analyzes \ IM_3 asymmetry issues for weakly nonlinear MOSFET Common-Gate(CG) and Common-Source(CS) architectures. Using a Volterra series analysis, the cause of \ IM_3 asymmetry in CG and CS amplifiers is explained. The asymmetry between high-side and low-side \ IM_3 products in the CG amplifier exhibits a larger amplitude difference at low-frequency offset than at high frequency offset, while the CS amplifier shows more asymmetry at a high frequency offset. The magnitude of the \ IM_3 product asymmetry in the CS amplifier can be significantly higher than the CG amplifier. Methods of mitigating \ IM_3 asymmetry are suggested for both CG and CS amplifiers. A 65 nm Si CMOS technology is used for the simulation verification of the results derived in this paper. [ABSTRACT FROM PUBLISHER]

This paper presents the analysis and design of a quadrature charge-domain down-conversion sampling mixer with embedded finite-impulse-response (FIR), infinite-impulse-response (IIR), and 4-path bandpass filters. An in-depth investigation of the principles of periodic impulse sampling, periodic windowed sampling, and periodic N-path windowed sampling is presented and their characteristics are compared. A detailed mathematical treatment of charge-domain windowed samplers with built-in sinc, FIR and IIR filters is provided. A quadrature charge-domain sampler with embedded FIR, IIR, and 4-path band-pass filters is proposed and its performance including the effect of the non-idealities of devices is investigated. The proposed design is implemented in an IBM 130 nm 1.2 V CMOS technology. Simulation results demonstrate that the proposed design is tunable over 50–250 MHz frequency range. For an 100 MHz input, the proposed design exhibits 70 dB aliasing rejection, 60 dB stop band attenuation while consuming current of 145 \muA. The performance of the proposed design is further validated using the results of on-wafer measurement of the fabricated microchip. [ABSTRACT FROM AUTHOR]

This paper presents a high-efficiency 60-GHz on-off keying (OOK) demodulator for high-speed short-range wireless communications such as wireless network-on-chip (WiNoC) applications. Targeting at data rates of beyond 16 Gb/s, the OOK demodulator consists of a wideband envelope detector (ED) and a single-stage baseband (BB) peaking amplifier. Novel dual gain-boosting techniques improve the gain, bandwidth, and out-of-band rejection of the ED. In addition, an actively-enhanced tunable inductor (AETI) load in the BB amplifier not only significantly reduces its area overhead, but also provides a tunable peaking level. Fabricated in a 65-nm bulk CMOS process, the OOK demodulator consumes only 4.6 mW from a 1-V supply, and occupies an active area of 0.043 mm^2. A maximum data rate of 18.7 Gb/s with a bit-error rate less than 10^-12 is demonstrated through measurements, which translates to a bit-energy efficiency of 0.25 pJ/bit. [ABSTRACT FROM AUTHOR]

It has been studied that, an N-path switched-capacitor (SC) branch driven by an N-phase non-overlapped local oscillator (LO), is equivalent to a tunable parallel-RLC tank suitable for radio-frequency (RF) filtering. This paper proposes a gain-boosted N-path SC bandpass filter (GB-BPF) with a number of sought features. It is based on a transconductance amplifier (Gm) with an N-path SC branch as its feedback network, offering: 1) double RF filtering at the input and output of the Gm in one step; 2) customized passband gain and bandwidth with input-impedance match; and 3) reduced physical capacitance thanks to the loop gain offered by Gm. All have been examined using a RLC model of the SC branch before applying the linear periodically time-variant (LPTV) analysis to derive the R, L, and C expressions and analytically study the harmonic selectivity, harmonic folding, and noise. The latter reveals that: 1) the noise due to the switches is notched at the output, allowing smaller switches to save the LO power and 2) the noises due to the source resistance and Gm are narrowband at the output, reducing the folded noise during harmonic mixing. To study the influence of circuit non-idealities, an intuitive equivalent circuit model is also proposed and verified. The design example is a four-path 0.5–2-GHz GB-BPF simulated with the 65-nm CMOS. It exhibits >11 dB gain, <2.3 dB NF, and +21-dBm out-of-band IIP3 at 150-MHz offset, while consuming just 7 mW of power. [ABSTRACT FROM PUBLISHER]

This paper presents a new ADC architecture called partially active flash ADC. A 10 GS/s 6 b four-way time-interleaved ADC prototype in 65 nm CMOS demonstrated that this new ADC architecture offers better power efficiency than traditional ADC architectures in the \geq10 GS/s speed range. Various considerations towards high-speed ADC designs are discussed including a proposed source-follower based boot-strap track-and-hold circuit to reduce input kickback and improve the ADC bandwidth. Also discussed is the generation and skew calibration of the four-phase clocks for the interleaved channels to improve the ADC effective resolution at high input frequencies. By deriving the four-phase clocks from a Nyquist frequency input clock through pass gates, accurate timing skew calibration is achieved through a simple duty-cycle correction. Measured SNDR is 34.3 dB at low input frequencies and 32.0 dB at the Nyquist input frequency. The ADC including the input clock buffer consumes 83 mW with a FOM of 197 fJ/cs. [ABSTRACT FROM AUTHOR]

This paper describes a 10-Gb/s clock-and-data recovery (CDR) with a background optimum loop-bandwidth calibrator. The proposed CDR automatically achieves the minimum-mean-square error between jittery input data and the recovered clock signal by adjusting the bandwidth of a CDR using Kalman filtering theory. A testchip is fabricated in a 0.11 \mum CMOS process and the adaptive optimum loop-bandwidth calibrator is implemented via an off-chip micro controller unit. The testchip recovers clock and data with a bit error rate of less than 10^-13 while consuming 82 mW at 10-Gb/s. [ABSTRACT FROM AUTHOR]

This paper presents a power and area efficient approach to embed a continuous-time linear equalizer (CTLE) within a clock and data recovery (CDR) circuit implemented in 65-nm CMOS. The merged equalizer/CDR circuit achieves full-rate operation up to 28 Gb/s while drawing 104 mA from a 1-V supply and occupying 0.33 mm2. Current-mode-logic (CML) circuits with shunt peaking loads using customized differential pair layout are used to maximize circuit bandwidth. To minimize the area penalty, differential stacked spiral inductors (DSSIs) are employed extensively. A novel and practical methodology is introduced for designing DSSIs based on single-layer inductors provided in foundry process design kits (PDK). The DSSI design increases the inductance density by over 3 times and the self-resonance frequency by 20% compared to standard single-layer inductors in the PDK. The measured BER of the recovered data by the CDR is less than 10-12 at 27 Gb/s for 211-1 400 mV PP pseudo-random binary sequence (PRBS) as input data. The measured rms jitter of the recovered clock and data are 1.0 and 2.6 ps, respectively. The CDR is able to lock to inputs ranging from 26 to 28 Gb/s with 29-1 PRBS pattern. Measurement results show that with the equalizer enabled, the CDR can recover a 26-Gb/s 27-1 PRBS data with BER ≤ 10-12 after a channel with 9-dB loss at 13 GHz. [ABSTRACT FROM AUTHOR]

This paper presents a fully implantable 100-channel neural interface IC for neural activity monitoring. It contains 100-channel analog recording front-ends, 10 multiplexing successive approximation register ADCs, digital control modules and power management circuits. A dual sample-and-hold architecture is proposed, which extends the sampling time of the ADC and reduces the average power per channel by more than 50% compared to the conventional multiplexing neural recording system. A neural amplifier (NA) with current-reuse technique and weak inversion operation is demonstrated, consuming 800 nA under 1-V supply while achieving an input-referred noise of 4.0 \muVrms in a 8-kHz bandwidth and a NEF of 1.9 for the whole analog recording chain. The measured frequency response of the analog front-end has a high-pass cutoff frequency from sub-1 Hz to 248 Hz and a low-pass cutoff frequency from 432 Hz to 5.1 kHz, which can be configured to record neural spikes and local field potentials simultaneously or separately. The whole system was fabricated in a 0.18-\mu\ m standard CMOS process and operates under 1 V for analog blocks and ADC, and 1.8 V for digital modules. The number of active recording channels is programmable and the digital output data rate changes accordingly, leading to high system power efficiency. The overall 100-channel interface IC consumes 1.16-mW total power, making it the optimum solution for multi-channel neural recording systems. [ABSTRACT FROM PUBLISHER]

This paper presents three compact CMOS voltage-to-current converters based on OTA/common-source configurations, which attain rail-to-rail input-output operation. The three converters present a high impedance input node while provide a highly linear V-I relationship over a (-40, +120^\circC) temperature range with a maximum transconductance temperature coefficient of 175 ppm/^\circC. Measurement results for 1.2-V 0.18-\mum CMOS implementations confirm rail-to-rail operation with bandwidths of up to 14.5 MHz and THD of up to -50 dB for 1 Vpp at 100 kHz, active areas below 0.0145 \mum^2 and power consumption below 85 \muW, which make these basic building blocks suitable for portable applications. [ABSTRACT FROM PUBLISHER]

In this paper, a switched load harmonic rejection mixer (HRM) structure with one single mixer core and a pair of switched load resistors is proposed. Different from the traditional three-phase HRM which is widely used in DTV tuners, this HRM performs the harmonic rejection function by vector multiplication rather than superposition. Sharing most of its parts with an ordinary Gilbert mixer, the proposed HRM shows greater simplicity in structure. The single mixer-core structure is also more power efficient than a traditional three-phase HRM. In order to verify the effectiveness of this approach, a proof-of-concept prototype is designed and fabricated in 0.18-\mum RFCMOS technology. Measurements indicate that 38 dB for 3rd and 34.5 dB for 5th harmonic rejection ratio can be achieved. The HRM including a buffer stage consumes a low bias current of 3 mA under 1.8 V supply voltage and has equivalent performance such as CG, NF, and IIP3 to an ordinary Gilbert mixer. With the load switch inactivated, this HRM can be easily transformed into an ordinary Gilbert mixer, which increases its flexibility for different applications. [ABSTRACT FROM AUTHOR]

This paper proposes a 3rd order single-loop continuous-time incremental sigma-delta analogue-to-digital converter (ADC) for time-multiplexed signals. Incremental sigma-delta modulation is used to address medium to high resolution requirements of multi-channel applications, while a 3rd order continuous-time implementation is investigated as an alternative for low-power solutions. A prototype of the proposed modulator, running at 320 kHz, has been fabricated in a 0.15-\mum CMOS technology, while the synchronization circuitry to allow incremental operation was built on-board. Measurement results show that the ADC achieves 65.3 dB peak SNR, 64 dB peak SNDR and 68.2 dB dynamic range over a 2 kHz bandwidth. The modulator's power dissipation is 96 \muW from a 1.6 V power supply. This translates into the best figure-of-merit when compared to recently published continuous-time alternatives, while being competitive with respect to state-of-the-art discrete-time counterparts. [ABSTRACT FROM AUTHOR]

This paper presents a general analysis of peaking methods in output stages of amplifiers for broadband communication systems. It is shown that common peaking methods, although providing significant signal bandwidth enhancement ratios (BWER), are limited to 30%–50% of their speed potential by output matching requirements. A modified T-coil peaking is analyzed which enhances both signal bandwidth and output matching frequency range by up to 200% compared to common peaking methods. A broadband amplifier using this inductive output matching with 69-GHz bandwidth implemented in a 0.25~\mu \m SiGe BiCMOS technology is presented to prove the validity of the analysis. [ABSTRACT FROM PUBLISHER]

This paper presents a low power radio design tailored to the short distance, low data rate application of body area networks. In our analysis we consider a comparison between traditional continuous wave radios and ultra wide band impulse radios for this application space. We analyze the energy/bit requirement for each of the architectures and discuss how a duty-cycled radio is better suited to low data rate applications due to practical design considerations. As a proof-of-concept we present the design and measured results of a duty-cycled, noncoherent impulse radio transceiver. The designed transceiver was measured to consume only 19 \mu \W at a data-rate of 100 kbps. The design gives a BER of 10 ^-5 and works for a range of 2.5 m at an average Rx-sensitivity of -81~\dBm. The designed transceiver enables both OOK and BPSK schemes and can be configured to use a pseudocoherent self-correlated signature detection and generation mechanism. This added functionality helps distinguish different types of pulses such as timing and data-pulses in real time. The transceiver was designed in a 90 nm CMOS process and occupies 2.3 \mm^2 area. [ABSTRACT FROM PUBLISHER]

This paper presents an automatic within-pair skew compensator for high-speed differential data transmission. A wide-bandwidth data delay line is proposed to provide adjustable delay for data signals. Also presented is an on-chip within-pair skew detection circuit to detect skew between the differential data signals for automatic close-loop skew compensation. A within-pair skew compensator prototype for 5 Gb/s data was fabricated in 0.13 \mu\m CMOS. Measurement results show that the within-pair skew compensator can automatically compensate for within-pair skew of \pm200 ps (\pm1 unit interval). It consumes 20.4 mW from 1.2 V supply and occupies 0.015 \mm^2 die area. [ABSTRACT FROM PUBLISHER]

This paper discusses the circuits and system design methodology of a highly-efficient wideband RF polar transmitter (TX) using the envelope-tracking (ET) technique for mobile WiMAX applications. Monolithic power amplifiers (PAs) are designed and fabricated in IBM 0.18 \mum SiGe BiCMOS technology, and a linear-assisted switch-mode envelope amplifier is applied to modulate the PA supply voltage to form the core of the RF polar TX. Nonlinearities caused by bandwidth limitation of the envelope amplifier and timing misalignment have been investigated. When driven by WiMAX 64QAM 8.75 MHz signals, the overall PAE of our ET-based polar TX system reaches 30.5% at 17 dBm average output power, while also meeting the stringent WiMAX linearity specs without using any predistortion. When the decresting algorithm using the soft limiter is applied to the baseband, the overall PAE increases to 33%, at the expense of a higher EVM of 4.9%. Based on measurement results, our ET-based polar TX system has demonstrated excellent efficiency with good linearity for high peak-to-average ratio (PAR) broadband signals when compared with the recent literature on state-of-the-arts polar TX designs. [ABSTRACT FROM PUBLISHER]

This paper presents a sub-Nyquist rate sampling receiver architecture that exploits signal sparsity by employing compressive sensing (CS) techniques. The receiver serves as an analog-to-information conversion system that works at sampling rates much lower than the Nyquist rate. A parallel-path structure that employs current mode sampling techniques is used. The receiver performance is quantified analytically. Useful and fundamental design guidelines that are unique to CS are provided based on the analytical tools. Simulations with a 90-nm CMOS process verify the theoretical derivations and the circuit implementations. Based on these results, it is shown that an instantaneous receiver signal bandwidth of 1.5 GHz and a signal-to-noise-plus-distortion ratio of 44 dB are achievable. The receiver power consumption is estimated to be 120.8 mW. A comparison with state-of-the-art high-speed analog-to-digital conversions reveals that the proposed approach improves the figure of merit by a factor of three if the signal exhibits a 4% sparsity. [ABSTRACT FROM PUBLISHER]

This paper presents an optical receiver with a monolithically integrated photodetector in 0.18-\mu\m CMOS technology using a combination of spatially modulated light (SML) detection and an analog equalizer. A transimpedance amplifier employing negative Miller capacitance is introduced to increase its bandwidth without causing gain peaking. To provide sufficient reverse-bias voltage to the photodetector's p-n junction, the transimpedance amplifier is operated with a 3.3-V supply, while the rest of the circuit blocks is powered with a 1.8-V supply. The on-chip SML detector achieves a net responsivity of 0.052 A/W. Occupying a core area of 0.72 \mm^2, the fully integrated optical receiver achieves 4.25 and 5 Gbits/s with power consumption values of 144 and 183 mW, respectively. [ABSTRACT FROM PUBLISHER]

This paper presents a new high-gain structure for the distributed amplifier. Negative capacitance cells are exploited to ameliorate the loading effects of parasitic capacitors of gain cells in order to improve the gain of the distributed amplifier while keeping the desired bandwidth. In addition, the negative capacitance circuit creates a negative resistance that can be used to increase the amplifier bandwidth. Implemented in 0.13-\mum IBM's CMRF8SF CMOS, the proposed six-stage distributed amplifier presents an average gain of 13.2 dB over a bandwidth of 29.4 GHz. The measured input return loss is less than -9 dB and the output return loss is less than -9.5 dB over the entire bandwidth. With a chip area of 1.5 mm\,\times\,0.8 mm, the amplifier consumes 136 mW from a 1.5-V dc power supply. [ABSTRACT FROM PUBLISHER]

A 10-GBd 40-Gb/s coherent optical transport is a promising technology for higher data rate communications by virtue of improved sensitivity and high spectrum efficiency. One of the major challenges in designing a 40-Gb/s coherent quadrature-phase-shift-keying receiver is to achieve high-speed data conversion at around 20-GHz sampling rate with at least 5-bit resolution. With the detailed design framework for the target requirements, this paper presents a 5-bit 20-GS/s flash analog-to-digital converter (ADC) realized in 0.18-\mu\m SiGe BiCMOS technology. The ADC includes a track-and-hold amplifier (THA) incorporated with linear distortion compensation, double-interpolation preamplifier, current bias-weighted comparator, and high-speed encoder logic. At 4 V, the THA had a bandwidth that exceeded 23 GHz and an IIP3 of 24 dBm. The ADC achieves a signal-to-noise-plus-distortion ratio of 28.6 dB and a spurious-free dynamic range of 36 dB with a 1-GHz input sinusoid sampled at 20 GS/s. The ADC has a wide resolution bandwidth of 7 GHz, and the figure of merit is 9.54 pJ/conversion-step. The ADC consumes 3.24 W from 4- and 3-V supplies when sampled at 20 GHz. The prototype ADC occupies 8.68 \mm^2 of silicon area. [ABSTRACT FROM PUBLISHER]

As technology pushes deeper into the nanoscale, the difficulty in developing high-performance analog functions has driven an explosion in digitally intensive architectures to replace them. Commonalities among these new architectures include a paradigm shift toward temporal versus voltage encoding of analog signals, and the extensive use of digital calibration. In particular, recent developments in fractional-N all-digital phase-locked loops (ADPLLs) have proven them to be competitive with analog state of the art for narrowband applications, demonstrating excellent phase noise and achieving even traditionally difficult standards such as GSM. However, to achieve comparable high performance for wideband applications requires a reduction in fractional spurs. This paper provides a brief summary of ADPLL architectures, leading to a prototype synthesizer at 3 GHz which implements a spurious tone reduction technique. Along the way, an efficient simulation model to predict fractional spur amplitude and frequency in ADPLLs is presented. The 3 GHz prototype operates from a flexible reference frequency, between 25 MHz–100 MHz, has in-band phase noise of -101 dBc/Hz with a decade of loop bandwidth programmability, and in-band spurs below -45 dBc. The synthesizer occupies 0.4 \mm^2 in 65 nm digital CMOS and consumes less than 10 mW from a 1.2 V supply. [ABSTRACT FROM PUBLISHER]

Time analog-to-digital converters (TADs) based on the power-supply voltage dependence of CMOS gate propagation delay time can be constructed solely of CMOS digital circuits and are characterized by output of the time integral of input voltage, with no dead time. This paper describes digital quadrature detection (DQD) by TAD (TAD-DQD). With TAD-DQD, the in-phase and quadrature components of the input signal, including amplitude and phase information, can be obtained simply by adding and subtracting AD-converted TAD output using a sampling frequency that is four times the carrier frequency of the target signal. As an example of the application of TAD-DQD, the standard-time and frequency-signal receiver circuits of a radio-controlled clock/watch are shown, and the experimental results demonstrate that the time code can in fact be received. [ABSTRACT FROM AUTHOR]

Analog domain true-time-delays (TTD) are desired in hybrid beamforming receivers with large relative bandwidths to mitigate the problem of beam squint. We propose a true-time-delay beamforming receiver architecture which enables squint-free wideband spatial filtering prior to the A/D conversion. The receiver implements true-time-delay with delayed re-sampling of the discrete-time output of a passive mixer. The receiver has the capability to extend the range of the beamforming delays from one to several carrier periods of the RF signal with pulse-skipped local oscillator (LO) signals, thereby enabling TTD beamforming with large antenna arrays. Further, a polyphase structure with parallel mixers is proposed to prevent spectral aliasing resulting from the lowered sample rate of the pulse-skipped LO signals. In addition, the maximum beamforming delay scales with the LO frequency, supporting large arrays also at low frequencies where the antenna separation set by the wavelength is large. We verify the proposed concepts with transistor-level simulation of the receiver implemented with a 28-nm CMOS process. The design achieves a squint-free beamforming for a 400 MHz RF bandwidth, and a maximum beamforming delay of three carrier time periods. The power consumption for a 3 GHz carrier frequency is 4 mW per antenna. [ABSTRACT FROM AUTHOR]

An active transmitter self-leakage suppressor for frequency-division duplex transceivers is presented. A wideband active notch filter is implemented at the mixer IF ports to suppress out the transmitter leakage. Since the active notch filter is operating at IF frequencies, its noise, power, and area consumption penalty for the overall transceiver is negligible, and it does not require any complicated amplitude and phase calibration circuitry that is necessary for the cancelers which operate at RF frequencies. Due to the transfer function seen by the active notch-filter, its noise and distortion contribution is shaped and reduced further. The proposed design is implemented in a 65 nm standard CMOS process for an LTE receiver and provides minimum of 5 dB attenuation at duplex distance for E-UTRA band 20. For the same frequency band, it enhances the IIP2 and IIP3 of the receiver with a minimum of 12 and 6 dB, respectively. The active filter consumes only 1.1 mA/channel from a 2.5 V supply and occupies 0.078 mm2/channel. Its noise contribution is within the NF measurement error, thus negligible. The design is intended and tested for transmitter self-interference and wideband ACS blockers. [ABSTRACT FROM AUTHOR]

An inductorless 10-Gb/s optical receiver including a novel transimpedance amplifier (TIA) with dual feedback loop and a limiting amplifier with third-order nested feedback is presented. The current-buffer-based TIA employs an active Cherry-Hooper stage in the auxiliary amplifier and reuses the tail current source to achieve 10 Gb/s operation in the presence of a 1 pF photodiode input capacitance. Systematic analysis and design methodology of the double loop TIA is given with simple design equations derived for optimizing the performance of each loop. The use of nested feedback in the four stage limiting amplifier enables a gain-bandwidth-product >1 THz without the use of on-chip inductors. It is shown that the proposed limiting amplifier circuit enhances bandwidth by utilizing inherent equalization between the overdamped and underdamped poles. Implemented in IBM 130-nm CMOS technology, the optical receiver achieves a BER $<10^{-12}$ at 10 Gb/s for an input current of $30\,\,\mu \text{A}_{\mathrm{ p-p}}$ in electrical measurement, delivering 600 mV $_{\mathrm{ p-p}}$ at the output of the 50- $\Omega $ buffer. Optical testing confirmed −17.4 dBm sensitivity for a data rate of 7.5 Gb/s, which is limited by the maximum speed of the 850-nm source available at the time of measurement. The receiver dissipates 108 mW from 1.2-V supply (excluding the output buffer) and occupies a core area of only 0.08 mm2. [ABSTRACT FROM AUTHOR]

We introduce a first principles, end-to-end analysis of opto-electronic communication links which incorporates a thorough model of the receiver circuitry, in addition to the more familiar laser transmitter optimization. In particular, we optimize receiver sensitivity and power by studying their dependence on front-end design as well as follow-on digital sampler requirements. We find that the photo-receiver sensitivity is the most important factor in controlling the overall link power consumption. Our physical model and circuit optimization principles are applied to a heterogenous-integrated photonic+CMOS platform, where we show state-of-the-art performance through this physics-based rapid-design protocol. Incidentally this greatly simplifies the design process. Lastly, we apply this approach to extrapolate future performance trends, platform bottlenecks, and fundamental limits in optical link design while showcasing the potential for sub-1fJ/bit system efficiency at high speeds. [ABSTRACT FROM AUTHOR]

Bench characterization of wide band oversampled converters is a challenge due to the high data rate at the output of the modulator. We propose the use of a duobinary test interface to extend the frequency range over which reliable laboratory measurements become possible. We show that using such an interface effectively randomizes the modulator output data and reduces high frequency content, thereby reducing the bandwidth demands made on the test equipment. It also reduces degradation of the modulator performance caused by package feedthrough effects. Experimental results from a test chip in 90 nm CMOS show that the proposed interface extends the upper sampling frequency limit of an existing single-bit CTDSM from 3.6 GHz to 4.4 GHz. [ABSTRACT FROM AUTHOR]