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To meet the requirements of low cost, thin vehicles, and multiple functions, the fan-out panel-level packaging (FO-PLP) is introduced to be one of the next-generation packaging technologies. However, the warpage issue of FO-PLP remains a critical concern during temperature cycling manufacturing processes. The utilization of finite-element analysis (FEA) to estimate the warpage of FO-PLP and to address the major mechanism of warp-induced failure is therefore crucial. Given that an increase in the structural complexity of packaging follows the advancement in technological development, the effect of redistribution layer (RDL) on packaging warp considered in FEA becomes greatly difficult. The complicated RDL might cause computational bottlenecks. For this reason, several equivalent material approaches composed of composite theory and simulation-based material testing approach are proposed and compared with resolve the abovementioned problem. The gravity effect is considered in the present process-oriented FEA to acquire accurate warpage. To perform the foregoing FEA, identifying how to determine the equivalent reference temperature at each step of manufacturing process is the key. In this article, three methods, namely, zero deformation approach, force equilibrium approach, and modified Timoshenko bimaterial approach, are proposed. To validate these methods, a comparison of warpage between the experimental measurement and simulation is conducted. The analytic results demonstrate that the modified Timoshenko approach has the best ability to evaluate the warpage of RDL-first FO-PLP among them due to the feasible assumption for the actual mechanical behavior of warpage. With regard to the extraction of equivalent material, the results indicate that the simulation-based material testing approach is more suitable to obtain the equivalent RDL. The estimated warpage has only a 0.9% deviation between the simulation and experiment when the modified Timoshenko bimaterial approach combined with the simulation-based material testing approach is adopted. Consequently, the RDL-induced warpage in FO-PLP can be accurately estimated through the presented simulation methodology. [ABSTRACT FROM AUTHOR]

An analytical model for the precise stress estimation of device channels is developed and demonstrated in this article. The resultant stress magnitude under considered stress resources, including strained source/drain (S/D) and intrinsic stressed shallow trench isolation (STI), is carefully predicted and compared. The calculated accuracy of the presented model is validated through finite element simulation by a given example of the Si/SiGe material system arranged in S/D local regions and surrounded in the STI field. The rapid prognosis ability of the proposed model is performed on Si, Ge, and group III–V channels of nano-scaled transistors under specifically designed stressors. The S/D dependence of performance variety for all considered device materials can be directly estimated by changing the designed S/D length substituted into the analytical model. Moreover, the variations in induced mobility gain are further quantified using stress-piezoresistance relation. The analytic results indicate that the strained Ge pMOSFET outperforms other strained devices, such as Si and In0.53Ga0.47As channel materials, while identically designed strained level resulting from the lattice mismatch of S/D stressors is considered. Furthermore, the unstrained GaAs-based nMOSFET integrated with lattice-matched S/D Ge, indicating its superior electron mobility as compared with the S/D strained Si and Ge nMOSFETs owing to its advanced initial mobility. Accordingly, the systematically analytic flow of stress-induced device performance prediction is demonstrated via the present analytical solution integrated with corresponding piezoresistance models. [ABSTRACT FROM AUTHOR]

This paper presents a new method of reactive-combiner structure to be used as part of a multiphase digital pulsewidth modulated polar transmitter (DPWMPT). It overcomes the limitations of previous implementations of the multiphase pulse-modulated polar transmitter related to terminating pulsewidth modulation (PWM) harmonics located outside the passband, thereby improving both PWM harmonic suppression by using multiphase aliasing-free digital PWM technique and increasing overall efficiency by using reactive combining. For validation, a prototype transmitter was implemented and tested with a 64-QAM 20-MHz bandwidth long-term evolution (LTE) downlink signal with a 7.5-dB peak-to-average power ratio at 2140 MHz. The prototype dual-phase DPWMPT architecture achieved an output power level of 37 dBm and power-added efficiency of 33.5% while passing the stringent spectral requirements of the LTE standard for small-cell base stations using only simply memoryless predistortion correction. [ABSTRACT FROM AUTHOR]

The stress distributions and induced mobility gain in germanium (Ge)-based p-type MOSFETs (pMOSFETs) with an extended channel width are estimated in this paper. Several tin (Sn) concentrations of group-IV semiconductor GeSn alloys integrated with a compressive contact etching stop layer (CESL) are logically analyzed to evaluate the stress impact that results from the high lattice mismatch of embedded GeSn alloys on narrow device channels. Analytic results show that the stress intensity and corresponding mobility gain are enhanced by increasing the Sn concentration in the embedded source/drain GeSn stressors. By contrast, the performance variation of the short-channel Ge-based pMOSFET is strongly dominated by the extended width when the CESL covers the entire device. A mobility gain of up to ~124.07% is achieved for the 22-nm pMOSFET when a 100-nm extended width is considered. Moreover, the entire stress responses of high- ${k}$ /metal gate-last procedure combined with the following CESL deposition are investigated. Analytic results reveal that the stress relaxation along the channel height direction occurs after the poly gate etch process. Consequently, the adoption of a stressed CESL is demonstrated to be an effective approach to remedy the device mobility gain by stress improvement on the channel height direction. [ABSTRACT FROM AUTHOR]

In this paper, the characteristic of the amorphous indium–gallium–zinc-oxide thin-film transistors under steady bias and fast multiple-pulse illumination stress is analyzed. The change in the drain current ( \Delta ID ) with respect to time is measured under different light intensities and pulse frequencies. The mechanism is proposed to explain the results by correlating the oxygen vacancy ( VO ) reacting with the light-induced electron–hole (e-h) pairs. The results can be well analyzed by the fitting formula and parameters for the different light pulse frequencies. The tendency proves that not all the VO react with e-h pairs at the same reaction rate. It is observed for the first time the number of VO with fast reaction decreases with the pulse frequency. A model is proposed to describe the relation between the number and reaction rate of VO . [ABSTRACT FROM PUBLISHER]

Cooperative localization has been proved to effectively outperform single-robot localization. While most of the state-of-the-art multi-robot localization systems either treat moving objects as outliers or accomplish moving object tracking separately from localization, we argue that augmenting moving objects into the localization estimation can further enhance localization performance and is indeed the key to solve several localization challenges such as insufficient map features, no map features, and symmetric maps. In this paper, a multi-robot simultaneous localization and tracking (MR-SLAT) algorithm based on the extended Kalman filter is proposed, and multiple hypothesis tracking (MHT) is integrated into MR-SLAT for dealing with challenging data association issues. The proposed approach is verified in two scenarios: the NAO humanoid robots equipped with cameras and WiFi are used in the RoboCup scenario and the robotic vehicles with laser scanners and dedicated short-range communications (DSRC) are used in the traffic scenario. The experiments with ground truth show that MR-SLAT, by exploiting moving objects, is superior to single-robot localization and cooperative localization in challenging scenarios. Ample experimental and simulation results demonstrate the effectiveness of exploiting moving objects and the generality and feasibility of the proposed MR-SLAT algorithm. [ABSTRACT FROM AUTHOR]

The pulse-modulated polar transmitter (PMPT) uses envelope information to pulse modulate phase information to implement highly linear and highly efficient polar transmitters. Previous implementations of the PMPT successfully achieved bandwidths up to 5 MHz. However, as the bandwidth of the signal increases, nonidealities of the PMPT limit the performance of this architecture. The nonidealities are predominantly aliasing from pulsewidth modulation (PWM) and distortions from switching, which degrade the spectral performance. By using aliasing-free digital PWM and digital pre-distortion concurrently, spectral performance of the PMPT can be improved for wide bandwidth applications. For validation, a prototype transmitter was tested with a 20-MHz bandwidth downlink long-term evolution (LTE) signal at 836.5 MHz. Using the proposed method, the prototype transmitter achieved an output power of 19.8 dBm and drain efficiency of 24.4% while passing the spectral requirements of the LTE standard for femtocell base stations. [ABSTRACT FROM AUTHOR]

This paper presents a wideband power recycling technique for pulse-modulated polar transmitters (PMPTs). The technique allows unwanted out-of-band modulation spurs in PMPTs to be rectified and recovered back to the power supply for efficiency improvement. By configuring the power amplifiers as a balanced amplifier with dual-phase digital pulse-width modulation, the odd modulation spurs can be extracted directly from the isolation port of the output-combining quadrature coupler. Using the proposed architecture, the prototype transmitter achieved 59.1% drain efficiency at an output channel power of 26.2 dBm using a 10-MHz bandwidth long-term evolution 16-quadrature amplitude modulation test signal at 836.5 MHz. After output signal restoration by a surface-acoustic-wave filter, an output power level of 24.8 dBm and 42.8% drain efficiency were achieved while passing the spectral and receive-band-noise requirements without using any digital pre-distortion techniques. [ABSTRACT FROM AUTHOR]

Run-to-Run control algorithms for high-mix semiconductor processes typically require that the initial product state estimates have sufficient accuracy for satisfactory control. In this paper, we use historical process data and apply single observation just-in-time adaptive disturbance estimation (JADE) to find the initial product state estimates. Single observation JADE with random selection, high-frequency sampling, and exclusion of the earliest data from the average is shown to provide satisfactory initial product state estimates. The effect of initial state estimate accuracy is demonstrated by several simulation and industrial data examples. We also provide a method to estimate relative confidence between individual product state estimates, information that may be used to determine assignment of process error between the tool and product state. [ABSTRACT FROM AUTHOR]

The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (Vth) roll-off characteristics at supply voltage (VDD) 1 V. Analyses of electron density and electric field distributions in on-state and off-state also show that the JL devices have better on–off current ratios. Regarding design aspects, the effects of channel doping concentration (Nch) and Fin height (H)/width~(W) on device Vth are also compared. In addition, the Vth of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (Nsub). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (tHL) and low-to-high delay time (tLH) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application. [ABSTRACT FROM AUTHOR]

A 3-D finite-difference time-domain (FDTD) scheme with controllable stability beyond the stability limit of FDTD is presented. The key to controlling the FDTD stability limit is a spatial filter applied to the electromagnetic field vectors in order to ensure that unstable spatial harmonics are eliminated. A significant advantage of this approach is the simplicity of its incorporation into existing FDTD codes. Moreover, this method is employed as a means to implement a late-time stable 3-D sub-gridding scheme. Applications include waveguide filters and the analysis of screens for near-field sub-wavelength focusing at microwave frequencies. [ABSTRACT FROM PUBLISHER]

3-D integration provides a promising approach for the construction of complex microsystems through the bonding and interconnection of individually optimized device layers without sacrificing system performance. The use of traditional underfill processes is expected to face an arduous challenge as the filled gap of a large-scale chip is narrowed down to several micrometers. Consequently, the subsequent reliability of microbumps (\mu-bumps) joints and the relative assembly compatibility of stacked chips of 3-D IC packages deteriorate. To resolve this critical issue, a novel technology for wafer-level underfill film (WLUF) is developed. This paper demonstrates the steps that the proposed technology would take. These steps include the alignment of the WLUF-coated chip to the substrate chip and the elimination of voids to make the proposed technology work. However, the coplanarity of stacked thin chips after assembling with the WLUF, is an urgent problem that needs to be understood in detail. Therefore, this paper presents a nonlinear finite element analysis (FEA) using a process-oriented simulation technique to estimate the warpage of stacked thin chips. For experimental validation, the effects of several key designed factors on the thermomechanical behavior of chip-on-chip package under various bonding forces are investigated. The analytic results indicate that a chip thickness of <50∼\mum at the outermost region of the packaging structure without \mu-bumps significantly reduces approximately 2 \mum of gap between chips. This phenomenon is attributed to the major structural support at the purlieus of the chip via WLUF, which is extremely weak when a uniform bonding pressure is loaded. In addition, the subsequent cooling procedure of the WLUF further aggravates the warpage magnitude of the stacked thin chips. The results of this paper could serve as a guideline for further improvement of the bonding reliability and for the design of the structural optimization of packaging assemblies via the WLUF. [ABSTRACT FROM AUTHOR]

A wheeled human-conveyance vehicle (WHCV) with a low-level microprocessor is realized in this paper. WHCVs are environmentally friendly short-range transportation vehicles. This paper proposes a simple Mamdani-like fuzzy controller for self-balancing WHCV control. System stability is guaranteed by establishing sufficient conditions based on the Lyapunov stability analysis. Finally, experimental results show that the proposed Mamdani-like fuzzy control strategy can control the WHCV. [ABSTRACT FROM PUBLISHER]

Run-to-run (RtR) control is an important method for improving process capability. The most common form of RtR controllers are exponentially weighted moving average (EWMA) controllers. The performance of EWMA RtR controllers is affected by the values of the selected tuning parameter. In practice, the tuning parameter usually remains unchanged, resulting in suboptimal performance. In this paper, we propose an adaptive-tuning method for a group and product (G&P) EWMA controller to improve the control performance. The G&P EWMA controller is developed for mixed run processes. We show that the optimum-tuning parameters for the next run of this G&P EWMA controller are obtained online using a window of historical input–output data. The performance improvement due to the proposed method is demonstrated by a simulation example and an industrial application. [ABSTRACT FROM PUBLISHER]

Microcystis aentginosa (MA), which is one kind of cyanobacteria, is the primary algal species in Taihu Lake. The MA bloom has a significantly negative effect on the human health and water environment ecosystem. The monitoring and prediction of MA bloom become more and more critical for the security of drinking water source and environment in the Taihu Lake area. In this paper, the percentage of MA was estimated from remote-sensing reflectance via a novel spectral shape genetic optimization algorithm. This algorithm focuses on the shape of remote-sensing reflectance, and it can remove the influence of the amplitude of remote-sensing reflectance from the retrieval result. The accuracy of this optimization algorithm is acceptable according to both simulated and in situ data. The percentage of mean square root (RMSP) of the percentage of the phytoplankton absorption coefficient to the total absorption coefficient at 440 nm [ar (440 nm)] between the retrieved and the simulated is 18.39%. The RMSP of the total absorption coefficient at 440 nm [a (440 nm)] between the retrieved and the simulated is 3.65%. The RMSP of the percentage of MA [Sf] between the retrieved and the simulated is 13.60%. The RMSP of the colored dissolved organic matter (CDOM) absorption coefficient slope [S] between the retrieved and the simulated is 5.89%. The RMSP of the particle backscatter coefficient slope [Y] between the retrieved and the simulated is 30.46%. In Taihu Lake, the RMSPs of ar (440 nm), a (440 nm), Sf, and S between the retrieved and the measured are 36.59%, 35.70%, 19.25%, and 16.80%, respectively. The retrieved percentage of MA (Sf) and Scenedesmus obliquus  (1 - Sf) by this model from August 2006, October 2006, to November 2008 indicates the variation trend of algal species in different seasons. This trend accords with the results from previous studies and observations. This paper extends and advances the previous retrieval methods and confirms that the genetic optimization algorithm can be used to retrieve the information of water constituents in the high turbid and eutrophic inland water mass. [ABSTRACT FROM PUBLISHER]

Tilt and decenter errors in lenses are usually caused by lens manufacturing processes: either injection or glass molding. This paper presents an image polarization method for measuring tilting and decentering of lenses. We placed a sample lens between two linear polarizers and passed either a focused or a divergent polarized beam through a half-wave or a full-wave plate. If any error were present in the shape of the lens, patterns and colors shown in the image of polarization would be altered. Finally, the degree of error in the shape of the lens can be computed using image processing software. [ABSTRACT FROM AUTHOR]

This paper addresses the stability-analysis problem for teleoperation systems with time delays. Compared with previous work, communication delays are assumed to be both time-varying and asymmetric, which is the case for network-based teleoperation systems. The stability analysis is performed for two classes of controllers: delayed position-error feedback and delayed torque feedback. By choosing Lyapunov–Krasovskii functional, we show that the master–slave teleoperation system is stable under specific linear-matrix-inequality (LMI) conditions. With the given controller-design parameters, the proposed stability criteria can be used to compute the allowable maximal transmission delay. Finally, both simulations and experiments are performed to show the effectiveness of the proposed method. [ABSTRACT FROM PUBLISHER]

Electromigration is a reliability concern of microelectronic interconnections, especially for flip chip solder bump with high current density applied. This study shows that with the line-to-bump geometry in a flip chip solder joint, the current density changes significantly between the Al trace and the bump, while the current crowding effect generates more heat between them. This large Joule heating under high current density can enhance the migration of Sn atoms at the current entrance of the solder bump, and cause the void formation at the entrance point. The present study finds two kinds of electromigration failure modes at the cathode/chip side of the solder bump: the pancake-type and the cotton-type void. The experimental finding shows that the effects of polarity and tilting are key factors to observe in the electromigration behavior of SnAg3.0Cu0.5 solder bumps. Consequently, this study has designed a 3-D numerical model and a corresponding test vehicle to verify the numerical finding. The maximum current density is simulated through the finite element method to provide a better understanding of local heat and current crowding. This study finds that the current crowding ratio is reduced linearly while the void formation is increased. Furthermore, it is concluded that there is a linear relationship between the growth of the intermetallic compound (IMC) layer and the applied current density at the anode/substrate side. [ABSTRACT FROM AUTHOR]

Abstract-In this paper, the robust-control problem is investigated for a class of uncertain nonlinear time-delay systems via dynamic output-feedback approach. The considered system is in the strict-feedback form with unknown control direction. A full-order observer is constructed with the gains computed via linear matrix inequality at first. Then, with the bounds of uncertain functions known, we design the dynamic output-feedback controller such that the closed-loop system is asymptotically stable. Furthermore, when the bound functions of uncertainties are not available, the adaptive fuzzy-logic system is employed to approximate the uncertain function, and the corresponding output-feedback controller is designed. It is shown that the resulting closed-loop system is stable in the sense of semiglobal uniform ultimate boundedness. Finally, simulations are done to verify the feasibility and effectiveness of the obtained theoretical results. [ABSTRACT FROM AUTHOR]

The increasing use of Cu/low-k dielectrics as multilevel interconnect inclusion materials and aggressive scaling in advanced back-end of line (BEOL) results in a considerable challenge in the structural enhancement of mechanical reliability. Owing to the expected adoption of various ultra dielectrics, the development of a prediction methodology with reliable virtual prototypes is needed before realizing successful integrated circuits (IC) for the next technology node. These prototypes are required to assess the potentiality of interfacial cracks in dissimilar materials, while the impacts of chemical-mechanical polishing (CMP) and packaging are introduced. In order to meet the diversity of a Cu/low-k material system and to resolve the significant size difference between the interconnects and the whole IC device, this research presents finite element (FE) analysis based on the mechanic theory of interfacial fracture integrated with a global/local sub-modeling approach. The unique feature of the proposed novel concept is the adoption of equivalent stacked low-k interconnects within the analysis of a global FE model. Through estimation of the i-integral approach and verification of the four-point bending test (4-PBT), the methodology presented exhibits excellent numerical precision in predicting the cracking energy of low-k packaging. In addition, interfacial fracture parameters and stress fields acting near the crack tip are evaluated using an analytical solution combined with polynomial regressions. The derived results match well compared with the simulated data. Based on the presented demonstrations on the ability of simulated procedures, this investigation provides a desirable manner of understanding the related failure mechanisms of low-k interconnects. [ABSTRACT FROM AUTHOR]

For low-delay video transmission, we introduce a q-domain characteristic-based bit-rate model. Specifically, three characteristics are efficiently extracted from the quantized DCT spectra to construct the bit-rate model. Extensive experimental results show that our rate model can provide more accuracy with lower complexity than existing models. [ABSTRACT FROM AUTHOR]

In order to resolve the issues of RC time delay and high power consumption, IC chips with Cu/low-k interconnects are developed to meet the foregoing requirements. However, there is a high potential that in doing so it may contribute to interfacial cracks occurring or propagating between the copper metal and the low-k dielectric material as a result of poor adhesion and lower fracture toughness, which results from the inherent mechanical imperfection of low-k materials. This fracturing problem is one of the most urgent issues for the thermomechanical reliability of Cu/low-k interconnects, and it needs to be resolved urgently. For this reason, we propose a prediction methodology of finite-element analysis (FEA) based on J-integral value estimation to investigate the interfacial fracture opportunity of low-k packages. However, the J-integral calculation is path dependent and so crucial in FEA for a crack on an interface between dissimilar materials. Therefore, various paths with an integral contour surrounding the crack tip are considered to avoid a misunderstanding of the cracking energy. All the analytic results indicate that a rectangular contour with a proper ratio of length/width, and multilayers of element close to the delaminating surfaces, is suggested for obtaining a stable J-integral value. On the other hand, the proposed methodology has been validated by a four-point bending test and compared with the relative experimental data of multi-low-k dielectric films. Moreover, under a reliable integral contour path that crack driving force predicted using the type of interfacial crack constructed by means of the element death technique, it shows good agreement with the simulated results of embedding actual crack. [ABSTRACT FROM AUTHOR]

With the present trend of multifunction and minimizing of size, the conventional electronic package type no longer meets the requirement of the new-generation products. Consequently, new type packaging, based on the wafer level packages (WLPs) and chip scale packages (CSPs) technology are being developed to achieve these requirements, as well as long term reliability. Novel wafer-level chip scale packages (WLCSP) [1] with a stress buffer layer and bubble-like plate (Fig. 1) are proposed in this research to improve the solder joint fatigue life. The thermal stress caused by the coefficient of thermal expansion mismatch can be significantly reduced, and the reliability of the WLP could be substantially enhanced by this new design. In order to realize the relationship of the solder joint fatigue life, stress buffer layer and bubble-like plate, a finite element parametric analysis applying software ANSYS is utilized. In additions, the methodology based on the finite element method (FEM) used in the study has been verified by the relative experiments in our previous researches. The design parameters include the thickness of the stress buffer layer, thickness, bending angle and standoff height of the different types of bubble-like plate. The results of the FEM analysis reveal that the stress buffer layer and bubble-like plate can relax the thermal stresses of solder joints and enhance the package reliability. Besides, the peeling stress between stress buffer layer and two different types of bubble-like plates is discussed, and the stress state of the leadframe is also analyzed in this research. Furthermore, the findings of this research can be used as the guideline for advanced WLCSP design. [ABSTRACT FROM AUTHOR]

Newer, faster, and smaller electronic packaging approaches with high 110 counts and more complex semiconductor devices are emerging steadily and rapidly. Wafer-level chip scaling package (WLCSP) has a high potential for future electronic packaging. However, the solder joint reliability for a large chip size of about 100 mm² without underfill remains a troubling issue that urgently requires a solution. To this end, a double-layer WLCSP (DL-WLCSP) with stress compliant layers and dummy solder joint is adopted in this research in order to study the design parameters of enhancing the solder joint fatigue life. To ensure the validity of the analysis methodology, a test vehicle of Rambus DRAM is implemented to demonstrate the applicability and reliability of the proposed DL-WLCSP. The results of the thermal cycling in the experimental test show good agreement with the simulated analysis. Furthermore, to investigate the reliability impact of the design parameters, including solder volume, the arrangement of the die-side and substrate-side pad diameter, second compliant layer thickness, die thickness, and the printed circuit board (PCB) thickness, a design of experiment (DOE) with factorial analysis is adopted to obtain the sensitivity information of each parameter by the three-dimensional nonlinear finite-element models (FEM5). The statistics results of the analysis of variance reveal that the thickness of the second stress compliant layer and the volume of the solder joint can effectively reduce the stress concentration phenomenon, which occurs around the outer corner of the solder joint. In addition, the evident interaction between design parameters can also be obtained. The smaller thermal strains can be achieved through a better combination of design parameters of the geometry so as to provide the actual requirement of the physical information prior to manufacturing. [ABSTRACT FROM AUTHOR]

During the design and manufacturing processes of electronic packaging, solder joints are fabricated using a variety of methods to provide both mechanical and electrical connections for different applications. They include flip chip, wafer level chip scale packaging (WLCSP), fine pitch ball grid array (BGA), and chip scale packaging (CSP). The solder joint shape prediction methods have been incorporated as a design tool to enhance the reliability of the WLCSP. However, the reliability of solder joints for a large chip size such as 10 mm × 10 mm without underfill remains questionable. In this research, a hybrid method combining an analytical algorithm with the energy-based approach is applied to predict standoff heights and geometry profiles of the solder joints. In addition, a hybrid-pad-shape system is proposed to design the solder ball layout, and to enhance the reliability of the solder joints. Next, a nonlinear and parametric finite element analysis is conducted to investigate the reliability issues that result from several design parameters. In addition, an experimental validation is completed to verify the correctness and feasibility of the solder joint shape prediction methods and finite element analysis procedures. The design parameters considered in this study include solder joint layout, solder volume, pad diameter, as well as the ratio and orientation of the elliptical pad. With regards to solder joint layout design, the solder joints located in the corner areas can be considered as structural dummy balls with no electrical signals passing through them. The results reveal that when the WLCSP has large round pads, or properly oriented elliptical solder joint pads at the corner areas underneath the chip, then the maximum equivalent plastic strain of the solder joints will be effectively reduced. As a result, the solder joint fatigue life under thermal loading will be greatly enhanced. Furthermore, the findings of this research can be used as a design guideline for electronic packaging with area array interconnections such as CSP, flip chip packaging, Super CSP, and fine pitch BGA. [ABSTRACT FROM AUTHOR]

Examines a universal current-mode operational transconductance amplifier-capacitor biquad with minimum components. Description of the circuit; Features of the circuit.

With the introduction of stricter energy-efficiency-ratio regulations, the surface-mounted permanent-magnet motor (SPM) is gaining increasing attention due to its inherent high-power density. This article investigates the feasible SPM structures for refrigerant compressor applications, particularly those used in metal industry factories with high surrounding temperatures so that cost-effective solutions can be achieved. A theoretical model is first established to aid structural parameter optimizations and the management of specific operational objectives and constraints; multiple SPM arrangements are investigates, with ease of manufacturing implementation being one consideration, as shown in Liu et al., 2021. Detailed finite element calculations and experimental measurements are performed to develop feasible SPMs with optimized structural arrangements that meet the desired operational objectives. [ABSTRACT FROM AUTHOR]

Presents information on a study which proposed some novel multifunction operational transconductance amplifier biquadratic filters. Circuit descriptions; Simulation results; Conclusions.

Presents an analysis of the bit-error probability for receivers in which the diversity branches are independent. Noncoherent orthogonal digital modulation; Diagonalization of quadratic forms; Maximum-likelihood combiner; General formula; Square-law combining; Correlated dual diversity.

Presents information on a fast block-matching algorithm for video coding. How the algorithm works; Benefits it offers; Result of the evaluation of the algorithm's performance.

Interpolation involves the process of estimating values at positions in between the adjacent samples, which has very fundamental and applied implications in signal processing and communication systems. In this work, a new method of cubic spline interpolation (CSI) is proposed and derived mathematically from the input samples respecting the time-domain boundary conditions, and the corresponding piecewise polynomials are optimized in the frequency domain to achieve good spectral properties. A comparative analysis of several prior arts, including arbitrary frequency response polynomial (AFRP) and basis spline (B-spline) is also presented, giving a clear overview of the advantages associated with the proposed technique in terms of implementation complexity, latency, and in-band and out-of-band spectral performance. The measurement results with three different radio frequency (RF) power amplifier (PA) prototypes using an input stimulus comprised of different instantaneous bandwidth (iBW) carrier aggregated 5G new radio (NR) waveform are demonstrated to highlight the improved performance in the context of digital predistortion (DPD) correction. Finally, the architecture of the proposed method is illustrated, which is suitable for real-time high-speed digital implementation. [ABSTRACT FROM AUTHOR]

Provides information on the presentation of some novel multifunction biquadratic filters with voltage gain, each of which employs four current conveyors, two grounded capacitors, and three-five resistors. Information on the circuit descriptions; Detailed information on the experimental results; Conclusions reached.

Presents information on a study which proposed a voltage-mode filter and three outputs using two compound current conveyors. Features of the proposed circuit; Circuit description; Conclusions.

This paper reports our study on the nonlinear stiffness of a few diaphragm designs used for miniature loudspeakers. For this study, the sample diaphragms were experimented for their stiffness curves using the laser vibrometry. Additionally, the stiffness curves were also obtained using finite element analysis (FEA). For calculating total harmonic distortion (THD), the electroacoustic system is modeled using the equivalentcircuit analogy. As a result of solving the coupled system of ordinary differential equations by the Runge-Kutta method, THD of three sample designs, characterized by different track patterns, were calculated and plotted as a function of frequency. The specimens were tested in a standard anechoic chamber for recording THD. Additionally, the sound pressure level (SPL) curves of these specimens were also recorded for comparison. It turns out that, despite no significant SPL difference, diaphragms with different track patterns shall, as a result, lead to substantial variations of THD. The consistence of our simulations with the measured THD has promised the feasibility of simulating THD by FEA for optimizing the design of track patterns for diaphragm. [ABSTRACT FROM PUBLISHER]

An interpersonal network within a firm serves as a primary knowledge base for organizational innovation. In this article, we propose that intrafirm network connectivity, which is measured by the transitivity of an intrafirm network, has a nonlinear effect on firm innovation performance. Furthermore, on the basis of the literature on environmental contingency, we propose that two dimensions of environmental uncertainty (i.e., environmental munificence and dynamism) moderate the influence of intrafirm network connectivity on firm innovation performance. To examine our hypotheses, we collect the profiles of firms in the pharmaceutical and biotechnology industries from the COMPUSTAT database and patent data from the United States Patent and Trademark Office database for the period of 1991–2012. Our longitudinal study finds an inverted U-shaped relationship between intrafirm network connectivity and firm innovation performance, and such a relationship is moderated by environmental munificence but not by environmental dynamism. [ABSTRACT FROM AUTHOR]

A correction to the article "Enhancing the Reliability of Wafer Level Packaging by Using Solder Joints Layout Design," by Chang-Ming Liu, Chang-Chun Lee, and Kuo-Ning Chiang, published in one of the previous issues of the journal.

In this paper, we investigate the response time of oxygen vacancies on the hysteresis for the amorphous indium–gallium–zinc oxide thin-film transistors. The fast pulse measurement method is used to observe the drain current under the different sweeping speeds of gate voltage to clarify the mechanism of the hysteresis. Effects of light intensity and temperature are also discussed. Based on the results and the analysis, the model of oxygen vacancies is proposed to explain the effect of sweep speed on the hysteresis, which would be important for the devices to be driven in their circuit application. [ABSTRACT FROM AUTHOR]

This paper mainly focuses on establishing the stability conditions of the double exponentially weighted moving average (d-EWMA) controller with metrology delay when the process experiences a general disturbance and analyzing its control performance under some typical types of process disturbance. The necessary and sufficient conditions for stability are established by Routh-Hurwitz criteria. It has been shown that if the process gain mismatch is greater than 4/3, metrology delay will make the feasible region of two weighting factors in the d-EWMA controller decrease, and the larger metrology delay is, the smaller the feasible region is. Moreover, given two weighting factors, it is found that metrology delay will weaken the robustness of the d-EWMA controller. The influence of metrology delay on the asymptotical control performance is evaluated based on asymptotical mean square error (AMSE). Optimal weighting factors and AMSE can be solved based on analytical expression of the AMSE, which is derived by using the Yule-Walker equations to avoid function summing limit operation. Through numerical simulations, it demonstrates that metrology delay may increase the variability of the process output under certain conditions. Finally, the chemical mechanical polishing process in semiconductor manufacturing is used to illustrate the validity of theoretical results. [ABSTRACT FROM PUBLISHER]

The pulse-modulated polar transmitter (PMPT) uses the envelope information to pulse modulate the phase information to implement a highly linear and highly efficient polar transmitter. The bandwidth of the PMPT is primarily determined by the pulsewidth modulation sampling frequency of the envelope information. For wide bandwidth applications such as long-term evolution (LTE), finite rise and fall times of the RF pulses distort the envelope information. In this paper, the nonideal RF pulses are analyzed and an envelope correction method is proposed to reduce the distortion in wide bandwidth applications using the PMPT architecture. For validation, a cellular-band prototype transmitter system was constructed using commercially available components. Using a 20-MHz bandwidth 16-QAM LTE signal at 836.5 MHz, the prototype transmitter achieved an output power of 22.7 dBm and drain efficiency of 33% while passing the spectral requirements of the LTE standard. [ABSTRACT FROM AUTHOR]