209 results on '"Bakkaloglu, Bertan"'
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2. Low-to-Medium Power Single Chip Digital Controlled DC-DC Regulator for Point-of-Load Applications
- Author
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Adell, Philippe C, Bakkaloglu, Bertan, Vermeire, Bert, and Liu, Tao
- Subjects
Electronics And Electrical Engineering - Abstract
A DC-DC converter for generating a DC output voltage includes: a digitally controlled pulse width modulator (DPWM) for controlling a switching power stage to supply a varying voltage to an inductor; and a digital voltage feedback circuit for controlling the DPWM in accordance with a feedback voltage corresponding to the DC output voltage, the digital voltage feedback circuit including: a first voltage controlled oscillator for converting the feedback voltage into a first frequency signal and to supply the first frequency signal to a first frequency discriminator; a second voltage controlled oscillator for converting a reference voltage into a second frequency signal and to supply the second frequency signal to a second frequency discriminator; a digital comparator for comparing digital outputs of the first and second frequency discriminators and for outputting a digital feedback signal; and a controller for controlling the DPWM in accordance with the digital feedback signal.
- Published
- 2015
3. Analog image recognition arrays design by using co-fabricated MOSFET and MESFETs on a 0.25 μm SOS process
- Author
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Kim, Sungho, Lepkowski, William, Thornton, Trevor J., and Bakkaloglu, Bertan
- Published
- 2012
- Full Text
- View/download PDF
4. A 280 mW, 0.07% THD+N class-D audio amplifier using a frequency-domain quantizer
- Author
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Lee, Junghan, Copani, Tino, Mayhugh, Jr., Terry, Aravind, Bhaskar, Kiaei, Sayfe, and Bakkaloglu, Bertan
- Published
- 2012
- Full Text
- View/download PDF
5. Electronic-nose for detecting environmental pollutants: signal processing and analog front-end design
- Author
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Kim, Hyuntae, Konnanath, Bharatan, Sattigeri, Prasanna, Wang, Joseph, Mulchandani, Ashok, Myung, Nosang, Deshusses, Marc A., Spanias, Andreas, and Bakkaloglu, Bertan
- Published
- 2012
- Full Text
- View/download PDF
6. A low noise, high power efficiency supply regulator for near-field power delivery
- Author
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Harrington, Peter, Chakraborty, Sudipto, and Bakkaloglu, Bertan
- Published
- 2011
- Full Text
- View/download PDF
7. Compact model and circuit simulations for asymmetric, independent gate FinFETs
- Author
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Dessai, Gajanan, Wu, Weimin, Bakkaloglu, Bertan, McAndrew, Colin C., and Gildenblat, Gennady
- Published
- 2010
- Full Text
- View/download PDF
8. Design and analysis of a CMOS passive Σ∆ ADC for low power RF transceivers
- Author
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Chen, Feng, Bakkaloglu, Bertan, and Ramaswamy, Srinath
- Published
- 2009
- Full Text
- View/download PDF
9. An Active EMI Cancellation Technique Achieving a 25-dB Reduction in Conducted EMI of LIN Drivers.
- Author
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Ray, Abhishek, Magod, Raveesh, Talele, Bhushan, Alevoor, Shashank, Mayhugh, Terry, and Bakkaloglu, Bertan
- Subjects
ELECTROMAGNETIC interference ,ELECTROMAGNETIC compatibility ,SYSTEMS on a chip ,FREQUENCY spectra ,COMPUTER performance ,POWER spectra ,VOLTAGE-controlled oscillators - Abstract
Robustness to electromagnetic interference (EMI) is one of the primary design aspects of state of the art automotive ICs like System Basis Chips (SBCs) which provide a wide range of analog, power regulation and digital functions on the same die. One of the primary sources of conducted EMI on the Local Interconnect Network (LIN) driver output is an integrated switching DC-DC regulator noise coupling through the parasitic substrate capacitance of the SBC. In this paper an adaptive active EMI cancellation technique to cancel the switching noise of the DC-DC regulator on the LIN driver output to ensure electromagnetic compatibility (EMC) is presented. The proposed active EMI cancellation circuit synthesizes a phase synchronized cancellation pulse which is then injected onto the LIN driver output using an on-chip tunable capacitor array to cancel the switching noise injected via substrate. The proposed EMI reduction technique can track and cancel substrate noise independent of process technology and device parasitics, input voltage, duty cycle and loading conditions of the DC-DC switching regulator. The EMI cancellation system is designed and fabricated on a 180nm Bipolar-CMOS-DMOS (BCD) process with an integrated power stage of a DC-DC buck regulator at a switching frequency of 2MHz along with an automotive LIN driver. The EMI cancellation circuit occupies an area of 0.7 mm2, which is less than 3% of the overall area in a standard SBC and consumes 12.5 mW of power and achieves 25 dB reduction of conducted EMI in the LIN driver output’s power spectrum at the switching frequency and its harmonics. [ABSTRACT FROM AUTHOR]
- Published
- 2022
- Full Text
- View/download PDF
10. A CMOS low noise, chopper stabilized low-dropout regulator with current-mode feedback error amplifier
- Author
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Oh, Wonseok, Bakkaloglu, Bertan, Wang, Chris, and Hoon, Siew K.
- Subjects
Circuit design -- Methods ,Amplifiers (Electronics) -- Design and construction ,Circuit designer ,Integrated circuit design ,Business ,Computers and office automation industries ,Electronics ,Electronics and electrical industries - Abstract
Low 1/f noise, low-dropout (LDO) regulators are becoming critical for the supply regulation of deep-submicron analog baseband and RF system-on-chip designs. A low-noise, high accuracy LDO regulator (LN-LDO) utilizing a chopper stabilized error amplifier is presented. In order to achieve fast response during load transients, a current-mode feedback amplifier (CFA) is designed as a second stage driving the regulation FET. In order to reduce clock feed-through and 1/f noise accumulation at the chopping frequency, a first-order digital [SIGMA][DELTA] noise-shaper is used for chopping clock spectral spreading. With up to 1 MHz noise-shaped modulation clock, the LN-LDO achieves a noise spectral density of 32 nV/ [square root of Hz] and a PSR of 38 dB at 100 kHz. The proposed LDO is shown to reduce the phase noise of an integrated 32 MHz temperature compensated crystal oscillator (TCXO) at 10 kHz offset by 15 dB. Due to reduced 1/f noise requirements, the error amplifier silicon area is reduced by 75%, and the overall regulator area is reduced by 50% with respect to an equivalent noise static regulator. The current-mode feedback second stage buffer reduces regulator settling time by 60% in comparison to an equivalent power consumption voltage mode buffer, achieving 0.6 [micro]s settling time for a 25-mA load step. The LN-LDO is designed and fabricated on a 0.25 [micro]m CMOS process with five layers of metal, occupying 0.88 [mm.sup.2]. Index Terms--Chopper stabilization, current feedback amplifier, low-dropout regulators, power supply rejection.
- Published
- 2008
11. Systematic design of supply regulated LC-tank voltage-controlled oscillators
- Author
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Wang, Xuejin and Bakkaloglu, Bertan
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Circuit design -- Methods ,Oscillators (Electronics) -- Design and construction ,Circuit designer ,Integrated circuit design ,Business ,Computers and office automation industries ,Electronics ,Electronics and electrical industries - Abstract
Systematic design of low-dropout-regulator (LDO) regulated low-phase-noise LC-tank voltage controlled oscillators (VCOs) is presented. Low-frequency sensitivity profile of power supply induced phase noise of a typical cross-coupled LC-tank VCO is investigated. The relationship between frequency pushing and power supply-induced phase noise is derived. Systematic codesign of VCO sensitivity to low-frequency supply noise with respect to an LDO output noise and power supply rejection profile is introduced. To demonstrate the design approach experimentally, two 2.4-GHz LC-tank VCOs with pMOS and nMOS switching devices powered by PFET LDOs are designed and fabricated on an 0.18-ftm, 7-layer metal CMOS process. By using an integrated LDO, it is shown that the VCO phase-noise sensitivity to low frequency improves by 55 dB at 100-kHz offset. Index Terms--DC-DC power conversion, voltage regulators, phase noise, power supply rejection (PSR), voltage-controlled oscillators (VCOs).
- Published
- 2008
12. A multistage interleaved synchronous buck converter with integrated output filter in 0.18 [micro]m SiGe process
- Author
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Abedinpour, Siamak, Bakkaloglu, Bertan, and Kiaei, Sayfe
- Subjects
Electric current converters -- Design and construction ,Electric filters -- Usage ,Voltage -- Measurement ,Electric current converter ,Business ,Electronics ,Electronics and electrical industries - Abstract
The design and analysis of a fully integrated multistage interleaved synchronous buck dc-dc converter with on-chip filter inductor and capacitor is presented. The dc-dc converter is designed and fabricated in 0.18 [micro]m SiGe RFBiCMOS process technology and generates 1.5 V-2.0 V programmable output voltage supporting a maximum output current of 200 mA. High switching frequency of 45 MHz, multiphase interleaved operation, and fast hysteretic controller reduce the filter inductor and capacitor sizes by two orders of magnitude compared to state-of-the-art converters and enable a fully integrated converter. The fully integrated interleaved converter does not require off-chip decoupling and filtering and enables direct battery connection for integrated applications. This design is the first reported fully integrated multistage interleaved, zero voltage switching synchronous buck converter with monolithic output filters. The fully integrated buck regulator achieves 64% efficiency while providing an output current of 200 mA. Index Terms--Fully integrated switched-mode (SM) dc-dc converter, interleaved synchronous buck converter, zero voltage switching (ZVS).
- Published
- 2007
13. Impact of sampling clock phase noise on [SIGMA][DELTA] frequency discriminators
- Author
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Kwon, Jiuk and Bakkaloglu, Bertan
- Subjects
Modulators (Electronics) -- Design and construction ,Discriminators (Electronics) -- Discipline ,Electromagnetic noise -- Influence ,Business ,Computers and office automation industries ,Electronics ,Electronics and electrical industries - Abstract
[SIGMA][DELTA] frequency discriminators ([SIGMA][DELTA]AFDs) convert instantaneous frequency deviations of a carrier signal to digital. They are used for decoding narrowband phase or frequency modulated signals in communication receivers, self calibration of RF frequency synthesizers and in digital phase locked loops. In this paper, the impact of reference (sampling) clock phase noise on a [SIGMA][DELTA]AFD's spurious-free dynamic range (SFDR) is derived. It is shown that for [SIGMA][DELTA]FDs with jittered sampling clock, in addition to FM sidebands, a high baseband tonal content is generated degrading overall SFDR. The reference clock phase noise impact is derived mathematically, and two commonly used [SIGMA][DELTA]FDs circuits are designed and implemented to verify the results experimentally. Experimental results are shown to match the theoretical prediction of SFDR within 3 dB. Index Terms--Clock Jitter, frequency discriminators, [SIGMA][DELTA]modulators.
- Published
- 2007
14. A CMOS low-dropout regulator with current-mode feedback buffer amplifier
- Author
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Oh, Wonseok and Bakkaloglu, Bertan
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Circuit components ,Semiconductor industry ,Complementary metal oxide semiconductors ,Semiconductor device ,Semiconductor industry ,Business ,Computers and office automation industries ,Electronics ,Electronics and electrical industries - Abstract
Current feedback amplifiers (CFAs) provide fast response and high slew rate with Class-AB operation. Fast response, low-dropout regulators (LDRs) are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. An LDR with an CFA-based second stage driving the regulation field-effect transistor is presented. The low dropout (LDO) achieves an output noise spectral density of 67.7 nV/[square root of Hz], and PSR of 38 dB, both at 100 kHz. In comparison to an equivalent power consumption voltage feedback buffer LDO, the proposed CFA-based LDO settles 60% faster, achieving 0.6-[micro]s settling time for a 25-mA load step. The LDO with CFA buffer is designed and fabricated on a 0.25-[micro]m CMOS process with five layers of metal, occupying 0.23-[mm.sup.2] silicon area. Index Terms--Current feedback amplifier (CFA), low-dropout regulators (LDRs), power supply rejection.
- Published
- 2007
15. Polar SiGe class E and F amplifiers using switch-mode supply modulation
- Author
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Kitchen, Jennifer N., Deligoz, Ilker, Kiaei, Sayfe, and Bakkaloglu, Bertan
- Subjects
Power amplifiers -- Analysis ,Modulation (Electronics) -- Analysis ,Business ,Computers ,Electronics ,Electronics and electrical industries - Abstract
Two integrated polar supply-modulated class E and F power amplifiers (PAs) in 0.18-[micro]m SiGe BiCMOS process are presented. The amplifiers are used to transmit GSM-EDGE signals with an envelope dynamic range of 11 dB and a frequency range of 880-915 MHz. The amplifiers use switch-mode dc--dc buck converters for supply modulation, where sigma--delta ([SUMMATION][DELTA]M), delta ([DELTA]M), and pulsewidth modulation are used to modulate the PA amplitude signal. A framework has been developed for comparing the three switching techniques for EDGE implementation. The measurement results show that [DELTA]M gives the highest efficiency and lowest adjacent channel power, providing class E and F PA efficiencies of 33% and 31%, respectively, at maximum EDGE output power. The corresponding class E and F finearized amplifiers' output spectra at 400-kHz offset are -54 and -57 dBc, respectively. Index Terms--EDGE, polar modulation, power amplifiers (PAs), switching amplifiers. Digital Object Identifier 10.1109/TMTT.2007.895407
- Published
- 2007
16. Randomized carrier PWM with exponential frequency mapping
- Author
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Carlosena, Alfonso, Chu, Wing-Yee, Bakkaloglu, Bertan, and Kiaei, Sayfe
- Subjects
Electromagnetic interference -- Measurement ,Pulse-duration modulation -- Analysis ,Electric current converters -- Design and construction ,Electric current converter ,Business ,Electronics ,Electronics and electrical industries - Abstract
Pulsewidth modulation (PWM) and sigma-delta modulation (SDM) have been used in several high linearity, high accuracy power delivery applications such as dc-dc power converters, audio, and radio frequency power amplifiers and data converters. While PWM can generate high linearity signals with high efficiency, it suffers from discrete tonal output spectrums. SDM, on the other hand, can generate high linearity output spectrums with shaped quantization noise spectrums and lower efficiencies due to oversampling requirements. In this paper we present a particular class of carrier frequency modulated PWM (CFMPWM), which spreads the tonal content of regular PWM uniformly in frequency and reduces the baseband noise with respect to SDM by up to 15 dB. The new modulation scheme preserves the high efficiency properties of PWM. An approximate method to estimate the spectrum of CFMPWM signals with both deterministic and random modulation is also presented. Simulation results and experimental data are reported to analyze the spectral spreading properties of the proposed CFMPWM scheme. Index Terms--Carrier frequency modulated pulsewidth modulation (CFMPWM), electromagnetic interference (EMI), pulse density modulation (PDM), sigma--delta modulation (SDM).
- Published
- 2007
17. An injection-locked frequency-tracking [SIGMA][DELTA] direct digital frequency synthesizer
- Author
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Lyles, Umar J., Copani, Tino, Bakkaloglu, Bertan, and Kiaei, Sayfe
- Subjects
Frequency synthesizers -- Analysis ,Oscillators (Electronics) -- Analysis ,Business ,Computers and office automation industries ,Electronics ,Electronics and electrical industries - Abstract
A bandpass (BP) sigma-delta modulator ([SIGMA][DELTA]M)-based direct digital frequency synthesizer (DDS) architecture is presented. The DDS output is passed through a single-bit, second-order BP[SIGMA][DELTA]M, shaping quantization noise out of the signal band. The single-bit BP[SIGMA][DELTA]M is then injection locked to an LC-tank oscillator, which provides a tracking BP filter response within its locking range, suppressing the BP[SIGMA][DELTA]M out of band quantization noise. The instantaneous digital frequency control word input of the DDS is used to tune the noise shaper center frequency, achieving up to 20% tuning range around the fundamental. The BP[SIGMA][DELTA]M-based synthesizer is fabricated in a 0.25-[micro]m digital CMOS process with four layers of metal. With a second-order BP noise shaper and a 44-MHz LC tank oscillator, an SFDR of 73 dB at a 2-MHz bandwidth and phase noise lower than--105 dBc/Hz at a 10-kHz offset is achieved. Index Terms--Direct digital frequency synthesizer (DDS), injection locking, oscillator, phase noise, sigma-delta modulator ([SIGMA][DELTA]M).
- Published
- 2007
18. Delta-sigma (ΔΣ) frequency synthesizers for wireless applications
- Author
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Bakkaloglu, Bertan, Kiaei, Sayfe, and Chaudhuri, Bikram
- Published
- 2007
- Full Text
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19. Analysis of single events effects on monolithic PLL frequency synthesizers
- Author
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Chung, Hoon Hee, Chen, Wenjian, Bakkaloglu, Bertan, Barnaby, Hugh J., Vermeire, Bert, and Kiaei, Sayfe
- Subjects
Phase-locked loops -- Research ,Frequency synthesizers -- Research ,Business ,Electronics ,Electronics and electrical industries - Abstract
Frequency synthesizers are fundamental building blocks in radio frequency, communications, and analog signal processing for generating high accuracy oscillatory signals. In general, the frequency synthesizer is the most sensitive block in the system since many of the signal processing elements such as clock, filters, and up/down converters depend on the synthesizer generating a clean sinusoidal signal at the given frequency. For radiation environments, the response and the sensitivity of the phase-lock loop (PLL) and the synthesizer block is very critical. This paper examines the effect of single events (SEE) radiation on the PLL locking and steady state response. The PLL circuits operating at 2.4 GHZ were designed and fabricated using a 0.13 ~m CMOS process This paper presents the experimental and simulations results on the SEE radiation effects on the PLL. Index Terms--Hold-in range, lock-in range, phase locked loop (PLL), radiation effects, single event effect (SEE), VCO.
- Published
- 2006
20. Closed-loop nonlinear modeling of wideband [SIGMA][DELTA] fractional-N frequency synthesizers
- Author
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Hedayati, Hiva, Bakkaloglu, Bertan, and Khalil, Waleed
- Subjects
Oscillators (Electronics) -- Design and construction ,Nonlinear theories -- Analysis ,Phase modulation -- Analysis ,Business ,Computers ,Electronics ,Electronics and electrical industries - Abstract
Wideband low-noise [SIGMA][DELTA] fractional-N synthesizers pose several design challenges due to the nonlinear time-varying nature of synthesizer building blocks such as phase frequency detectors (PFDs), charge pump, and frequency dividers. Loop nonlinearities can increase close-in phase noise and enhance spurious tones due to intermodulation of high-frequency quantization noise and tonal content; therefore, an accurate simulation model is critical for successful implementation of loop parameters and bandwidth widening techniques. In this paper a closed-loop nonlinear simulation model for fractional-N synthesizers is presented. Inherent nonuniform sampling of the PFD is modeled through an event-driven dual-iteration-based technique. The proposed technique generates a vector of piecewise linear time--voltage pairs, defining the voltage-controlled oscillator (VCO) control voltage. This method also lends itself to modeling of cyclostationary thermal and flicker noise generated by time-varying charge-pump current pulses. A flexible third-order [SIGMA][DELTA] modulated RF synthesizer core with integrated loop filter and LC-tank VCO is designed and fabricated in 0.13-[micro]m CMOS process in order to validate the technique experimentally. The proposed modeling technique was able to predict in-band spur power levels with 1.8-dB accuracy, and spur frequency offsets with lower than 400-Hz accuracy with several programmable nonidealities enabled. Index Terms--Fractional.N frequency synthesizers, phase-locked loops (PLLs), phase noise, quantization noise, sigma--delta modulation, spurs.
- Published
- 2006
21. Monolithic distributed power management for systems-on-Chip (SoC)
- Author
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Abedinpour, Siamak, Bakkaloglu, Bertan, and Kiaei, Sayfe
- Published
- 2004
- Full Text
- View/download PDF
22. An SET-free, all digital controlled point-of-load regulator for next generation power systems : ADC-POL
- Author
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Adell, Philippe C, Liu, Tao, Vermeire, Bert, Bakkaloglu, Bertan, and Aveline, David
- Published
- 2011
23. A Mixed-Signal Adaptive Ripple Canceler for Switching Regulators Providing 18 dB-24 dB of Ripple Rejection up to 1 MHz.
- Author
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Joshi, Kishan, Yang, Zhe, Fu, Chao, Mandal, Debashis, Waterfall, Gregory, and Bakkaloglu, Bertan
- Abstract
A mixed-signal adaptive ripple canceller for reducing switching noise and spurious emissions in switching regulators is presented. The proposed mixed-signal ripple suppression technique tracks and cancels the switching noise by utilizing two schemes: A primary mixed-signal adaptive ripple canceller that provides large signal ripple cancellation up to 20 dB, and an auxiliary linear amplifier-based ripple canceller that minimizes the residual ripple content, achieving a combined ripple rejection of 24 dB. Proposed approach operates without the need for external components, reducing overall printed circuit board area without loss of efficiency. The adaptive ripple canceller is designed and fabricated in a 250 nm CMOS process with four levels of metal. The ripple-canceller is integrated with an on-chip buck regulator to characterize its rejection effectiveness. The ripple canceller can also be utilized as a stand-alone ripple cleaner module with an external commercial-off-the-shelf (COTS) switching regulator. The proposed ripple canceller can track and cancel power supply ripple up to 1 MHz with 24 dB rejection and reduces ripple content up to fourth harmonic by at least 20 dB while supporting dc loads up to 1 A and ripple currents up to 350 mApk-pk. The proposed approach achieves 30% lower quiescent current than using a linear low-dropout regulator without the need for any external components. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
24. Editorial.
- Author
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Schreurs, Dominique and Lin, Jenshan
- Subjects
- *
PERSONNEL changes , *STUDENTS - Abstract
The article presents miscellaneous topics including an introduction in which the editor discusses resignation of Bertan Bakkaloglu, associate editor of the periodical and appointment of Olga Boric-Lubecke as his replacement along with biography of Boric-Lubecke. It mentions that Boric-Lubecke received her Bachelor of Science degree from the University of Belgrade, Belgrade, Yugoslavia and Masters Degree from the University of California at Los Angeles in Los Angeles, California.
- Published
- 2015
- Full Text
- View/download PDF
25. A 5.6 μ A Wide Bandwidth, High Power Supply Rejection Linear Low-Dropout Regulator With 68 dB of PSR Up To 2 MHz.
- Author
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Joshi, Kishan, Manandhar, Sanjeev, and Bakkaloglu, Bertan
- Subjects
POWER resources ,BANDWIDTHS ,GOVERNORS (Machinery) ,LOGIC circuits ,CAPACITORS - Abstract
High power supply rejection (PSR) with a wide rejection frequency band is becoming a critical requirement in linear low-dropout regulators (LDOs) used in complex systems-on-chip (SOCs). Typical LDOs achieve higher PSR within their loop-bandwidth; however, their supply rejection performance degrades with reduced loop-gain outside their loop-bandwidth. Typical LDOs with external filtering capacitors may also have spectral peaking in their PSR response, causing excess system-level supply noise. This work presents an LDO design approach, which achieves a PSR of higher than 68 dB up to 2 MHz frequency and over a wide range of loads up to 250 mA. The wide PSR bandwidth is achieved using a current-mode feedforward ripple canceller (CFFRC) amplifier which provides up to 25 dB of PSR improvement. The feedforward path gain is inherently matched to the forward gain of the LDO, not requiring calibration. The LDO has a fast load transient response with a recovery time of 6.1 $\mu \text {s}$ and has a quiescent current of 5.6 $\mu \text {A}$. For a full load transition, the LDO achieves settling with overshoot and undershoot voltages below 27.6 and 36.36 mV, respectively. The LDO is designed and fabricated in a 180 nm bipolar/CMOS/DMOS (BCD) technology. The CFFRC amplifier helps to achieve low quiescent power due to its inherent current mode nature, eliminating the need for supply ripple summing amplifiers and adaptive biasing. [ABSTRACT FROM AUTHOR]
- Published
- 2020
- Full Text
- View/download PDF
26. Wideband Hybrid Envelope Tracking Modulator With Hysteretic-Controlled Three-Level Switching Converter and Slew-Rate Enhanced Linear Amplifier.
- Author
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Mahmoudidaryan, Parisa, Mandal, Debashis, Bakkaloglu, Bertan, and Kiaei, Sayfe
- Subjects
LONG-Term Evolution (Telecommunications) ,DETECTOR circuits ,POWER amplifiers ,HYSTERESIS loop ,ELECTRIC current rectifiers ,PARALLEL electric circuits ,TRANSISTORS ,CAPACITOR switching - Abstract
A wideband hybrid Envelope tracking (ET) modulator utilizing a hysteretic-controlled three-level switching converter (3L-SWC) and a slew-rate enhanced linear amplifier (LA) are presented. In addition to smaller ripple and lower losses of 3L-SWCs, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80 MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage $V_{\mathrm{ CF}}$ and eliminates the conventionally required calibration loop to control it. The hysteretic-controlled 3L-SWC provides a high percentage of power amplifier (PA) supply load current with lower ripple, reducing the LA high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the LA, resulting in slew rate of over 307 V/ $\mu \text{s}$ and bandwidth of over 275 MHz for the LA. The SRE circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of output without modifying the operating point of the remaining LA, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in a 65-nm CMOS process. The measurement results show the tracking of long-term evolution (LTE)-40-MHz envelope with 93% peak efficiency at 1-W output power, while the SRE is disabled. Enabling the SRE, it can track LTE-80-MHz envelope with peak efficiency of 91%. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
27. IEEE Transactions on Microwave Theory and Techniques publication information.
- Subjects
- INSTITUTE of Electrical & Electronics Engineers, BAKKALOGLU, Bertan, DAMBRINE, Gilles
- Abstract
The article lists several members of the administrative committee and editors of the Microwave Theory and Techniques Society, a division of Institute of Electrical and Electronics Engineers, with its editorial policy including Bertan Bakkaloglu, Gilles Dambrine and Francisco Mesa.
- Published
- 2014
- Full Text
- View/download PDF
28. A 50-V Isolation, 100-MHz, 50-mW Single-Chip Junction Isolated DC-DC Converter With Self-Tuned Maximum Power Transfer Frequency.
- Author
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Liu, Chengxi, Mandal, Debashis, Yao, Zhao, Sun, Ming, Todsen, Jim, Johnson, Brian, Kiaei, Sayfe, and Bakkaloglu, Bertan
- Abstract
A fully integrated, point-of-load, low-noise, isolated dc–dc converter for supply regulation of high dynamic range analog and mixed-signal isolated sensor signal-chains is presented. The isolated dc–dc converter utilizes an integrated planar air-core micro-transformer as a coupled-resonator and an isolation barrier, and enables direct connection of low-voltage mixed-signal circuits to higher supply rails for current and voltage sensing. The transformer is driven at its resonant frequency of 100 MHz to achieve maximum power transfer. A mixed-signal perturb-and-observe-based frequency search algorithm is developed to improve maximum power transfer efficiency by 60% across the isolation barrier compared to fixed driving frequency method. The switching ripple at output is reduced by 11 dB utilizing spread spectrum clocking in the driver, and 21 dB using a low-dropout regulator. Conducted and radiated EMI distribution on the IC is measured by a set of proposed ring oscillator-based noise sensors with −68-dBm noise sensitivity. The proposed isolated converter achieves the highest level of integration compared to state-of-the-art integrated isolated converters, and provides 50-V on-chip junction isolation using standard CMOS technology. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
29. Adaptively Biased Output Cap-Less NMOS LDO With 19 ns Settling Time.
- Author
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Mandal, Debashis, Desai, Chirag, Bakkaloglu, Bertan, and Kiaei, Sayfe
- Abstract
This paper presents an output external capacitor-less, fully integrated, fast settling NMOS low-dropout (LDO) regulator with adaptively biased error amplifier (EA) for system-on-chip core applications. The adaptive biasing technique increases both loop bandwidth and slew-rate of the LDO by 100% at full load condition without changing no-load quiescent current. Direct feedback to gate-to-source voltage of the NMOS regulation FET provides fast load transient response. The proposed LDO employs a cross-coupled common-gate input based EA, with transconductance boosting, achieving twice unity-gain bandwidth in comparison to a typical folded-cascode common-source input stage. Low output impedance of NMOS regulation stage and low input impedance of the EA reduce load dependent stability issue. The proposed regulator is designed and fabricated in a 0.18- $\mu \text{m}$ CMOS technology with die-area of 0.21 mm2. The LDO generates a regulated output voltage of 1.4–1.6 V from an input voltage of 1.6–1.8 V, consumes 133 $\mu \text{A}$ quiescent current, and supports 0 pF to 50 pF load capacitance. Measured results show 166 mV undershoot with 19 ns settling time for a load step from 9 mA to 40 mA in 350 ps edge-time for zero-load capacitance. After using adaptive biasing, the settling time is reduced by 37% and 36% for 0 pF and 50 pF load, respectively. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
30. A 1.24 $\mu$ A Quiescent Current NMOS Low Dropout Regulator With Integrated Low-Power Oscillator-Driven Charge-Pump and Switched-Capacitor Pole Tracking Compensation.
- Author
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Magod, Raveesh, Bakkaloglu, Bertan, and Manandhar, Sanjeev
- Subjects
POWER resources ,GOVERNORS (Machinery) ,BATTERY industry ,ELECTRONIC amplifiers ,ELECTRIC potential ,OSCILLATOR strengths - Abstract
Supply regulation using low quiescent current linear regulators helps in extending the battery life of power aware applications with very long standby time. A 1.24 $\mu \text{A}$ quiescent current NMOS low dropout (LDO) that uses a hybrid bias current generator (HBCG) which boosts the bias current dynamically and adaptively to improve the transient response is presented in this paper. A bias-current scalable error amplifier with an on-demand pull-up/pull-down buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. A novel switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA with a low-ESR 1 $\mu \text{F}$ output capacitor. Designed in a 0.25 $\mu \text{m}$ CMOS process, the LDO has an output voltage range of 1–3 V, a dropout voltage of 240 mV, and a core area of 0.11 mm2. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
31. Radiation-Tolerant Digital Multiphase Current-Mode Hysteretic Point-of-Load Regulator.
- Author
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Adell, Philippe C., Sun, Ming, Joshi, Kishan, Allen, Gregory, Yang, Zhe, and Bakkaloglu, Bertan
- Subjects
COMPLEMENTARY metal oxide semiconductors ,HYSTERESIS ,RADIATION doses ,SYNCHRONIZATION ,FABRICATION (Manufacturing) ,DIGITAL technology - Abstract
A radiation-tolerant digital multiphase current-mode hysteretic point-of-load regulator fabricated on a commercial 180-nm CMOS process is presented. Experiments and simulations are used to demonstrate its single-event immunity and its total-dose tolerance over 100 krad(Si). Key electrical performance parameters are: 5-V input, 0.8–3.3 V output, 10-A load current, 93% peak efficiency, four-phase hysteretic quasi-current-mode buck converter with ±1.5% frequency synchronization, ±3.6% current sharing error, and 1% ripple. [ABSTRACT FROM AUTHOR]
- Published
- 2018
- Full Text
- View/download PDF
32. Integrated Quasi-Circulator With RF Leakage Cancellation for Full-Duplex Wireless Transceivers.
- Author
-
Ayati, Seyyed Amir, Mandal, Debashis, Bakkaloglu, Bertan, and Kiaei, Sayfe
- Subjects
ELECTRIC impedance ,CIRCULATORS (Electrical engineering) ,RADIO transmitter-receivers ,SOFTWARE radio ,LOW noise amplifiers - Abstract
An integrated reconfigurable CMOS quasi-circulator operating at 2.4 GHz is presented. A passive structure delivers transmit power amplifier (PA) output signal to the differential low-noise amplifier (LNA) input as a common-mode signal and simultaneously delivers received signal as a differential-mode signal at the LNA input. The leakage of the PA output signal at the LNA input is reduced in two steps. First, the use of a reconfigurable impedance matching circuit, instead of a fixed 50- $\Omega $ resistance reduces the leakage by compensating the antenna impedance mismatch, and improves transmitter–receiver isolation. Second, a reconfigurable summing stage adds amplitude and phase adjusted PA output signal to LNA output to cancel the residual PA output leakage. Measurement results show that the receiver achieves a reduction of 90 dB for a single tone and more than 50 dB for a QPSK modulated 40-MHz bandwidth transmit signal. The receiver gain is more than 10 dB and the noise figure in the receiver path is 4.5 dB. The reconfigurable quasi-circulator along with the receiver LNA is designed and fabricated on a 130-nm CMOS technology. The cancellation circuitry occupies 0.27 mm2 and consumes 30-mW quiescent power, while the total active area of the chip is 1 mm2, and it consumes 65-mW power. [ABSTRACT FROM PUBLISHER]
- Published
- 2018
- Full Text
- View/download PDF
33. A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter With ±1.5% Frequency and ±3.6% Current-Sharing Error.
- Author
-
Sun, Ming, Yang, Zhe, Joshi, Kishan, Mandal, Debashis, Adell, Philippe, and Bakkaloglu, Bertan
- Subjects
CONVERTERS (Electronics) ,PULSE width modulation transformers ,ELECTRIC circuits - Abstract
A four-phase, quasi-current-mode hysteretic buck converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3–9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual converter phases can be disabled, and the final stage power converter output stage is segmented for high efficiency. The dc–dc converter achieves 93% peak efficiency for Vi= 2 V and Vo= 1.6 V. [ABSTRACT FROM AUTHOR]
- Published
- 2017
- Full Text
- View/download PDF
34. A High Slew-Rate Adaptive Biasing Hybrid Envelope Tracking Supply Modulator for LTE Applications.
- Author
-
Jing, Yue and Bakkaloglu, Bertan
- Subjects
- *
LONG-Term Evolution (Telecommunications) , *POWER amplifiers , *IDDQ testing , *ELECTRONIC modulators , *ENERGY consumption - Abstract
A linear-switch mode hybrid envelope tracking (ET) supply modulator utilizing adaptive biasing and gain enhanced current mirror operational transconductance amplifier (OTA) with class AB output stage in parallel with a switching regulator is presented. In comparison to a conventional OTA design with similar quiescent current consumption, proposed approach improves positive and negative slew rate from 50 to 93.4 V/ \mu \texts and −87 to −152.5 V/ \mu \texts , respectively, dc gain from 45 to 67 dB while consuming same amount of quiescent current. The proposed hybrid supply modulator achieves 83% peak efficiency, power-added efficiency (PAE) of 42.3% at 26.2 dBm for a 10-MHz 7.24-dB peak-to-average power ratio (PAPR) long-term evolution (LTE) signal and improves PAE by 8% at 6 dB back off from 26.2-dBm power amplifier (PA) output power with respect to fixed supply. With a 10-MHz 7.24-dB PAPR quadrature-phase shift keying LTE signal the ET PA system achieves adjacent channel leakage ratio (ACLR) of −37.7 dBc and error vector magnitude (EVM) of 4.5% at 26.2-dBm PA output power, while with a 10-MHz 8.15-dB PAPR 64QAM LTE signal the ET PA system achieves ACLR of −35.6 dBc and EVM of 6% at 26-dBm PA output power without digital predistortion. The proposed supply modulator core circuit occupies 1.1-mm2 die area, and is fabricated in a 0.18- \mu \textm CMOS technology. [ABSTRACT FROM AUTHOR]
- Published
- 2017
- Full Text
- View/download PDF
35. Low-Power/Low-Voltage Integrated CMOS Sense Resistor-Free Analog Power/Current Sensor Compatible With High-Voltage Switching DC–DC Converter.
- Author
-
Singh, Shrikant, Mandal, Debashis, Bakkaloglu, Bertan, and Kiaei, Sayfe
- Subjects
COMPLEMENTARY metal oxide semiconductors ,SWITCHED capacitor circuits ,ELECTRIC power conversion ,DIGITAL signal processing ,GALVANIC isolation ,CAPACITOR switching ,MAXIMUM power point trackers ,ANALOG multipliers - Abstract
A sensor circuit to measure the output power of a dc–dc boost for photo-voltaic (PV) maximum power point tracking (MPPT) application is presented. The proposed approach obviates the need for a series current sense resistor and a complex current/voltage digitization and multiplication circuitry required for calculating power. Thereby, this technique does not require analog multipliers, analog-to-digital converters, digital signal processor, and FPGA, thus reducing the bill of material, silicon area, and power consumption of the overall system. Additionally, it provides the dc electrical isolation between the high output voltage of the boost converter and the low-voltage integrated CMOS power sensor circuit. The proposed power sensor circuit is implemented using a switched capacitor differentiator and a voltage-to-time converter. This approach results in lower complexity, lower silicon area, lower power consumption, and lower component count for the overall PV MPPT system. Designed in a 180-nm CMOS process, the circuit can operate with a supply voltage of 1.8 V. It achieves a power sense accuracy of 7.6%, occupies a die area of 0.0519 mm2, and consumes a power of 0.748 mW. [ABSTRACT FROM AUTHOR]
- Published
- 2019
- Full Text
- View/download PDF
36. Microwave Week 2015 Starts with RFIC.
- Author
-
Bakkaloglu, Bertan, Wang, Albert, and Kobayashi, Kevin
- Published
- 2015
- Full Text
- View/download PDF
37. A 50-mA 99.2% Peak Current Efficiency, 250-ns Settling Time Digital Low-Dropout Regulator With Transient Enhanced PI Controller.
- Author
-
Lim, Chaiyong, Mandal, Debashis, Bakkaloglu, Bertan, and Kiaei, Sayfe
- Subjects
SYSTEMS on a chip ,DIGITAL control systems ,ANALOG-to-digital converters ,TRANSIENT analysis ,TRANSIENT responses (Electric circuits) - Abstract
A fully integrated digital low-dropout regulator (DLDO) with a fast transient response, providing a regulated supply for system-on-chip (SoC) power management applications is proposed. Wideband operation and fast transient response are achieved through a transient enhanced proportional-integral controller, without compromising the stability of the DLDO at steady-state operation. The transient enhancement stage boosts loop-gain dynamically during load transients. In the gain boosting mode, the DLDO closed-loop bandwidth is increased, resulting in reduced undershoot/overshoot and fast settling. When the output voltage recovers to the desired level, the boost mode operation is disabled. For a load change with a 4-mA/ns slew rate between 10 and 50 mA, utilizing transient enhancement mode reduced the measured undershoot and overshoot by 35% and 17%, respectively. The characterization results show that the transient enhancement mode can reduce the settling time from 500 to 250 ns for a 10–50-mA load current change. The proposed DLDO operates with an input voltage ranging from 0.84 to 1.24 V, and output voltage ranging from 0.6 to 1 V. The maximum output current of the DLDO is 50 mA and the DLDO achieves a peak current efficiency of 99.2%, with DLDO figure of merit (FOM2) of 63.25 ps. The DLDO prototype chip is fabricated on a 0.13- \mu \textm CMOS technology and occupies a 0.0631-mm2 die area. [ABSTRACT FROM PUBLISHER]
- Published
- 2017
- Full Text
- View/download PDF
38. A Low-Noise Output Capacitorless Low-Dropout Regulator With a Switched-RC Bandgap Reference.
- Author
-
Magod, Raveesh, Suda, Naveen, Ivanov, Vadim, Balasingam, Ravi, and Bakkaloglu, Bertan
- Subjects
BAND gaps ,PINK noise ,ENERGY management ,CAPACITORS ,ELECTRIC resistors - Abstract
Low-noise linear regulators are critical for power supply regulation of noise-sensitive circuits, such as ADCs, phase-locked loops, and other mixed-signal/RF system-on-a-chip designs. A low-noise low-dropout (LN-LDO) regulator using switched-RC bandgap reference and a multiloop, unconditionally stable error amplifier for output capacitorless operation is presented in this paper. A sample-and-hold switched-RC filter is developed to reduce the noise of the bandgap reference and drain-side modulated current-mode chopping technique is proposed to reduce the flicker (1/f) noise of the error amplifier. A switched capacitor notch filter is utilized to filter out the residual chopping ripple of the error amplifier. Thermal noise of the current reference circuit which is significant at such low noise levels is also reduced by using a low-area penalty passive RC filter. These techniques reduce the total integrated output noise of the LDO in the 10 Hz to 100 kHz band from $95.3\;\mu {{\rm{V}}_{{\rm{RMS}}}}$ down to $14.8\;\mu {{\rm{V}}_{{\rm{RMS}}}} . The LDO delivers a maximum load current of 100 mA with a dropout voltage of 230 mV and a quiescent current consumption of 40\;\mu \rmA . It achieves a power supply rejection of 50 dB at 10 kHz for a programmable output voltage range of 1–3.3 V. Fabricated in a 0.25\;\mu \rmm CMOS process, the LDO core occupies an area of 0.18 mm2. [ABSTRACT FROM AUTHOR]
- Published
- 2017
- Full Text
- View/download PDF
39. A High-Voltage-Compliant Current-to-Digital Sensor for DC?DC Converters in Standard CMOS Technology.
- Author
-
Marti-Arbona, Edgar, Mandal, Debashis, Bakkaloglu, Bertan, and Kiaei, Sayfe
- Subjects
PHOTOVOLTAIC power systems ,CONVERTERS (Electronics) ,COMPLEMENTARY metal oxide semiconductors ,MAXIMUM power point trackers ,SWITCHING circuits - Abstract
Efficient current, voltage, and power sensing are critical blocks for power management, switching regulators, maximum power point tracking (MPPT) circuit, and motor control. This paper presents a standard CMOS and low-power current-to-digital converter (IDC) that senses the current flowing at high-voltage nodes. The proposed sensor uses a CMOS-switched capacitor circuit to sense a dc–dc converter output current and gives digital output without an analog-to-digital converter (ADC), or the need for high-voltage technologies. Compared to the resistor-based current-sensing methods that require current-to-voltage circuit, gain block, and an ADC converter, the proposed sensor is a low-power integrated circuit that achieves high resolution, lower complexity, and lower power consumption. The IDC circuit is fabricated on a 5 V, 0.7 μm, and three metal CMOS technology and occupied less than 10% area (1 mm2 area) compared to other sensors. It consumes 18 mW that is less than 40% power consumed by other sensors, and its current measurement error is below 0.4%. The proposed IDC circuit has been characterized as standalone and with a boost dc–dc regulator and MPPT for photovoltaic systems. [ABSTRACT FROM AUTHOR]
- Published
- 2017
- Full Text
- View/download PDF
40. A 100-mA, 99.11% Current Efficiency, 2-mVpp Ripple Digitally Controlled LDO With Active Ripple Suppression.
- Author
-
Cheah, Michael, Mandal, Debashis, Bakkaloglu, Bertan, and Kiaei, Sayfe
- Subjects
ANALOG-to-digital converters ,SYSTEMS on a chip ,VOLTAGE regulators - Abstract
Digital low-dropout (DLDO) regulators are gaining attention due to their design scalability for distributed multiple voltage domain applications required in state-of-the-art system-on-chips. Due to the discrete nature of the output current and the discrete-time control loop, the steady-state response of the DLDO has inherent output voltage ripple. A hybrid DLDO (HD-LDO) with fast response and stable operation across a wide load range while reducing the output voltage ripple is proposed. In the HD-LDO, a DLDO and a low current analog ripple cancellation amplifier (RCA) work in parallel. The output dc of the RCA is sensed by a 2-bit analog-to-digital converter, and the digitized linear stage current is fed into the DLDO as an error signal. During load transients, a gear-shift controller enables fast transient response using dynamic load estimation. The DLDO suppresses the output dc of the RCA within its current resolution. With this arrangement, a majority of the dc load current is provided by the DLDO and the RCA supplies ripple cancellation current. The HD-LDO is designed and fabricated in a 180-nm CMOS technology, and occupies 0.697 mm2 of the die area. The HD-LDO operates with an input voltage range of 1.43-2.0 V and an output voltage range of 1.0-1.57 V. At 100-mA load current, the HD-LDO achieves a current peak efficiency of 99.11% and a settling time of 15 clock periods with a 0.5-MHz clock for a current switching between 10 and 90 mA. The RCA suppresses fundamental, second, and third harmonics of the switching frequency by 13.7, 13.3, and 14.1 dB, respectively. [ABSTRACT FROM AUTHOR]
- Published
- 2017
- Full Text
- View/download PDF
41. An Electrical-Stimulus-Only BIST IC for Capacitive MEMS Accelerometer Sensitivity Characterization.
- Author
-
Ozel, Muhlis Kenan, Cheperak, Mike, Dar, Tehmoor, Kiaei, Sayfe, Bakkaloglu, Bertan, and Ozev, Sule
- Abstract
Testing and calibration constitute a major part of the overall manufacturing cost of microelectromechanical system (MEMS) devices. A physical-stimulus-free built-in-self-test (BIST) integrated circuit (IC) design characterizing the sensitivity of capacitive MEMS accelerometers is presented. The BIST circuitry can extract the amplitude and phase response of the acceleration sensor’s mechanics under electrical excitation within 0.55% of error with respect to its mechanical sensitivity under physical stimulus. Sensitivity characterization is performed using a low computational complexity multi-variate linear regression model. The BIST circuitry maximizes the use of existing analog and mixed signal readout signal chain and the host processor core, without the need for computationally expensive fast Fourier transform (FFT)-based approaches. The BIST IC is designed and fabricated using the 0.18- \mu \textm CMOS technology. The sensor analog front-end and BIST circuitry is integrated with a three axis, low- g capacitive MEMS accelerometer in a single hermetically sealed package. The BIST circuitry occupies 0.3 mm ^{ { {2}}} with a total readout IC area of 1 mm ^{ { {2}}}$ , and consumes 8.9 mW during self-test operation. [ABSTRACT FROM PUBLISHER]
- Published
- 2017
- Full Text
- View/download PDF
42. Online Built-In Self-Test of High Switching Frequency DC–DC Converters Using Model Reference Based System Identification Techniques.
- Author
-
Beohar, Navankur, Malladi, Venkata N. K., Mandal, Debashis, Ozev, Sule, and Bakkaloglu, Bertan
- Subjects
DC-to-DC converters ,BUILT-in self tests (Engineering) ,PULSE width modulation transformers ,PSEUDONOISE sequences (Digital communications) ,VOLTAGE-frequency converters - Abstract
A built-in self-test (BIST) technique that enables tracking of loop parameters of integrated DC–DC converters without affecting the normal mode of operation is presented. A digital pseudo-noise based stimulus and a mixed signal cross-correlation based analysis technique is used to derive on-chip impulse response, with minimum computational requirements in comparison to a digital correlator approach. Using measured impulse response, open-loop phase margin and closed-loop unity-gain frequency are estimated within 5.2% and 4.1% error, respectively, for the load current range of 30 mA to 200 mA. Converter parameters, such as natural frequency, Q -factor, and center frequency are estimated within 3.6%, 4.7%, and 3.8% error, respectively, over load inductance of 4.7 \mu \text{H} to 10.3 \mu \text{H} , and filter capacitance of 200 nF to 400 nF. A 5 MHz switching frequency, 5 V to 8.125 V input voltage range, voltage-mode controlled DC-DC buck converter is designed for the proposed model reference based parametric and non-parametric BIST analysis. The converter output voltage range is 3.3 V to 5 V and supported maximum load current is 450 mA with a peak efficiency of 87.93%. The proposed converter is fabricated on a 0.6 \mu \textm 6 layer-metal SOI technology with a die area of 9 mm2. The system identification circuitry occupies 3.8% of the converter area with 530 \mu \textA quiescent current during operation. [ABSTRACT FROM PUBLISHER]
- Published
- 2018
- Full Text
- View/download PDF
43. A 14.8μVRMS integrated noise output capacitor-less low dropout regulator with a switched-RC bandgap reference.
- Author
-
Magod, Raveesh, Suda, Naveen, Ivanov, Vadim, Balasingam, Ravi, and Bakkaloglu, Bertan
- Published
- 2015
- Full Text
- View/download PDF
44. Enabling unauthorized RF transmission below noise floor with no detectable impact on primary communication performance.
- Author
-
Chang, Doohwang, Bakkaloglu, Bertan, and Ozev, Sule
- Published
- 2015
- Full Text
- View/download PDF
45. Disturbance-free BIST for loop characterization of DC-DC buck converters.
- Author
-
Beohar, Navankur, Bakliwal, Priyanka, Roy, Sidhanto, Mandal, Debashis, Adell, Philippe, Vermeire, Bert, Bakkaloglu, Bertan, and Ozev, Sule
- Published
- 2015
- Full Text
- View/download PDF
46. SSB transceiver for vital sign detection.
- Author
-
Khunti, Hitesh, Krehbiel, James, Cheah, Michael, Bakkaloglu, Bertan, and Kiaei, Sayfe
- Published
- 2015
- Full Text
- View/download PDF
47. Low power integrated on-chip current to digital converter.
- Author
-
Marti-Arbona, Edgar, Mandal, Debashis, Bakkaloglu, Bertan, and Kiaei, Sayfe
- Published
- 2015
- Full Text
- View/download PDF
48. PV panel power optimization using sub-panel MPPT.
- Author
-
Marti-Arbona, Edgar, Mandal, Debashis, Bakkaloglu, Bertan, and Kiaei, Sayfe
- Published
- 2015
- Full Text
- View/download PDF
49. Monitor-Based In-Field Wearout Mitigation for CMOS LC Oscillators.
- Author
-
Chang, Doohwang, Kitchen, Jennifer N., Bakkaloglu, Bertan, Kiaei, Sayfe, and Ozev, Sule
- Abstract
Failure due to aging mechanisms is an important concern for RF circuits. In-field aging results in continuous degradation of circuit performances before they cause catastrophic failures. In this regard, the lifetime of RF/analog circuits, which is defined as the point where at least one specification fails, is determined not only by aging at the device level but also by the slack in the specifications, process variations, and the stress conditions on each of the devices. In this paper, we present a methodology for analyzing, monitoring, and recovering performance degradation in cross-coupled \textLC oscillators caused by aging mechanisms in MOSFET devices. At design time, we identify reliability hot spots and concentrate our efforts on improving these components. We also identify the circuit variable that is easy to measure but highly correlated to the performance of the primary circuit and codesign the monitoring and reconfiguration mechanism along with the primary circuit. Experimental results with a fabricated oscillator chip show that the phase noise of the oscillator degraded by 1.5 dB over ten days (240 h) of accelerated stress conditions, and this loss can be recovered by the proposed mitigation scheme. [ABSTRACT FROM PUBLISHER]
- Published
- 2016
- Full Text
- View/download PDF
50. Design-Time Reliability Enhancement Using Hotspot Identification for RF Circuits.
- Author
-
Chang, Doohwang, Kitchen, Jennifer N., Bakkaloglu, Bertan, Kiaei, Sayfe, and Ozev, Sule
- Subjects
ELECTRODIFFUSION ,METAL oxide semiconductor field-effect transistors ,HOT carriers ,RELIABILITY in engineering ,THRESHOLD voltage ,MATHEMATICAL models - Abstract
Failure due to aging mechanisms in CMOS devices is an important concern of RF circuits. Lifetime of analog/RF circuits is defined as the point where at least one specification will fail due to aging effects. In this brief, we present a methodology for analyzing the performance degradation of RF circuits caused by aging mechanisms in MOSFET devices and inductors at design time (presilicon). We identify reliability hotspots and concentrate on these circuit components to enhance the lifetime with low area and no performance impact. [ABSTRACT FROM PUBLISHER]
- Published
- 2016
- Full Text
- View/download PDF
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