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A normally-off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (HV, e.g., 1200 V) silicon-carbide (SiC) junction field effect transistor (JFET) delivering the HV blocking capability and a low-voltage (LV) enhanced-mode (E-mode) gallium-nitride (GaN) high electron mobility transistor (HEMT) providing the normally-off gate control. This all-wide-bandgap device exhibits superior thermal stability and high switching speed compared to its counterparts, e.g., the SiC/Si cascode device. In this article, we study short-circuit (SC) characteristics of a 1200-V/80-mΩ SiC/GaN cascode device by considering the interactions between the SiC and GaN devices. The single-event SC withstand time (SCWT) of the demonstrated SiC/GaN cascode device is tested to be ∼3 μs under a dc-bus voltage (Vdc) of 600 V when the turn-on gate voltage (VG-on) is set to 5 V. The SC failure occurs due to the formation of hot spots induced by thermal-runaway leakage currents inside the SiC JFET. The SCWT of the cascode device could be improved by applying a moderate VG-on (e.g., SCWT = ∼6.5 μs at VG-on = 3.5 V under v dc = 600 V) without affecting the on-state resistance (r on). However, it is identified that current oscillations tend to be triggered during the SC period when VG-on is too low (e.g., lower than 3 V). The oscillation behavior is attributed to the energy stored in the interconnection parts between the SiC and GaN devices. The harmful oscillations could be suppressed by applying higher VG-on, which drives the SiC JFET into low-transconductance mode by modulating the drain-to-source voltage (VDS-G) of the LV GaN HEMT. [ABSTRACT FROM AUTHOR]

With a switching drain bias, the gate reliability of Schottky-type ${p}$ -GaN gate high-electron-mobility transistors (HEMTs) under AC positive gate bias stress has been systematically investigated. The mean-time-to-failure (MTTF) under such application-relevant stress is found to be prolonged compared to that extracted from static and AC gate bias stress tests with the absence of a switching drain bias and exhibits positive coefficients with frequency and OFF-state drain bias (${V} _{\text {DSQ}}$). Such results can be explained by the drain-induced hole insufficiency in the gate stack at large ${V} _{\text {DSQ}}$ , a physical mechanism that results in elevated energy band at ON-state when ${V} _{\text {DSQ}}$ is just switched to low voltage. This non-equilibrium transient status could suppress injection of electrons from the 2DEG channel to the ${p}$ -GaN gate, which in turn substantially weakens the hot-electron’s generation in the depleted ${p}$ -GaN layer and the subsequent bombardment to the gate-metal/ ${p}$ -GaN interface, and thus prolongs the gate lifetime. [ABSTRACT FROM AUTHOR]

A 650-V/84-mΩ normally-off GaN/SiC cascode device is demonstrated with systematic static and dynamic characterizations. The cascode device features a low-voltage enhancement-mode (E-mode) gallium nitride (GaN) high electron mobility transistor (HEMT) to enable normally-off gate control, and a 650-V normally-on silicon carbide (SiC) JFET provides the high-voltage blocking capability. The GaN/SiC cascode device exhibits many application-desired behaviors, including reverse conduction capability, avalanche breakdown capability, thermally stable threshold voltage, low input/output capacitances, no dynamic RON degradation, and negligible dynamic VTH shift. In addition, a customized double-pulse test board is built to evaluate the switching performance of this cascode device and other 650-V SiC-based power devices. This cascode device adopting low-voltage GaN HEMT has low QG×RON and exhibits excellent switching performance. The switching losses (EON and EOFF) are much smaller than that of the 650-V Si/SiC cascode device and comparable to that of the state-of-the-art 650-V SiC MOSFETs. [ABSTRACT FROM AUTHOR]

The high-speed superiority of GaN power devices with silicon-based peripheral circuits is not yet fully leveraged, mainly due to the parasitic inductance of interconnections. In this article, we demonstrate a GaN-based gate driver with an overcurrent (OC) protection circuit and an undervoltage lockout (UVLO) circuit on a p-GaN gate power HEMT platform. The gate driver features a rail-to-rail output voltage, suppressed gate ringing, and tunable driving speed, all of which are highly desired in high-efficiency and high-speed GaN power systems. To offer timely but reliable protections, the OC protection and UVLO circuit are designed with reference to the switching speed and the threshold voltage of GaN power devices. The OC protection is implemented with a separated sensing branch and blanking time controller, and the response time to an OC event is reduced to 10 ns after the blanking time. The UVLO circuit has a fixed hysteresis of 0.5 V, and its threshold voltage is especially tailored for the GaN integrated circuits. [ABSTRACT FROM AUTHOR]

In this article, the impacts of the off-state gate bias (VGS,OFF) on dynamic on-resistance (RON) are systematically investigated in commercial Schottky-type p-GaN Gate high-electron-mobility transistors. Double-pulse tester and pulsed I–V system are adopted to evaluate the dynamic RON with various off-state gate and drain bias (VDS,OFF) under hard- and soft-switching conditions. More negative VGS,OFF can aggravate the dynamic RON degradation under both soft- and hard-switching, especially when switching with a high VDS,OFF. The impacts of VGS,OFF on switching transients and off-state stress are investigated separately to reveal the underlying mechanisms, which are found to be associated with the generation and movements of holes. The off-state gate bias of the voltage-driving scheme needs to be carefully considered according to the identified mechanisms in terms of dynamic on-resistance degradation. [ABSTRACT FROM AUTHOR]

The threshold voltage (VTH) of an enhancement-mode Schottky-type p-GaN gate high-electron-mobility transistor (HEMT) is found to have a special dependence on the drain bias. The device commonly requires higher gate voltage to switch on the transistor from a high-drain-voltage off-state than what is expected from the static device characteristics. The reason behind the dynamic VTH has been proved to be the floating p-GaN layer, where charges could be stored and further influence VTH under different drain bias. In this article, a SPICE-compatible equivalent circuit model is presented according to the structure of Schottky-type p-GaN gate HEMTs. It features a floating node to imitate the charge storage process within the gate stack. Compared to conventional models, the proposed model could accurately predict the dynamic VTH characteristics and switching behaviors of power electronics circuits, where Schottky-type p-GaN gate HEMTs are deployed as power transistors. The phenomena related to the dynamic VTH, including the disappearance of Miller plateau, the overestimated false-turn-on problem, and the higher reverse conduction loss are evaluated with a half-bridge circuit and the merits of the proposed model are verified. [ABSTRACT FROM AUTHOR]

The dynamics of the intrinsic threshold voltage (VTH) shift in 650-V Schottky-type p-GaN gate HEMT under high-frequency switching is investigated by a bootstrap voltage clamping circuit in which the GaN HEMT serves as the key bootstrapping device. This new testing setup covers a wide range of OFF-state drain bias (VDSQ) up to 400V, a short OFF-to-ON (or stress-to-sense) delay (Tdelay) of 60ns, and a high switching frequency (ƒsw) up to 2MHz. The dynamic VTH’s dependences on VDSQ and ƒsw are characterized by this testing setup. A higher VDSQ (up to 400V) results in a larger dynamic VTH shift (Δ VTH). The Δ VTH exhibits a gradually increasing trend under the continuous high-frequency switching mode. In addition, after continuous switching operation for 200 μs, the maximum Δ VTH shows no ƒsw dependence with a wide range of frequency from 50kHz to 2MHz. [ABSTRACT FROM AUTHOR]

Systematic characterizations of a cascode device with a low-voltage enhance-mode (E-mode) p-GaN gate high-electron mobility transistor as the control device and a high-voltage (HV) depletion-mode (D-mode) silicon carbide junction field effect transistor (JFET) as the voltage blocking device are presented in this article. The demonstrated device with a breakdown voltage rating of 1200 V and a static on-resistance (RON) of 100 mΩ features small device capacitances with fast switching speed, avalanche breakdown capability, thermally stable threshold voltage (VTH), and no dynamic RON degradation. To identify its safe operation in the off-state with a high drain bias, the off-state middle point voltage (VM) between the E-mode device drain and D-mode device source is investigated. A relatively low off-state VM is achieved under both static and dynamic modes. In addition to the device-level characterization, a custom-designed double-pulse test circuit is built to evaluate the transient switching performance of the cascode device. Optimal gate drive conditions are proposed to 1) overcome the drain bias induced positive dynamic VTH shift; and 2) suppress the increased dynamic off-state leakage current (IOFF) induced by on-state hole injection. Under 800 V/16 A testing conditions, high switching speed with the drain voltage peak slew rates of 72 V/ns during turn-on and 121 V/ns during turn-off is achieved. [ABSTRACT FROM AUTHOR]

A 1200-V/100-mΩ silicon carbide (SiC) junction field-effect-transistor (JFET)/ gallium nitride (GaN) high-electron-mobility-transistor (HEMT) hybrid power switch is demonstrated, which features a flip-chip copackaged cascode configuration incorporating a vertical SiC JFET and a lateral GaN-HEMT. The high-voltage SiC-JFET provides the high-voltage blocking capability while the low-voltage GaN-HEMT enables the normally-off gate control with superior switching characteristics. Compared to conventional SiC-JFET/Si-mosfet cascode devices, the SiC-JFET/GaN-HEMT cascode device exhibits fast switching speed, which has been validated by systematic characterizations including static/dynamic device-level measurements and board-level hard-switching tests. Meanwhile, the device is free from several notorious issues of high-voltage GaN power transistors such as dynamic on-state resistance degradation and threshold voltage shift. Such a wide-bandgap semiconductor-based hybrid switch is suitable to be deployed in high-power and high-efficiency power conversion systems. [ABSTRACT FROM AUTHOR]

In this paper, systematic characterization and the corresponding suppression strategies of dynamic OFF-state leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) are presented based on fast pulsed ${I}$ – ${V}$ measurement and consecutive switching measurement. It is found that the high ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under dynamic pulse mode without hole injection is a result of the reduced voltage blocking capabilities (both lateral and vertical) with weaker trapping effect in the buffer, and the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection is caused by further increased lateral conductivity through the buffer from source to drain. The corresponding behaviors under continuous waveforms with different switching conditions are analyzed to identify effective approaches for the suppression of dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ in practical switching operations. A higher temperature is shown to be beneficial to the reduction of the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection. To completely eliminate the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ caused by ON-state hole injection and minimize the OFF-state power consumption in practical power switching applications, a sufficiently large negative OFF-state gate bias (e.g., ${V}_{\text {GS}, \mathrm{\scriptscriptstyle OFF}}\le -{3}$ V) is recommended in the gate driver turn-off voltage design for the Schottky-type p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

The drain induced dynamic threshold voltage (${V}_{\textrm {th}}$) shift of a ${p}$ -GaN gate HEMT with a Schottky gate contact is investigated, and the underlying mechanisms are explained with a charge storage model. When the device experiences a high drain bias ${V}_{\textrm {DSQ}}$ , the gate-to-drain capacitance (${C}_{\textrm {GD}}$) is charged to ${Q}_{\textrm {GD}}$ (${V}_{\textrm {DSQ}}$). As the drain voltage drops to ${V}_{\textrm {DSM}}$ where ${V}_{\textrm {th}}$ is measured, ${C}_{\textrm {GD}}$ is expected to be discharged to ${Q}_{\textrm {GD}}$ (${V}_{\textrm {DSM}}$). However, the metal/ ${p}$ -GaN Schottky junction could block the discharging current, resulting in storage of negative charges in the ${p}$ -GaN layer. For the device to turn on, additional gate voltage is required to counteract the stored negative charges, resulting in a positive shift of ${V}_{\textrm {th}}$. The dynamic ${V}_{\textrm {th}}$ shift is an intrinsic and predictable characteristic of the ${p}$ -GaN gate HEMT which is linearly correlated with $\Delta \!{Q}_{\textrm {GD}}={Q}_{\textrm {GD}}$ (${V}_{\textrm {DSQ}}$) $- {Q}_{\textrm {GD}}$ (${V}_{\textrm {DSM}}$). The ${V}_{\textrm {th}}$ shift is dependent on ${V}_{\textrm {DSQ}}$ as well as ${V}_{\textrm {DSM}}$ , indicating that the ${V}_{\textrm {th}}$ shift is varying along the load line during a switching operation. [ABSTRACT FROM AUTHOR]

Commercially available normally-off GaN power high-electron-mobility transistor (HEMT) devices have typically adopted a p-GaN gate structure. In the gate region, there exist a Schottky junction (between gate electrode and the p-GaN layer) and a p-GaN/AlGaN/GaN heterojunction. As the p-GaN layer is not directly shorted to the gate electrode and conducting channel, it can be considered as electrically “floating.” With drain voltage changing during a switching process, the variation of net charge in the floating p-GaN layer would cause instability in threshold voltage. Besides, because of the distinctive features of the p-GaN gate HEMT structure under certain gate/drain bias, gate-related junction capacitances would exhibit behavior different from those of a Si mosfet. Consequently, the switching transient performance of a GaN transistor with a p-GaN gate could be significantly influenced by the aforementioned factors. In this work, the threshold voltage instability associated with the drain-to-gate voltage stress is first analyzed. Despite the difficulty in directly performing capacitance measurements inside the device structure, a hybrid physical-behavior modeling method is proposed. The model is capable of extracting the capacitance bias relationships with regard to the gate region from static terminal measurements. In previous works, the advanced analytical model would make modest change on a Si mosfet's model. As a result, without fully considering the specific features of a GaN transistor with the p-GaN gate, the simulated waveforms would exhibit 20–50% discrepancy from the experiment. In contrast, the proposed switching transient analytical approach would exhibit improved accuracy (<10% disparity). Consequently, the switching transient performance of the GaN transistor with the p-GaN gate could be more accurately evaluated. [ABSTRACT FROM AUTHOR]

A new silicon power MOSFET architecture is proposed by introducing a built-in channel diode through a dummy MOS gate electrically coupled to the source. The oxide thickness of the channel diode is reduced to obtain a desired turn-ON voltage and attenuate the minority carrier injection from the PN junction body diode. Consequently, the proposed MOSFET is able to deliver superior reverse recovery characteristics, including reductions in reverse recovery charge ($Q_{\sf RR}$) and peak reverse recovery current ($I_{\mathrm{ RRM}}$) by a factor of ~4.2 and ~2.6, respectively. The breakdown voltage (232 V) of the proposed MOSFET is the same as the conventional MOSFET. The on-resistance of the proposed MOSFET (8.5 $\text{m}\Omega \cdot \text {cm}^{{2}}$) is only slightly increased compared with conventional MOSFET (8.0 $\text{m}\Omega \cdot \text {cm}^{{2}}$). The gate-to-drain charge ($Q_{\sf GD}$) and gate charge (${Q} _{\mathsf {G}}$) are reduced by a factor of ~7.2 and ~3.9, respectively. Significantly improved figures of merit (${R} _{ON} \times {Q}_{\mathsf {G}}$ and ${R} _{ON} \times {Q}_{\mathsf {GD}}$ reduced by a factor of ~3.7 and ~6.8, respectively) are obtained in the proposed MOSFET. The device concept and characteristics are systematically analyzed with numerical TCAD simulations. [ABSTRACT FROM AUTHOR]

The OFF-state drain leakage characteristics in 600-V p-GaN HEMTs with an ohmic gate contact are investigated under dynamic switching conditions instead of commonly used quasi-static measurement setup. It is found that fast dynamic OFF-state leakage current (dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$) is substantially higher than the slow-ramping quasi-static ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ due to the weaker trapping effect in the buffer layer. With sufficiently large positive ON-state gate bias, further increase in dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ is observed and is attributed to ON-state hole injection that leads to energy band lowering in the buffer. The underlying physical processes are explained by the dynamic behavior of the traps in the buffer layer. This letter indicates that the ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under practical switching operations is much higher than the static measurement results and should be used to evaluate dynamic OFF-state power consumption in the p-GaN HEMTs with an ohmic gate contact. [ABSTRACT FROM AUTHOR]

An MOS field plate-protected Schottky-drain (gated Schottky-drain) is successfully integrated on a double-channel AlGaN/GaN MOS-HEMT to provide reverse blocking capability. The leakage suppression MOS field plate is deployed on the etched upper GaN channel layer after a barrier fully recess process, leading to a low reverse OFF-state leakage current of −20 nA/mm (at −100 V). The drain metal is deployed adjacent to the MOS field plate, contacting the upper MOS-channel and lower heterojunction channel from the sidewall. A metal-2DEG Schottky contact with a low turn-ON voltage of 0.5 V is achieved. Since the lower channel (below the MOS field plate) is separated from the etched surface of upper GaN channel layer, a high-conductivity MOS-gated channel with a sheet resistance of 806 $\Omega$ /Square is obtained. The device exhibits a threshold voltage of +0.6 V (at $10~\mu \text{A}$ /mm and +1.9 V from linear extrapolation) and an ON-resistance of ~18 $\Omega {\cdot} \text {mm}$. Besides, a high forward (and reverse) breakdown voltage of 790 V (and −656 V, all at $10~\mu \text{A}$ /mm) is achieved. [ABSTRACT FROM AUTHOR]

Compared with the state-of-the-art Si-based power devices, enhancement-mode Gallium Nitride (E-mode GaN) transistors have better figures of merit and exhibit great potential in enabling higher switching frequency, higher efficiency, and higher power density for power converters. The bridge-leg configuration circuit, consisting of a controlling switch and a synchronous switch, is a critical component in many power converters. However, owing to the low threshold voltage and fast switching speed, E-mode GaN devices are more prone to false turn-on phenomenon in bridge-leg configuration, leading to undesirable results, such as higher switching loss, circuit oscillation, and shoot through. In order to expand gate terminal's safe operating margin without increasing reverse conduction loss during deadtime, negative gate voltage bias for turn-off and antiparallel diode could be applied to E-mode GaN device. In this paper, with consideration of strong nonlinearities in C–V and I–V characteristics of high-voltage (650 V) E-mode GaN transistors, analytical device models are first developed. Then, we develop an analytical circuit model that combines the circuit parameters with intrinsic characteristics of the high-voltage GaN transistor and antiparallel diode. Thus, key transient waveforms with regard to the false turn-on problem can be acquired, including displacement current and false triggering voltage pulse on gate terminal. The simulated waveforms are then verified on a testing board with GaN-based bridge-leg circuit. In contrast to piecewise switching process models and PSpice simulation, the proposed model exhibits outstanding performances. To provide design guidelines for mitigating false turn-on of GaN transistor, the impacts of different circuit parameters, along with the optimum negative gate voltage bias, are investigated based on the proposed model. [ABSTRACT FROM AUTHOR]

Dynamic ON-resistance ( \mathrm RON ) of 650-V GaN-on-Si lateral power devices with a floating Si-substrate termination is investigated. Compared with the grounded substrate termination, the floating substrate could deliver smaller dynamic \mathrm RON under higher drain bias (> 400 V) switching operation, but leads to larger dynamic \mathrm RON under low-drain bias (< 400 V). The underlying physical mechanisms are explained by the tradeoff between charge storage in the Si substrate and electron trapping effect in the GaN buffer layer. [ABSTRACT FROM AUTHOR]

The systematic characterization of a 650-V/13-A enhancement-mode GaN power transistor with p-GaN gate is presented. Critical device parameters such as ON-resistance $R_{{\rm{ON}}}$ and threshold voltage $V_{{\rm{TH}}}$ are evaluated under both static and dynamic (i.e., switching) operating conditions. The dynamic RON is found to exhibit different dependence on the gate drive voltage $V_{{\rm{GS}}}$ from the static $R_{{\rm{ON}}}$. While reasonably suppressed at higher $V_{{\rm{GS}}}$ of 5 and 6 V, the degradation in dynamic RON is significantly larger at lower $V_{{\rm{GS}}}$ of 3–4 V, which is attributed to the positive shift in $V_{{\rm{TH}}}$ under switching operations. In addition to characterization of discrete devices, a custom-designed double-pulse test circuit with 400-V, 10-A test capability is built to evaluate the transient switching performance of the p-GaN gate power transistors. Optimal gate drive conditions are proposed to: 1) provide sufficient gate over-drive to minimize the impact of the $V_{{\rm{TH}}}$ shift on the dynamic $R_{{\rm{ON}}}$; and 2) leave enough headroom to save the device from excessive gate stresses. Moreover, gate drive circuit design and board layout considerations are also discussed by taking into account the fast switching characteristics of GaN devices. [ABSTRACT FROM AUTHOR]

The high OFF-state oxide field in the SiC trench MOSFET is a threat for its long term reliability, and thus hinders the wide acceptance of the SiC trench MOSFETs. In this paper, an SiC trench MOSFET with protruded p-bases (PB-MOS) is proposed, which features protruded p-bases to shield the gate oxide at the trench bottom against the high OFF-state drain voltage. Numerical device simulations based on Sentaurus TCAD verify the benefits of the structure. The OFF-state oxide field ( E\text {ox-m} ) in the PB-MOS is 1.7 MV/cm, which is dramatically lower compared to the high E\text {ox-m} of 8.6 MV/cm in the conventional trench MOSFET (C-MOS). The above benefit is achieved without sacrificing device performances. The reverse transfer capacitance ( C\text{rss} ) of the PB-MOS is around ten times lower than that in the C-MOS. Both the gate charge ( Q\text{G} ) and the gate-to-drain charge ( Q\text{GD} ) of the PB-MOS are significantly improved compared to the C-MOS. A low specific ON-resistance ( R\text{ON} ) is maintained in the PB-MOS by using additional JFET doping to compensate the JFET effect. As a result, the PB-MOS presents much better figures of merit Q\text{G} \cdot { {R}}\text{ON} and Q\text{GD} \cdot { {R}}\text{ON} than those of the C-MOS. The PB-MOS achieves a much faster switching speed than the C-MOS, and consequently exhibits an appreciable reduction in the switching energy loss. [ABSTRACT FROM PUBLISHER]

A p-type shield region (p-shield) under the gate trench is typically adopted in a SiC trench MOSFET for achieving a lower oxide field and reverse transfer capacitance ( Crss) . This paper comparatively studies the effects of a grounded p-shield and a floating p-shield. Device simulations using Sentaurus TCAD are carried out in this paper to reveal the devices’ internal dynamics. The floating p-shield can effectively reduce the OFF-state oxide field as a grounded p-shield does, without degrading its static performance. However, after being switched from the OFF-state, the ON-state oxide field in the trench MOSFET with a floating p-shield (FS-MOS) is dramatically elevated. Compared with the trench MOSFET with a grounded p-shield, the FS-MOS also exhibits a higher C{{\text {rss}}} and a consequently slower switching speed. Furthermore, the FS-MOS exhibits a degradation of dynamic R{ \mathrm{ON}} during switching operation. A charge storage mechanism is then presented to explain the dynamics in FS-MOS. Upon a high V{{\text {DS}}} , holes are emitted from the floating p-shield when the parasitic p-n-p structure consisting of p-shield, p-body, and n-region between them is punched through, leaving negative charges in the floating p-shield even when the high V{{\text {DS}}} is removed. Based on this mechanism, the behaviors of the FS-MOS are well explained. [ABSTRACT FROM AUTHOR]

In this paper, we present a comprehensive reviewand discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated. Comparisonwith other competingpower device technology, such as Si superjunction-MOSFET and SiC MOSFET, is also presented and analyzed. Critical issues for commercialization of GaN-on-Si power devices are discussed with regard to cost, reliability, and ease of use. [ABSTRACT FROM AUTHOR]

The switching behavior of on-chip photon sources, i.e., the p-doping-free Schottky-on-heterojunction light-emitting diodes (SoH-LEDs), which can be seamlessly integrated into the AlGaN/GaN-on-Si power high electron mobility transistors platform is investigated. It is demonstrated that the electroluminescence (EL) from an interdigital SoH-LED can be switched at least up to 10 MHz, fulfilling the requirement of most power switching circuits. In order to evaluate the EL switching limit of SoH-LEDs, a quantitative analysis of the dependence of junction current on operating frequency at different dc biases is performed based on S-parameter characteristics. At a criterion of junction-current/input-current to 50%, the cutoff frequency of an interdigital SoH-LED is obtained to be 210 MHz at a forward bias of 4 V. This letter proves that the SoH-LED is adequately fast for being employed as an on-chip synchronous photon source in GaN power switching applications. [ABSTRACT FROM PUBLISHER]

In this paper, static and dynamic performances of an AlGaN/GaN-on-Si power FET utilizing the integrated photonic-ohmic drain (PODFET) were systematically investigated. The operational mechanisms of the PODFET, including both the conditions of photon generation and the related physical processes, were explained. The dynamic switching tests were carried out under two types of hard switching conditions. With the photon generation and channel current inherently switched ON and OFF in synchronization, the dynamic performances of the PODFET can be significantly enhanced owing to photon pumping of deep electron traps. In addition, the generated photons were proved to be confined in proximity of the drain terminal without causing adverse effects on the device performances (e.g., the OFF-state leakage degradation). [ABSTRACT FROM PUBLISHER]

In this letter, we demonstrate an integrated process that illustrates the compatibility of AlN/SiNx passivation with high-performance (i.e. low leakage and high breakdown) low-pressure chemical vapor deposition (LPCVD) SiNx gate dielectric for GaN-based MIS-HEMT. It is shown that the AlN/SiNx passivation structure maintains its superior capability of suppressing the current collapse after enduring high temperature of 780 °C during the LPCVD-SiNx deposition. The AlN/SiNx passivation is shown to be significantly better than the LPCVD-SiNx passivation by delivering small dynamic $R_{{\mathrm{\scriptscriptstyle ON}}}$ degradation, especially under high drain bias switching with $V_{{\mathrm{DS}}} > 100$ V. [ABSTRACT FROM PUBLISHER]

Very fast transients of V {\text {TH}} shift and their impact on R\mathrm{\scriptscriptstyle ON} under dynamic AC (1 k–1 MHz) positive gate stress in depletion-mode (D-mode) metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) are revealed. We achieve data acquisition within 120 ns right after each stress pulse throughout the entire stress time range from 10^ -7 up to 10^ 3 s, by virtue of a short stress-to-sense delay of \sim 100 ns and high sampling rate up to 50 MSa/s. Despite the considerable V_{\mathrm {\mathbf {TH}}} shift, its impact on R\mathrm{\scriptscriptstyle ON} in D-mode MIS-HEMT is modest, if the device is under sufficient gate overdrive. Furthermore, V_{\mathrm {\mathbf {TH}}}$ shift and the consequent R\mathrm{\scriptscriptstyle ON} increase under dynamic stress, which are more relevant to high-frequency switching operation, exhibits frequency dependence within 1 k–1 MHz and is always smaller than that under conventionally used static (constant) stress. [ABSTRACT FROM PUBLISHER]

We investigate in detail the influence of AlN passivation on dynamic ON-resistance ( \(R_{\mathrm{{\scriptstyle ON}}}\) ) and electric field ( \(E\) -field) distribution in high-voltage AlGaN/GaN high electron mobility transistors (HEMTs) on a Si substrate based on pulsed \(I\) – \(V\) measurements, electroluminescence (EL) microscopy, and 2-D physics-based numerical device simulations. It is found that the dynamic \(R_{\mathrm{{\scriptstyle ON}}}\) increase has been significantly suppressed to below 10% at various temperatures ranging from −50 to 200 °C owing to the effective and robust compensation of deep acceptor-like trap states at the AlN/GaN (passivation/cap) interface by the additional positive polarization charges induced in the epitaxial AlN thin passivation layer grown in a plasma-enhanced atomic layer deposition system. To the best of our knowledge, this is the first time that highly suppressed current collapse in an AlGaN/GaN HEMT on a Si substrate within a wide temperature range is ever reported. By monitoring the dynamic \(R_{\mathrm{{\scriptstyle ON}}}\) for 100 consecutive 133-kHz switching cycles, its variation is observed to be less than 2.5%, indicating excellent stability of the passivation effectiveness. The electric field in an AlN-passivated device is found to be well confined at the drain-side gate edge, as shown in EL measurement and numerical simulation results. This phenomenon directly suggests that the virtual gate effect arising from surface trap charging has been effectively alleviated by the AlN passivation technique. [ABSTRACT FROM AUTHOR]

High-frequency and high-temperature dynamic performance of plasma-enhanced atomic layer deposition AlN-passivated enhancement-mode GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) has been investigated under hard switching conditions. Low dynamic ON-resistance ( $R_{{\mathrm{{\scriptscriptstyle ON}}}})$ degradation with small frequency dispersion and weak temperature dependence is obtained. The effectiveness of AlN passivation in suppressing current collapse is proved even under hard switching operations, which, according to other reports of SiNx-passivated devices, could worsen the dynamic $R_{{\mathrm{{\scriptscriptstyle ON}}}}$ degradation due to the trapping of additional hot electrons. [ABSTRACT FROM AUTHOR]

An effective passivation technique for AlGaN/GaN high-electron-mobility transistors (HEMTs) is presented. This technique features an AlN thin film grown by plasma-enhanced atomic layer deposition (PEALD). With in situ remote plasma pretreatments prior to the AlN deposition, an atomically sharp interface between ALD-AlN and III-nitride has been obtained. Significant current collapse suppression and dynamic ON-resistance reduction are demonstrated in the ALD-AlN-passivated AlGaN/GaN HEMTs under high-drain-bias switching conditions. [ABSTRACT FROM AUTHOR]