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Advantages of the building-in reliabiity (BIR) methodology for semiconductor manufacturing are identified and discussed.

The isothermal electromigration (EM) test at wafer level can greatly reduce the test time from months to minutes. This plausible feature makes inline reliability monitor a promising approach to enhance product reliability. Although most wafer-level reliability (WLR) tests are applied for process monitors and comparisons, their applicability for qualification will be justified. The correlation between package-level reliability (PLR) and the isothermal EM is necessary and is discussed in this paper. Besides failure analysis, the 95% confidence interval of activation energy is constructed. Since the sizes of voids formed at isothermal EM are much smaller than those at PLR EM tests, the failure criterion should be changed (i.e., using a smaller [DELTA] R). Issues for better test structure designs are described and verified. Generally, the straight-line test structure with four pads is recommended for the isothermal EM tests because of the uniform temperature profile. An extensive example is provided to illustrate the procedures on isothermal EM tests for WLR control. In the example, we propose using [t.sub.50] for routine Cpk review and the slope of the fitting line to monitor the degradation. The spec limits can be obtained based on customers' or internal reliability goals. Index Terms--Black model, confidence interval, control limit, Cpk, Ea, EM, FA, isothermal, PLR, WLR, WLRC.

System burn-in can get rid of more residual defects than component and subsystem burn-ins because incompatibility exists not only among components, but also among different subsystems and at the system level. There are two major disadvantages for performing the system burn-in: the high burn-in cost and the complicated failure rate function. This paper proposes a nonparametric approach to estimate the optimal system burn-in time. The Anderson-Darling statistic is used to check the constant failure rate (CFR), and the pool-adjacent-violator (PAV) algorithm is applied to 'unimodalize' the failure rate curve. Given experimental data, the system burn-in time can be determined easily without going through complex parameter estimation and curve fittings.

A nonlinear model has been developed to find optimal burn-in times for all levels and optimal redundancy for every subsystem. It shows that reliability of the target system can be achieved by lowering the incompatibility or component hazards rates. The system reliability is susceptible to the compatibility level of the initial system. Burn-in times increase due to decreases in burn-in cost because it is more useful to burn-in items than to raise the subsystem numbers.

Advancement in integrated circuit (IC) brings a series of challenges on product reliability. In order to meet these challenges and fulfill customers’ requirements, we introduced the methodology of building-in reliability (BIR) into whole stages during IC manufacturing. The wafer-level reliability (WLR) is an essential element of the BIR system. Significant amount of costs, resources, and times are saved from the early detections on reliability deficiencies at design and development stages. After successful mass production, hidden reliability risks can also be timely identified before shipment. Currently, the process reliability has been successfully evaluated by WLR platform. However, the product reliability, which covers much wider reliability factors, has not been effectively covered by WLR. Currently, we still rely on the conventional package-level reliability (PLR) tests to assess product reliability. In this paper, we report how the classical static random access memory (SRAM) is transplanted into the WLR system, which serves as an efficient platform to detect reliability weakness. In our extended BIR methodology, by reasonable test structure and pattern designs, proper electric parameters selections, test methods optimizations, we can thoughtfully consider inherent failure mechanisms and process fluctuations in order to build quantitative reliability models, which are essential to our proposed system. The quantitative reliability model was not seen in the similar WLR approaches and this may explain why these previous proposals failed. Finally, we report the obtained robust correlations between single-bit cell wear-out and package-level SRAM degradations, which is further validated by conventional HTOL tests. Our approaches provide opportunities not only on early detecting reliability weakness, but also on reliability assurance after product deliveries. These two contributions are essential and especially crucial for advanced technology developments. [ABSTRACT FROM AUTHOR]

Identification of the defective patterns of the wafer maps can provide insights for the quality control in the semiconductor wafer fabrication systems (SWFSs). In real SWFSs, the collected wafer maps are usually imbalanced from the defective types, which will result in misidentification. In this paper, a novel deep learning model called adaptive balancing generative adversarial network (AdaBalGAN) is proposed for the defective pattern recognition (DPR) of wafer maps with imbalanced data. In addition, a categorical generative adversarial network is improved to generate simulated wafer maps in high fidelity and classify the patterns with high accuracy for all defective categories. Taking consideration of the various learning abilities of the DPR model for different patterns into account, an adaptive generative controller is designed to balance the number of samples of each defective type according to the classification accuracy. The experiment results indicated that the proposed AdaBalGAN model outperforms conventional models with higher accuracy and stability for the DPR of wafer maps. Further results of comparative experiments revealed that the proposed adaptive generative mechanism can enhance and balance the recognition accuracy for all categories in the DPR of wafer maps. [ABSTRACT FROM AUTHOR]

The semiconductor manufacturing is one of the most sophisticated processes in modern industries. It contains hundreds of complex operations, and this makes semiconductor reliability a challenging task especially in recent years that integrated circuits (ICs) have been broadly used at much wider areas including the health cares, automotive, and aerospace applications, where safety is the major concern. To make things worse, due to the shorter product life cycles and severe competitions, time-consuming reliability tests become unacceptable. The industries are in urgent need of a fast and effective way to quickly assess reliability risks. Under all these stringent limitations and the high reliability targets, we propose a consolidated approach that consists of an efficient and effective reliability baseline (BL) management system and a test scheme developed based on sequential probability ratio test (SPRT). To ensure a trustworthy setting for the SPRT test scheme, we apply the Bayesian approach to continuously update the BL database. An integrated flow chart is introduced to elucidate our proposed methodology. It is the first time SPRT is applied on reliability risk assessments with two unknown parameters. Several actual cases from semiconductor arena are reported to demonstrate the merits and powers of our proposed methodology. From these real cases, as a side benefit, we show the wide applicability of our method, which does not limit to reliability but on yield and functionality checks as well. To facilitate the use of our method by field practitioners, we do the best to explain derivations in a plain manner and provide analysis codes in R (in Supplementary Material) to make our approach as portable as possible. [ABSTRACT FROM AUTHOR]

The static random access memory (SRAM) is generally used in the technology qualification vehicle (TQV) in the semiconductor industries (e.g., assess process maturity and reliability risks). It is well known that the minimum operating voltage shift ($\Delta $ Vccmin) will be better if write-dominated is observed, and it will be worse for a read-dominated SRAM. However, in our experiments, a 40-nm technology node TQV SRAM based on the self-timing mechanism, which was read-dominated, showed a reverse outcome. After weeding out most known factors based on an inline, wafer acceptance test (WAT) and wafer-level reliability (WLR) data, we suspected such controversial phenomenon resulted from the competing aging effect of the memory arrays and the peripheral circuits. Through three HTOL experiments, we used the metrics $\Delta $ Vccminw and $\Delta $ Vccminr (i.e., the write and read Vccmin shift) to validate our speculation. The peripheral aging could not be neglected on assessing SRAM reliability, and we might have false conclusions without considering it. It is the first time such competing aging behavior, which easily leads to incorrect assessments, is reported. After successfully identifying the root cause leading to wrong conclusions, we provided a series of suggestions to minimize the impact of the peripheral aging effect and draw the more adequate conclusions. Meanwhile, combined with our experiences, we also provided design guidelines on the TQV SRAM to avoid such “defects” and potential risks. [ABSTRACT FROM AUTHOR]

In modern semiconductor manufacturing, one type of measured particle count data contains excess zeros, and the ratio of zeros in the measurements is usually larger than 50%. This type of particle count sample data cannot be well modeled by popular defect models such as Poisson, zero-inflated Poisson, generalized zero-inflated Poisson, and Neyman and Gamma-Poisson models. In this paper, a threshold-Poisson model was proposed to describe the particles with excess zero counts, and the method for parameter estimation was developed. Via comparison with those popular models by using 15 measured samples, it showed that the measurements are better modeled by the threshold-Poisson model. A control chart called threshold-c control chart was proposed and the control limits were derived. A reasonable minimum sample size for constructing control chart was also discussed based on simulations. [ABSTRACT FROM AUTHOR]

In this paper, we report electromigration (EM) reliability optimizations using highly efficient uniform design (UD). Considering the large error that results from using a single lifetime index, and the different EM failure modes, we introduce a new proportion index incorporating early failures to compensate for the shortage of using a single traditional intrinsic lifetime index in our Design of Experiments (DOE). Applying a supersaturated UD DOE, we greatly reduce (> 70\\% savings) the number of wafers used in experiments, comparing to the classical RSM design. This very economic experiment has successfully maximized EM lifetimes, which are more than 10 times longer, and without early failure, in a much shorter period of time. [ABSTRACT FROM PUBLISHER]

Reliability assessment is very important in semiconductor manufacturing, and we need to setup and maintain an efficient and effective reliability baseline (BL) management system to, for example, assess reliability risks, to dispose impacted lots, and to release equipment. To achieve these goals, we propose a corresponding flow and pinpoint the critical points to establish and maintain reliability BLs. To provide insights to readers by actual cases on reliability BL analyses and applications, we setup and analyze the BLs for the electric-field acceleration factor and activation energy of gate oxide, the gate voltage exponent of device Negative Bias Temperature Instabilities (NBTI), and the parameters of interconnect model for current density and activation energy. We also find the enriched reliability BL database does benefit line excursion disposition, process optimization, quicker judgment on the reliability impacts of nonconformance, feasibility studies of process changes, faster tool releases, risk assessments of common reliability tests, and earlier root cause identifications of abnormality by narrowing down failure mechanisms. [ABSTRACT FROM AUTHOR]

Yield and reliability susceptibility would become obvious with the increase in the complexity of manufacturing technology. Yield and reliability enhancement is always our pursuit. However, tradeoffs between yield and reliability, or between Fab and assembly house, are often observed during the technology development (TD) phase, which will lengthen the production ramp-up period, and further affect the product profit. To shorten the time-to-market of a new technology, some practical experiences on solving tradeoffs in semiconductor manufacturing are reported; a generic procedure to handle the tradeoff problem is proposed, and the effectiveness was also proved. Early detection capability, baseline knowledge management, fully understanding customers' requirements, and effectively consolidating all parties' efforts are considered to play key roles in the procedure. It is believed that such a procedure can be also applied to solve the tradeoff problem in other industries. [ABSTRACT FROM AUTHOR]

The limitation of the trend test in SPC is reviewed. The current Nelson's run test for the six or seven consecutive increasing or decreasing points cannot detect non-monotonic increasing or decreasing trend that is frequently encountered in industries. This paper proposes the reverse arrangement test (RAT) to replace the current SPC trend test rule in order to detect both non-monotonic and monotonic increasing or decreasing trends. The theory of RAT is reviewed and we point out the errors in the tables from a well-known and most frequently referenced paper on RAT. The corrected tables of accumulated probabilities for each total reverse arrangement for N = 3 to 12 are presented. The false alarm rate from RAT is verified with excellent accuracy by 108 data points simulating stable normal distributed process. Real examples from the semiconductor manufacturing illustrate that 7 non-monotonic increasing points can be detected by RAT with the same false alarm rate as for the 6 monotonic increasing trend, while sometimes none of the current WECO and Nelson's rules can detect such abnormal pattern. Applications of RAT in IC SPC and WLRC (Wafer Level Reliability Control) show RAT is much more powerful than conventional monotonic trend tests in detecting nonconformance. [ABSTRACT FROM AUTHOR]

A method is proposed in this paper to determine whether a product, a component, or a system in reliability life testing has a longer lifetime than the other. We propose two indices to compare reliability. The comparison is also distribution-free; i.e., it does not require the assumption on the lifetime distributions. A comparability index that is derived by integrating the weighted difference between the reliability functions of the two groups under comparison is named the "Better or Worse" (BOW) index. The second comparability index that is derived by calculating the overlapping area under the two distributions in comparison is named "Reliability Comparability" (RC) to quantify the degree of similarity between the two distributions. These two new indices are compared with the conventional methods currently used in the IC industries. Practical applications in lifetime-type reliability comparison are also illustrated in this paper. [ABSTRACT FROM AUTHOR]