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In this work, we develop an ultrathin epitaxial h-AlN as an interfacial layer (IL) between HfO2 and monolayer WS2 channel by atomic layer deposition (ALD). The growth of ultrathin dielectrics using ALD has been challenging due to the dangling-bond-free surface of 2D materials. By utilizing sub-1 nm h-AlN as an IL and depositing HfO2 high-k dielectric, we were able to form a uniform and atomically flat gate dielectric without voids. The resulting structure exhibits an equivalent oxide thickness as low as 1 nm and ultra-low leakage currents of ∼10−6 A/cm2. The fabricated top-gate WS2 transistors demonstrate on-off ratios of around 106 and subthreshold swing as low as 93 mV/dec. Furthermore, we have verified the feasibility of using h-AlN IL for a gate-all-around structure. Our work presents a CMOS-compatible low-temperature ALD process for integrating gate dielectrics, offering excellent thickness scalability and uniform coverage around monolayer WS2 nanosheets. The combination of high-quality two-dimensional dielectrics and semiconductors will contribute to the development of future high-performance and low-power electronic devices. [ABSTRACT FROM AUTHOR]

Transition metal dichalcogenides (TMDs) with only a few atoms thickness provide an excellent solution to scale down current semiconductor devices. Many studies have demonstrated that molybdenum disulfide (MoS2), a member of TMDs, is promising as a channel material to fabricate field-effect transistors (FETs). However, the carrier mobility in MoS2 FET is always far lower than the theoretical prediction. Although this poor performance can be attributed to the defects, it still lacks a quantitative analysis clarifying the correlation between carrier mobility and defect density. In this work, by using scanning tunneling microscopy, we directly counted the defects in MoS2 FETs with different carrier mobility. We found that vacancies and impurities equally contribute to carrier mobility and the total defect density induces a power-law decreasing tendency to the carrier mobility of MoS2 FET. Our current results directly prove that the reduction of point defects can exponentially improve the carrier mobility of FETs made by TMDs. [ABSTRACT FROM AUTHOR]

We report the demonstration of growing two-dimensional (2D) hexagonal-AlN (h-AlN) on transition metal dichalcogenide (TMD) monolayers (MoS2, WS2, and WSe2) via van der Waals epitaxy by atomic layer deposition (ALD). Having atomically thin thickness and high theoretical carrier mobility, TMDs are attractive semiconductors for future dense and high-performance 3D IC, and 2D hexagonal boron nitride (h-BN) as a gate dielectric is known to significantly improve TMD device performance. However, h-BN growth requires 1000 °C temperature that is not compatible with CMOS fabrication, and ALD deposition of any high-k 2D insulator on TMD continues to be an elusive goal. The epitaxial 2D layered h-AlN by low-temperature ALD is characterized by synchrotron-based grazing-incidence wide-angle x-ray scattering and high-resolution transmission electron microscopy. In addition, we demonstrate the feasibility of using layered h-AlN as an interfacial layer between WS2 and ALD HfO2. The significantly better uniformity and smoothness of HfO2 than that directly deposited on TMD are desirable characteristics for TMD transistor applications. [ABSTRACT FROM AUTHOR]

This paper presents an approach to enhance Hf0.5Zr0.5O2 (HZO) ferroelectric orthorhombic phase (O-phase) formation via in situ NH3 plasma treatment. High-resolution non-disruptive hard x-ray photoelectron spectroscopy confirmed that O-phase formation can be enhanced by suppressed interfacial diffusion between HZO and the top TiN electrode. Additional N-bonding facilitated by NH3 treatment was shown to suppress the interaction between TiN and HZO, thereby reducing the formation of oxygen vacancies within HZO. It was shown to improve the reliability and ferroelectric performance (examined by the leakage current and positive-up-negative-down measurements) of HZO devices. After cyclic operations, NH3-treated ferroelectric FETs (FeFETs) exhibited stable transfer characteristics and memory windows, whereas untreated devices presented unstable behaviors. Our results demonstrate the efficacy of the proposed in situ NH3-treatment scheme in enhancing the stability of HZO-based FeFETs. [ABSTRACT FROM AUTHOR]

The influence of Ti top electrode material on the resistive switching properties of ZrO2-based memory film using Pt as bottom electrode was investigated in the present study. When Ti is used as top electrode, the resistive switching behavior becomes dependent on bias polarity and no current compliance is needed during switching into high conducting state. This phenomenon is attributed to the fact that a series resistance between Ti and ZrO2 film, composed of a TiOx layer, a ZrOy layer, and even the contact resistance, imposed a current compliance on the memory device. Besides, our experimental results imply that switching the device into high conducting state is a field driven process while switching back into low conducting state is a current driven process. [ABSTRACT FROM AUTHOR]

The dependence of the metal gate work function on the underlying gate dielectric in advanced metal-oxide-semiconductor (MOS) gate stacks was explored. Metal work functions on high-κ dielectrics are observed to differ appreciably from their values on SiO[sub 2] or in vacuum. We applied the interface dipole theory to the interface between the gate and the gate dielectric of a MOS transistor and obtained excellent agreement with experimental data. Important parameters such as the slope parameters for gate dielectrics like SiO[sub 2], Al[sub 2]O[sub 3], Si[sub 3]N[sub 4], ZrO[sub 2], and HfO[sub 2] were extracted. In addition, we also explain the weaker dependence of n[sup +] and p[sup +] polysilicon gate work functions on the gate dielectric material. Challenges for gate work function engineering are highlighted. This work provides additional guidelines on the choice of gate materials for future MOS technology incorporating high-κ gate dielectrics. [ABSTRACT FROM AUTHOR]

Provides information on a study that focused on the use of p-channel silicon-gate metal-oxide semiconductor transistors for the examination of quantum yield of electron impact ionization in silicon. Way of injecting electrons into silicon from the polysilicon gate; Use of the carrier-separation properties of the induced junction; Examples of hot-carrier effects.

Presents information on a study which investigated the origin of the substrate current of a metal-oxide semiconductor field-effect transistor when the gate oxide undergoes Fowler-Nordheim stress. Experimental details; Results and discussion; Conclusions.

Presents information on hot-carrier-induced degradation of metal-oxide-semiconductor filed-effect transistors. Electron and hole trapping and interface-trap generation; Overview of electron-trapping efficiency of the group one device gate oxide; Generation of oxide traps by electron-hole recombination in the oxide.

The ultrafast metal-gate silicon quantum-dot (Si-QD) nonvolatile memory (NVM) with program/erase speed of 1 μs under low operating voltages of ± 7 V is achieved by thin tunneling oxide, in situ Si-QD-embedded dielectrics, and metal gate. Selective source/drain activation by green nanosecond laser spike annealing, due to metal-gate as light-blocking layer, responds to low thermal damage on gate structures and, therefore, suppresses re-crystallization/deformation/diffusion of embedded Si-QDs. Accordingly, it greatly sustains efficient charge trapping/de-trapping in numerous deep charge-trapping sites in discrete Si-QDs. Such a gate nanostructure also ensures excellent endurance and retention in the microsecond-operation Si-QD NVM. [ABSTRACT FROM AUTHOR]

The nearly free interfacial layer and the tetragonal phase ZrO2 with the high permittivity of 45 ± 3 on Ge (001) substrate lead to the equivalent oxide thickness as low as 0.39 nm and the low leakage current density of 2 × 10-3 A/cm-2. The ultrathin GeON layer formed by remote plasma treatment on GeO2/Ge can inhibit the interfacial layer regrowth by retarding the interdiffusion of Ge and O atoms. The initial ∼1 nm GeO2 layer is consumed during the remote plasma treatment, confirmed by x-ray photoelectron spectroscopy and further thinned down by post-deposition annealing to trigger the GeO desorption. [ABSTRACT FROM AUTHOR]

We examine room temperature band-to-band tunneling in 2D InAs/3D GaSb heterostructures. Specifically, multi-subband, gate-controlled negative differential resistance is observed in InAs/AlSb/GaSb junctions. Due to spatial confinement in the 10 nm-thick InAs layer, tunneling contributions from two distinct subbands are observed as sharp steps in the current-voltage characteristics. It is shown that the relative position of the steps can be controlled via external gate bias. Additionally, the extracted separation in the subband energy agrees well with the calculated values. This is the first demonstration of a gate controlled tunneling diode with multiple subband contributions. [ABSTRACT FROM AUTHOR]

An ultrathin body InAs tunneling field-effect transistor on Si substrate is demonstrated by using an epitaxial layer transfer technique. A postgrowth, zinc surface doping approach is used for the formation of a p+ source contact which minimizes lattice damage to the ultrathin body InAs compared to ion implantation. The transistor exhibits gated negative differential resistance behavior under forward bias, confirming the tunneling operation of the device. In this device architecture, the ON current is dominated by vertical band-to-band tunneling and is thereby less sensitive to the junction abruptness. The work presents a device and materials platform for exploring III-V tunnel transistors. [ABSTRACT FROM AUTHOR]

We explore the scaling limits of alternative gate dielectrics based on their direct tunneling characteristics and gate leakage requirements for future complementary metal-oxidesemiconductor technology generations. Important material parameters such as the tunneling effective mass are extracted for several promising high-κ gate dielectrics. We also introduce a figure of merit for comparing the relative advantages of gate dielectric candidates. Using an accurate direct tunneling gate current model and specifications from the International Technology Roadmap for Semiconductors, we provide guidelines for the selection of gate dielectrics to satisfy the off-state leakage current requirements of future high-performance and low power technologies. [ABSTRACT FROM AUTHOR]

A correction is presented to the article "Differential voltage amplification from ferroelectric negative capacitance" which was published in the perodical.

A stack structure for the gate electrode of metal-oxide-semiconductor (MOS) transistors is proposed, analyzed, and simulated. The stack consists of a very thin polycrystalline silicon (polysilicon) layer and metal. By changing the thickness of the polysilicon layer, one can change the effective work function of the gate. Thus, the stacked-gate structure allows for a method to continuously adjust MOS field-effect transistor threshold voltage through gate work-function engineering while retaining the proven SiO[sub 2]/polysilicon interface. © 2000 American Institute of Physics. [ABSTRACT FROM AUTHOR]

A simulator using a coupled Schro¨dinger equation, Poisson equation and Fermi–Dirac statistics to analyze inversion layer quantization is shown to match the measured capacitance versus voltage data of thin oxide gate metal-on-insulator capacitance closely. The effects of bias voltage, oxide thickness and doping concentration on the charge centroid are presented. A simple empirical model for the alternating current charge centroid of the inversion layer is proposed. This model predicts the in-version layer capacitance or charge centroid in terms of T[sub ox] (oxide thickness), V[sub t] (threshold voltage), and V[sub g] (gate voltage) explicitly. © 1998 American Institute of Physics. [ABSTRACT FROM AUTHOR]