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Abstract: A model is presented for external latchup. The effects of spacing, temperature, supply voltage and layout are captured in the model. The model shows a good fit to measurement results from two different technologies, RF-CMOS and SmartMOS. [Copyright &y& Elsevier]

We present an easy-to-use, simulator-independent compact model of a vertical npn transistor suitable for ESD circuit simulation. In addition to including high-current and breakdown effects, we also model accurately the small-signal off-state impedance of the device using s-parameter measurements, for inclusion in RF circuit simulations. Experimental results are provided for silicon and SiGe npn transistors. [Copyright &y& Elsevier]

This work presents a model for multi-finger MOSFETs operating under ESD conditions. It is a distributed model that can reproduce the effect of layout geometry on trigger voltage, on-state resistance, and non-uniform turn-on of device fingers. A three-terminal transmission line pulsing technique enables model parameter extraction. Analysis of measurement data and TCAD simulation reveals that self-heating is not uniform across the device, and this affects the relation between on-state resistance and the number of fingers. With self-heating incorporated, the model correctly reproduces the device I–V curve up to high current levels. [ABSTRACT FROM AUTHOR]

We demonstrate that narrow-band tuned circuits may be used for ESD protection of RF inputs, and a figure of merit for optimization of these circuits is presented. The performance of the ESD-protected RF circuit is dependent on the quality factor of the ESD device, and various protection devices are evaluated in this work. Record-breaking human body model (HBM) protection levels, exceeding 5 kV, have been achieved without significantly degrading the RF performance at 5 GHz. Broadband circuit protection is also addressed. [Copyright &y& Elsevier]