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New tools have been created to allow a superconducting design flow for schematic design, verification, and optimization. These tools integrate with the Cadence design environment. In single flux quantum superconducting electronics, individual component values, such as wire inductances, Josephson junction critical currents, and bias currents, must be optimized to allow for maximum deviance from the designer value, which is also known as the device margin. One tool is used to create a description of the proper circuit behavior. Included with this tool is the ability to automatically create the description from a Cadence netlist. The other tool is an automated device margin circuit schematic verification and optimization tool, which widens device margins while maintaining proper circuit behavior derived from the first tool. Additionally, this optimization tool can automatically correct the circuit schematic using the proper circuit behavior description. In this paper, the functionality of the language used to create the description of the proper circuit behavior is presented. Several circuits are then verified and optimized based on their correct behavior.

The present work proposes an Automated Place and Route Methodology for asynchronous SFQ circuits using PTL lines and a commercial EDA tool, Cadence's Innovus. At the cell level, dual rail SFQ Asynchronous standard cells were developed for the MIT Lincoln Labs SFQ5ee Process to be implemented in the Place and Route methodology. Python Scripts were written that could convert single rail netlists, obtained through the synthesis tool Design Vision from Synopsys, into dual rail asynchronous cells. Automatic Place and Route of Verilog based designs using these standard cells produced layouts that passed checks for Layout vs Schematic (LVS) and Design Rule Check (DRC). Then, the transmission line lengths are back annotated from the placed and routed design into analog simulation to simulate propagation delay.

This paper describes a system wide approach to synthesizing executable robot behaviors based on system capabilities. The approach builds upon prior work with the Flexible Behavior Engine (FlexBE), which uses hierarchical finite state machines (HFSM) to implement and execute robot behaviors. This paper extends prior work that integrated Linear Temporal Logic (LTL)-based automata synthesis into FlexBE by automatically generating the required configuration files based on distributed specifications of deployed system capabilities. Given this information, an end user can use existing tools to synthesize a reactive behavioral state machine (if realizable) given task specifications. The paper describes experiments executing synthesized state machines on a small wheeled mobile robot called TurtleBot running the ROS Kinetic system.

We present a rigorous electrical and optical analysis of a strained and graded base SiGe Heterojunction Bipolar Transistor (HBT) electrooptic (EO) modulator. In this paper, we propose a 2-D model for a graded base SiGe HBT structure that is capable of operating at a data bit rate of 80 Gbit/s or higher. In this structure, apart from a polysilicon/monosilicon emitter (Width = 0.12 μm) and a strained SiGe graded base (Depth = 40 nm) , a selectively implanted collector (SIC) (Depth = 0.6 μm) is introduced. Furthermore, the terminal characteristics of this new device modeled using MEDICI are closely compared with the SiGe HBT in the IBM production line, suggesting the possibility of fast deployment of the EO modulator using established commercial processing. At a subcollector depth of 0.4 μm and at a base-emitter swing of 0 to 1.1 V, this model predicts a rise time of 5.1 ps and a fall time of 3.6 ps. Optical simulations predict a π phase shift length (Lπ) of 240.8 μm with an extinction ratio of 7.5 dB at a wavelength of 1.55 μm. Additionally, the tradeoff between the switching speed, Lπ and propagation loss with a thinner subcollector is analyzed and reported.

We present a rigorous electrical and optical analysis of a highly scaled, graded-base, SiGe heterojunction bipolar transistor (HBT) electrooptic (EO) modulator. In this study, we propose a 2-D electrical model and a 3-D optical model for a graded-base SiGe HBT structure that is capable of operating at a data bit rate of 250 Gbit/s or higher. In this structure, apart from a polysilicon/low doped emitter ( width = 90 nm) and a strained SiGe graded base ( depth = 8.5 nm), a selectively implanted collector (SIC) (depth = 26 nm) is introduced. Furthermore, at a base-emitter swing of 0 to 1.0 V, this model predicts a rise time of 3.48 ps and a fall time of 0.55 ps. Optical simulations predict a π phase shift length (Lπ) of 204 μm, with an extinction ratio of 13.2 dB at a wavelength of 1.55 μm.

With the spotlight on smart grid development around the world, it is critical to recognize the key factors contributing to changing power-system characteristics. This is more apparent in distribution systems with the integration of renewable energy sources, energy storage, and microgrid development. Source and load control at the distribution level is a key requirement of the evolving system. These activities require distribution automation (DA) strategies that take advantage of available technologies, while promoting newer solutions. It is necessary to create a roadmap for holistic DA strategies in a smarter grid. Sustainable and resilient grid development is a paradigm shift requiring a new line of thinking in the engineering, operation, and maintenance of the power system. Distributed control architectures based on dynamic load and source data should be explored as a possible solution. This paper discusses a novel approach that integrates protection, control, and monitoring using high-performance computing at the primary distribution substation level. The business case for infrastructure investment in the distribution systems is also discussed. This paper concludes with a discussion on emerging and future technologies for DA to improve the resiliency of a sustainable grid.

Malfunctions at the site of neuromuscular junction (NMJ) of post-injuries or diseases are major barriers to recovery of function. The ability to efficiently derive motor neurons (MN) from embryonic stem cells has indicated promise toward the development of new therapies in increasing functional outcomes post injury. Recent advances in micro-technologies have provided advanced culture platforms allowing compartmentalization of sub-cellular components of neurons. In this study, we combined these advances in science and technology to develop a compartmentalized in vitro NMJ model. The developed NMJ system is between mouse embryonic stem cell (mESC)-derived MNs and c2c12 myotubes cultured in a compartmentalized polydimethylsiloxane (PDMS) microfluidic device. While some functional in vitro NMJ systems have been reported, this system would further contribute to research in NMJ-related diseases by providing a system to study the site of action of NMJ aimed at improving promoting better functional recovery.

NASA's latest space mission, the Lunar Reconnaissance Orbiter (LRO) has produced some of the largest publicly accessible Laser Altimeter data products available to date. The spatial density of these new data products are up to four times greater than laser altimeter data produced from previous space missions. However, partially due to the size, volume and density of the new altimeter data, current software tools provide only limited or no support for real-time cartographical projects, slope analysis, distance measurements or other analyses method critical to physiographic study of planetary systems. We discuss a novel software tool called mVTK, which facilitates the physiographic analysis of the Lunar surface using the newly acquired high resolution altimeter data products. Some of the features provided by mVTK include real-time cartographic projects, slope analysis, distance measurement and visual data discovery.

In this paper, a double-balanced common gate folded Gilbert mixer with low voltage supply and low power consumption is presented in 0.13um CMOS technology. This mixer features the common gate gm stage following by a folded LO switch stage. These two stages can be biased independently to achieve gain, linearity and noise figure specification in a wideband range. The simulation shows this mixer can achieve 6.3∼11.8dB conversion gain, 9.8∼15.2dB noise figure, 39dBm∼48dBm second-order intermodulation intercept point(OIP2), and around −7.5dBm Input Referred 1dB compression point between 2.5GHz∼7.5GHz with 7mW power consumption under 1.5V voltage supply.

This paper describes the design and simulation of a fully-differential, high gain, high speed CMOS Operational Transconductance Amplifier (OTA). The op-amp is designed for unity gain sampler stage of 14bit 12.5Ms/s pipeline analog-to digital converter. The design is implemented using a folding cascode topology with the addition of gain boosting amplifiers for increased gain. Common-mode feedback (CMFB) is used to stable the designed OTA against temperature and other process variations. This design has been implemented in 0.13μm IBM RF mixed signal CMOS Technology. The Spectre simulation shows the DC gain of 91.5 dB and a unity-gain frequency of 714.5MHz with phase margin of 62° (double 7.5-pF load) while consuming 9 mW power. For the normal corner, the settling time to 1/2 LSB of 14bit A/D converter accuracy is 40 ns.

This paper presents a quarter-phase 32GHz PLL using 0.13um SiGe BiCMOS technology for a high speed microprocessor. The PLL characterizes a 3-state phase frequency detector (PFD), a charge pump loop filter, a VCO, a frequency doubler and a feedback 1/32 frequency divider. The VCO used in this PLL is a four -- stage ring oscillator that has a wide tuning range with a feed-forward interpolation topology for coarse frequency tuning and varactor diodes load capacitance variation for fine frequency tuning. The PLL has a wide locking range from 24.4 GHz to 39 GHz with a phase noise of-102dBc/Hz at 1MHz offset.

This paper discusses the challenges that can arise from the lack of coordination among the distribution optimization applications. It analyzes the optimization objectives and the corresponding control strategies of the individual optimization applications to illustrate the conflicts in both the objectives and the control logics among the applications. Typical operation scenarios are explored to demonstrate the potentially detrimental conflicts. It is concluded from the results of the logical analysis and the scenario evaluation that a well-designed coordinating mechanism is necessary for the various optimization applications to work harmoniously for achieving the corresponding objectives. A priority based collaborative approach is proposed for coordinating the multiple optimization objectives and control strategies among the applications.

This paper describes the capacitorless 1-transistor (1T) DRAMs exploits the floating body (FB) effect of Fully depleted (FD) SOI devices, where the transistor body is used as a charge storage node. A novel three-tier, 3D, 1T embedded DRAM is presented that can be vertically integrated with the microprocessor achieving low cost, high density on-chip main memory. A 394Kbits test chip is designed and fabricated in a 0.15um fully depleted SOI CMOS process. The measured retention time under holding conditions is higher than 10ms. In the continuous read mode, every read should be followed by a refresh. The test chip is designed to work with an access time of 50ns and operates at 10MHz.

Electric Utilities have huge potential to utilize non-operational data already available in their grid management systems to improve their Operational Excellence. Further, as they deploy Smart Grid technologies the availability of non-operational data will increase tremendously. In this paper we introduce a system architecture for implementing an enterprise-level Decision Support System that utilizes non-operational data. We also propose a process for utilities, working cross-functionally, to design and acquire such a Decision Support System. We also list some of the benefits from the non-operational data management and the associated challenges that a utility may face in implementing the system.

Electrical utilities strive for optimal grid operations while increasing efficiency and maintaining high reliability. With the advent of the Smart Grid, these objectives remain important worldwide. Recently many separate optimization applications for distribution grid operation have been deployed, including FDIR, IVVC, OFR, and DR. These applications may have been developed with sophisticated optimization algorithms and provide value in their own right. However each application is designed to serve specific tasks and does not consider other optimization programs' existence and mutual impacts, resulting in significantly reduced benefits or even conflicting control actions. This paper intends to address some of the problems that can arise from the lack of coordination among the distribution optimization programs. Three typical operation scenarios will be explored to demonstrate the potentially detrimental consequences due to lack of coordination. The observations and results from the operation scenarios studied with the standard IEEE 123 Bus circuit indicate that a well-designed coordinating mechanism is necessary for the various optimization programs to work together properly while achieving their corresponding objectives. This paper proposes a collaborative approach to solve the problem by considering the multiple-time-interval look-ahead capabilities, incorporating all the available controls, and coordinating the multiple system objectives in each of the optimization applications.

A 128Kbit BiCMOS SRAM with a typical access time of 125ps was developed with 0.13um IBM Silicon Germanium BiCMOS technology[1]. The fast access time with moderate power dissipation has been achieved using following techniques: CML decoder, CML driver circuit, bipolar sense amplify. CMOS 6T memory cell is used to achieve the high packing density. The simulation demonstrates that this SRAM macro can achieve working frequency of 4GHZ. This Macro is especially useful for realizing ultrahigh speed, high density SRAMs which is used as cache in the super computing processor.

In this paper, we present our vision of a highly scalable arrayed biochemical sensor platform. This platform combines the advantages of refined and entrenched technologies like top-down integrated circuit fabrication and clinical assays with emerging technologies like three-dimensional stacking and label-free sensing. We demonstrate fabrication concepts and preliminary sensing results on ovarian cell lines prior to engaging in a discussion about relevant applications with regard to the exciting recent advances in genomics and oncology.

CMOS evolution by lateral lithographic shrinkage has encountered an impediment in that wires do not scale well. As a result, it would appear that the clock race is over and the future of computing lies in multicore or parallel processing. In a prior paper [1] we have explored the implications of Amdahl's figure of merit (FOM), which suggests that for algorithms to successfully demonstrate large throughput improvement by parallelization, the fraction of non-parallelizable code (also called serial code) must be less than about 4%. We observed that memory latency, synchronization, and inter-processor communication latency can masquerade as non-parallelizable code. While there are no doubt certain applications where this non-parallelizable code fraction of less than 4% exists, and others where the large memory needed to just hold the data can justify use of parallel processors in any case, the implications for the broad class of other code are at best in doubt. The Amdahl figure of merit suggests worse, that a favorable impact is unpromising. In this paper we continue the dialogue begun in the earlier paper by pushing on to examine a small demonstration processor that accomplishes high performance by pursuing the traditional higher clock rate through improvements in device and interconnection technology. Because the processor uses a BiCMOS process and requires a 3D memory for Memory Wall mitigation, it is important to address thermal issues. Preliminary analyses are perhaps unexpectedly somewhat favorable.

We analyzed an electro-optic modulator consisting of a heterojunction bipolar transistor (HBT) with graded SiGe composition in the base. Simulation shows single mode operation is attainable with an interaction length Lp of 40.8μm.

Three dimensional memory systems has been argued as a potential pathway in solving the ever growing difference between comparative speeds of CPU and memory systems. In this paper, we describe a three-tier, three-dimensional SRAM macro that has been designed and fabricated in a 0.18 um FD-SOI CMOS technology. 3D stacking is found to improve wire latency as compared to planar memory structure although the reduction is not enough to have a significant effect on access time of the memory. It is argued that the major performance benefit obtained by 3D integration is in term of very wide data bus that can be realized much more easily with 3D structures as compared to 2D memories.

Forty years ago Gene Amdahl published a figure of merit for parallel computation, which proved extremely controversial. The controversy still rages today, although those that have looked closely at this figure of merit conclude that it is correct, but perhaps misinterpreted. In this paper we will look at a small variation on that law that suggests computer designers should take a closer look at two emerging technologies, SiGe HBT BiCMOS and 3D chip stacking. We may be overlooking a way to continue the clock race, and in so doing accomplish better parallelism.

High speed and low power is the dream of circuit designers. In this paper a novel self-timed logic family is presented for high-speed self-timed pipelining applications. We developed a novel triple-rail MOS current mode logic (Tr-MCML) logic family and integrated it seamlessly with self-timed pipelines. This self-timed pipeline is designed to realize power-on-demand operations that achieve both high speed and low power, which is appropriate for the design of bus drivers, asynchronous I/Os, and infinite impulse response (IIR) filters. The ripple-carry adder is used as a testbench for verification. Simulation shows that the energy-delay product (EDP) of large digital systems can be reduced significantly.

An 8-phase 20 GHz PLL has been designed for a serial transceiver. The PLL has a wide locking range from 10 GHz to 20 GHz with a phase noise of -112 dBc/Hz at 10 kHz offset. The PLL uses a four-stage ring oscillator that has a wide tuning range with a feedforward interpolation topology for coarse frequency tuning and a varactor diode load capacitance variation for fine frequency tuning. The PLL is fabricated in 0.13-mum SiGe BiCMOS technology.

FPGAs have been a popular topic among electrical engineers for over a decade. Modern FPGAs are denser, faster and use less power compared to PLD and CPLD. This paper presents a high speed FPGA that operates in the gigahertz range. An improved reconfigurable circuit is described. State-of-the-art IBM SiGe BiCMOS technology is used to realize this high speed FPGA. A measurement on a fabricated chip proves that this FPGA is capable of operating at 11 GHz, a SONET OC-192 standard, for optical applications.

This paper presents the design of a voltage-controlled ring oscillator that has ultra wide tuning range of 12 to 23 GHz with hybrid control schemes. The voltage-controlled oscillator (VCO) uses a feedforward interpolation topology scheme and a varactor diode load capacitance variation scheme to control the oscillation. The measurement result of the VCO shows good linearity in frequency-voltage characteristics over the ultra wide tuning range.

This paper presents an approach to address the high static power consumption problem of the MOS current mode logic (MCML) by integrating MCML with self-timed pipelines. We develop a new MCML style, called triple-rail MOS current mode logic (Tr-MCML), that supports seamless integration with a self-timed pipeline. A look-ahead self-timed Tr-MCML pipeline architecture is designed to realize the data-driven power-on-demand operation to reduce the static power consumption while maintaining the high-speed property of MCML. This design approach is particularly desirable for latency-critical digital systems that solely rely on high-speed circuit design to improve performance. We use ripple carry adders as a test vehicle to demonstrate the significant improvement on the energy-delay product (EDP) compared with conventional MCML design.

The demand for high speed Field Programmable Gate Arrays (FPGAs) has been on a rise. These were never possible using CMOS as the basic device. People were able to achieve frequencies in the range of 70-250 MHz using CMOS. The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened the door for Gigahertz FPGAs. An FPGA with a speed of over 5 GHz was reported by B.S. Goda (2000) using SiGe 5HP technology. However in order to scale up FPGAs significantly, a serious power management scheme must be in place. Apart from this, architectural changes can be made to improve the speed and reduce the power. This paper elaborates on the architecture of the new SiGe FPGA and its advantages over the previous generation SiGe FPGAs. The entire Configuration Logic Block (CLB) has been implemented using seven Current Mode Logic (CML) trees. Apart from these, a novel power management scheme is implemented which allows the FPGA to operate at multiple modes: fast, non-critical, slow and off. The new FPGA can run in the fast mode when speed is critical or in the slow mode when power is the limiting issue. The CLB can run up to 5.96 GHz.

Advanced bipolar circuits for a RISC operating at a 250 MHz instruction rate are presented. Specifically a 30*8 bit register file macro with 500-ps access time is presented and a clock skew compensation scheme based on digital delay lines is introduced that can significantly reduce clock skew in a wafer scale multichip package. The predicted performance of advanced bipolar memory macros, I/O circuitry, and differential logic circuit are very encouraging. Measurement on a fabricated divide by two circuits shows good agreement with SPICE simulations. >

The exceptionally large amounts of bypass-capacitance requirements of wafer scale integration (WSI) and wafer scale hybrid packaging/multichip module (WSHP/MCM) based systems operating at state-of-the-art switching speeds are explored. The capacitance required may become considerably larger than can be obtained by simply making thin-oxide-metal-plate capacitors unless alternate design styles which exhibit less switching noise are adopted for the circuits employed. Some of the criteria for picking the value of the bypass capacitance are examined, together with techniques for introducing high-dielectric-constant materials into the processing of the semiconductor substrates. The possibility of depositing thin layers of amorphous BaTiO/sub 3/ at low temperature to form a reliable, pin-hole free dielectric for bypass capacitance by use of ionized cluster beam techniques is explored. Deposition of the amorphous material on both metal and semiconductor substrates is possible. >

Describes the current status of the ongoing development of a virtual simulation system for use in training anesthesiology residents in the technique of delivering an epidural block. The system utilizes real-time graphics, a voice interface, and force-feedback applied to a Crawford needle to simulate a realistic epidural experience. The user sits in front of a SGI workstation and invokes the program through a voice interface. A computer generated image of the back, taken from MRI data, appears on the screen along with an image of the needle. The user places his hands on the physical needle, which is held by a 1 DOF Impulse Engine (developed by Immersion Corporation). As the physical needle is pushed in, the graphical representation of the needle moves in synchrony, and realistic forces are applied by the Impulse Engine to give the user the feel of actually inserting the needle into a patients back. The novice user can get feedback as to the position of the needle by watching an interactive view of the needle in a image showing the axial view of the MRI data of the patient's back. A more advanced user can request instantaneous axial, sagittal, or coronal MRI views of the position of the needle in the MRI data set using vocal commands. The haptic forces are currently being modeled from a combination of the MRI intensity values and expert opinion. Work in progress involves modeling these forces as springs, using the MRI intensity levels and a system of equations to quantitatively define the force for a given needle depth. A series of experiments are being planned to identify the true physiological forces involved in needle insertion. Results from these experiments will be used to develop the system of equations which will drive the force feedback on the simulator.

The difficulty of cost-effectively identifying Known Good Die (KGD) is increased in circuits requiring multiple die packaged in Multi-Chip Modules (MCMs). Such circuits typically have high frequency I/O signals which are difficult to measure using inexpensive test equipment. The cost of full Built-In Self-Test (BIST) can be prohibitive, particularly when device integration levels are low. This paper presents a scheme for testing die for functionality and speed at minimal cost. The scheme also allows testing of MCM traces and testing of on-chip circuits both before and after packaging. The scheme was developed for use in Rensselaer Polytechnic Institute's F-RISC/G 1 ns processor project.

The low dielectric constant of parylene-n (PA-n) and high conductivity of Cu can provide a low RC time constant interconnection scheme. Vapor deposited PA-n and Partially Ionized Beam (PIB) deposited Cu have been employed for this study. Both Cu and Cr formed plasmas during the PIB deposition. The diffusion of Cu in low concentrations into PA-n at temperatures higher than 350 degrees C has been previously observed. Another problem with high temperature anneals (>300 degrees C) in the Cu/PA-n system is the gradual loss of adhesion. Here, chromium has been demonstrated as a diffusion barrier and adhesion promoter. Previous studies of different systems have used Cr with mixed success as a diffusion barrier. Thus, it is essential to determine its efficiency in the specific Cu/Cr/PA-n system. In this system, thin Cr layers, 1000-100 AA, served as a good barrier and adhesion promoter up to the tested temperature of 350 degrees C. These thin layers are essential to minimize the resistive contribution due to skin effect at high frequencies. >

Copper is investigated as an interconnect metal and parylene as the interlayer dielectric. It has been found that copper adheres to the parylene well. The effect of a soldering step has been simulated by annealing. Using Rutherford backscattering (RBS) and secondary ion mass spectroscopy (SIMS) it has been found that copper does indeed diffuse into the parylene at elevated temperatures. However, this diffusion is small and does not affect the dielectric leakage properties much. >

A theoretical model for a metal-over-silicon microstrip interconnection is presented using a quasi-TEM approximation. We consider in this paper several physical effects, including: SiO/sub 2/ insulator layer, slow-wave substrate coupling, conductor resistance, skin-effect degradation, distributed RC propagation, and signal dispersion. We have examined, in particular, the influence of an underlying SiO/sub 2/ insulator layer, as previous studies have not included such a layer. Pulse propagation has been studied for durations down to 50 ps, suitable for 10 GHz clocks. We have found that pulse attenuation is reduced dramatically as the thickness of the SiO/sub 2/ layer is increased.

The authors have previously reported two components of a methodology for acquiring and quantitatively analyzing three dimensional (3D) echocardiograms of the human heart. This report describes tools that they have developed to facilitate analysis of the left ventricle (LV), and to expand the applications of the technology to analysis of the right ventricle and mitral apparatus. Specifically the authors describe methods for 3D imaging, image analysis, surface reconstruction, and quantitative analysis of cardiac parameters. They also describe methods for facilitating these analyses and for adapting them to different clinical and research applications, such as measuring the relationship between different structures of the heart in 3D. The authors present clinical data to illustrate the applications of these technical innovations.

IC interconnect characterization is growing in importance as devices become faster and smaller. Accurate numerical extraction of 3D interconnect capacitance is essential for achieving design targets in the multi-GHz digital regime. An AlGaAs-GaAs heterojunction-bipolar-transistor test chip was fabricated. The chip used 3-level metal with anisotropic polyimide interlevel dielectrics. Full differential current-mode logic circuit technology was employed. The chip contained a variety of interconnect capacitor structures (parallel plate, finger, crossover) and interconnect-limited ring-oscillator circuits. Capacitance and oscillator frequency measurements were performed to compare with CAD-tool predictions. Good agreement with measurements was achieved with an independently obtained 25% uniaxial polyimide dielectric anisotropy. Measured and predicted results for the capacitor test structures generally agreed to within 2%. Predicted ring-oscillator periods were within 4% of measurement.

Wafer Scale Hybrid Packages (WSHPs) or MultiChip Modules (MCMs) have provided a breakthrough in system packaging for high clock rate systems. Based on this technology a 2 GHz Fast RISC demonstration integer-only computational engine has been designed, and is submitted for fabrication. This design involved use of Heterojunction Bipolar Transistors (HBTs) in the GaAs/AlGaAs materials system. This paper reviews some of the schemes used in that design and shows how there are actually several paths using advanced GaAs/AlGaAs and SiGe HBT technology to create similar systems that can actually run 8 times faster. Some of the challenges facing the architect and chip designer are discussed.

Three dimensional (3D) reconstruction of multiple two dimensional images, spatially and time registered, is increasingly being employed. These can be visualized on computer screens in full stereographic perspective using software and stereographic glasses now available. The authors have applied stereographic viewing to over 40 reconstructions of outlines of the endo and epicardiums of ultrasound imaged hearts. They found that standard viewing often mislead them into believing that misregistration existed. However, when viewed in stereographic mode, they found that these suspected lines did intersect, but at other places in the 3D reconstruction. The stereographic method has proven very useful in this and in distinguishing the separability of various 3D structural features in grid, surface, and voxel echocardiogram reconstructions.

A digital high-speed voltage-controlled oscillator (VCO) has been developed which uses frequency-multiplication and division to attain a wide frequency range of 0.5-13.66 GHz. The circuit is implemented in differential current-mode logic using GaAs-AlGaAs heterojunction bipolar transistors (HBTs). This paper discusses top-level system design as well as the design of several key components.

Soft-programmable logic is increasingly used to emulate and verify CMOS designs before fabrication. The F-RISC emulator uses this technology to emulate and verify a multichip GaAs RISC processor. An essential part of the F-RISC emulator is the mapping of the differential CML GaAs libraries to the Xilinx FPGA libraries. The emulator helped to detect several design errors.

Reconstruction of heart chambers from tomographic images has traditionally been done from either parallel or fixed position rotational scans. We introduce a method of reconstruction from random slice orientations, using labeled landmark features to guide fitting to a labeled predesigned surface-generating mesh. This method is applied specifically to ultrasound sector scanning, but is applicable to any tomographic imaging technique. Given surface descriptions of the left ventricle (LV) endocardium and epicardium at end diastole (ED) and end systole (ES) (or other time points), LV wall motion can be computed by matching the ED and ES surface features. Wall thickness at ED and ES is computed using the CenterSurface method. A new method of computing the CenterSurface is described.

A high speed voltage-controlled oscillator (VCO) bas been developed using 50 GHz GaAs-AlGaAs HBTs which can generate differential signals in the range of 0.25-20 GHz. The design process was focused on producing a layout with highly-matched parasitic capacitance by exploiting the high degree of symmetry present in differential circuits. The system design and cell layout techniques are described in detail using examples from the VCO. The operation of the VCO is also discussed along with design tradeoffs.

Devices are becoming available whose inherent switching speeds are approaching only a few picoseconds. CMOS FET devices with 0.12 micron channel length have exhibited f/sub T/ values of 89 GHz. SiGe HBTs have been demonstrated with an f/sub T/ of 117 GHz. InP/InGaAs/AlGaAs HBT's have exhibited an f/sub T/ of 200 GHz, with minimum feature sizes that are above one micron. InGaAs/AlGaAs MESFET's with 0.05 micron channel lengths have exhibited f/sub T/ values of 350 GHz. Clearly even faster devices are possible, and some have even begun to appear in viable fabrication lines where prospects for interesting levels of integration are being realized. For such technologies subnanosecond machine cycles seem possible. However, for conventional 2D chip or wafer fabrication some of the distances between key components on these substrates can be too long for subnanosecond operation. This may be true even for ideal transmission line interconnections that exhibit "speed of light" propagation speeds and extremely wide bandwidths. At this point the last resort is to shorten these interconnections by rearranging the components in 3D structures, implying either die or wafer stacking. This paper explores some of the requirements for subnanosecond machine design, and practical schemes to accomplish this with discussion on how to distribute the power supply current and dissipate the heat generated. These schemes use the full array of WSI, WSHP and MCM technologies plus some new techniques for 3D vertical stacking.

Three-dimensional (3D) ICs offer increased performance of digital lCs, heterogeneous integration for numerous applications and lower manufacturing cost for electronic and optoelectronic systems. After a discussion of alternative 3D integration technologies, our approach of using dielectric glue layers for attachment of fully processed 200mm diameter wafers (followed by top wafer thinning and inter-wafer interconnection with copper damascene patterning) is described. The wafer bonding process is highlighted, and requirements for polymeric adhesives for this application are described. Results with Flare/sup TM/, a non-fluorinated poly aryl ether, are presented in detail and serve as a baseline for alternative adhesives.

Analysis of LV shape can aid in characterizing LV remodeling following myocardial infarction. The authors developed and validated a method of detecting abnormalities in left ventricular (LV) shape using three-dimensional (3D) echocardiography. LV endocardial surfaces were reconstructed by piecewise smooth subdivision method from traced echocardiographic scans in end diastole. Artificially distorted surfaces were created to test the method which aligns two LV surface reconstructions along regions of similar shape. Five different functions with decreasing degree of penalty for large variation in shape were tested. Difference in shape was computed as distance between the LV surface being compared. Function performance in detecting a shape difference was assessed by comparison of distances from alignment by different functions. The mean variability of normal LV shape was defined from the LVs of 14 normal subjects. Variation in size was normalized by the right ventricular apex to aortic valve distance. Reconstructions of 9 patients studied