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This work aims at optimizing the hardware implementation of the SubBytes and inverse SubBytes operations in the advanced encryption standard (AES). To this, the composite field arithmetic (CFA) is employed to optimize all building blocks in S-box (and inverse S-box) of SubBytes (and inverse SubBytes) transformation. A joint design of S-box and inverse S-box is also proposed to further enhance the area efficiency. Specifically, the area of multiplier in the Galois composite field, GF $((2^{2})^{2})$ , is reduced. The squaring and multiplication with constant $\lambda $ in GF $((2^{2})^{2})$ are combined and optimized as well. Moreover, the multiplicative inversion in GF $((2^{2})^{2})$ is manually optimized. Furthermore, the S-box and inverse S-box are combined and optimized using the pre_processing and post_processing modules. To increase the throughput, a balanced and pipelined architecture is derived. Using the proposed architecture, a throughput of 5.79 Gbps for the S-box can be achieved on Virtex-6 XC6VLX240T and 10% better than the conventional work. According to the ASIC implementation result, the proposed design can still achieve the highest area efficiency and approximately 30% better than conventional works using TSMC 90nm process.

Ultrareliable low-latency communication (URLLC), a major 5G new-radio (NR) use case, is the key enabler for applications with strict reliability and latency requirements. These applications necessitate the use of short-length and high-rate channel codes. Guessing random additive noise decoding (GRAND) is a recently proposed maximum likelihood (ML) decoding technique for these short-length and high-rate codes. Rather than decoding the received vector, GRAND tries to infer the noise that corrupted the transmitted codeword during transmission through the communication channel. As a result, GRAND can decode any code, structured or unstructured. GRAND has hard-input as well as soft-input variants. Among these variants, ordered reliability bits GRAND (ORBGRAND) is a soft-input variant that outperforms hard-input GRAND and is suitable for parallel hardware implementation. This work reports the first hardware architecture for ORBGRAND, which achieves an average throughput of up to 42.5 Gb/s for a code length of 128 at a target frame error rate (FER) of 10−7. Furthermore, the proposed hardware can be used to decode any code as long as the length and rate constraints are met. In comparison to the GRAND with ABandonment (GRANDAB), a hard-input variant of GRAND, the proposed architecture enhances decoding performance by at least 2 dB. When compared to the state-of-the-art fast dynamic successive cancellation flip decoder (Fast-DSCF) using a 5G polar code (PC) (128, 105), the proposed ORBGRAND VLSI implementation has $49\times $ higher average throughput, $32\times $ times more energy efficiency, and $5\times $ more area efficiency while maintaining similar decoding performance. [ABSTRACT FROM AUTHOR]

This paper presents a generalized novel design of a family of multiplier free orthogonal wavelet filter banks (FBs) with low complexity. In the proposed method, maximum number of zeros at $z=-1$ is ensured for a desired length of analysis and synthesis filters. A new class of technique is proposed to obtain dyadic filter coefficients based on double shifting orthogonality property with allowable deviation from original filter coefficients. This is achieved by slightly altering perfect reconstruction (PR) condition to obtain dyadic filter coefficient. A general closed form expression is formulated using double shifting orthogonality property to reduce the error between original filter coefficients and proposed dyadic filter coefficients. The designed wavelet FB improved time-frequency product, Sobolev regularity and frequency selectivity (low energy in error) over well known existing wavelet FBs. In addition, a fixed point VLSI architecture is proposed for the designed family of orthogonal wavelet FBs. The suggested architecture is designed and implemented on Kintex7 FPGA board. The proposed family of orthogonal wavelet FBs is multiplier less with significantly reduced adders, shifters and dynamic power dissipation. The performance of the proposed wavelet FB is validated on two different applications namely image compression and medical image retrieval. The proposed FBs are tested on well known datasets such as CLASSIC, EPFL, RAISE, and FiveK for image compression and on three different medical image databases such as NEMA, OASIS, and EXACT09 for image retrieval. [ABSTRACT FROM AUTHOR]

Stochastic computing (SC) has been applied on the implementations of complex arithmetic functions. Complicated polynomial-based approximations lead to large hardware complexity of previous SC circuits for arithmetic functions. In this paper, a novel piecewise approximation method based on Taylor series expansion is proposed for complex arithmetic functions. Efficient implementations based on unipolar stochastic logic are presented for the monotonic functions. Furthermore, detailed optimization schemes are provided for the non-monotonic functions. Using NAND and AND gates as main computing elements, the optimized hardware architectures have extremely low complexity. The experimental results show that a broad range of arithmetic functions can be implemented with the proposed SC circuits, and the mean absolute errors can achieve the order of 1 × 10-3. Compared with the state-of-the-art works, the approximation precision for some typical functions can be increased by more than 8× with our method. In addition, the proposed circuits outperform the previous methods in hardware complexity and critical path significantly.

This brief presents a novel VLSI architecture for computing discrete wavelet packet transform (DWPT) for the continuous flow of data. Each stage of the proposed multi-stage architecture consists of the bit-reordering circuit and serial wavelet filter. The conventional wavelet filter has been modified for single path serial data. The intermediate coefficients are reordered with the help of a bit reordering circuit in order to maintain a continuous flow of data from input to output end with minimum memory and minimum latency. In comparison to the recently published architectures, the proposed one not only reduces the memory requirement by more than 50% but also achieves a 100% hardware utilization ratio. Furthermore, the area and power requirements are reduced by more than 60% and 50%, respectively. [ABSTRACT FROM AUTHOR]

A novel sparsity adaptive compressed sensing (CS) scheme based on Reed-Solomon (RS) codes is proposed to reduce the amount of sampled data, which can adjust the sampling rate adaptively to achieve data sampling and reconstruct the original data accurately by any decoding algorithm on the finite field. Moreover, the proposed sparsity adaptive reconstruction architecture can greatly improve the data reconstruction efficiency of the proposed CS scheme. The simulation results show that the sparsity adaptive scheme can reduce 83.6% of the sampled data. The results illustrate that the proposed architecture needs about 95k gates and operates at 500 MHz to achieve the throughout of 4.0 Gb/s, which can greatly improve the efficiency of the communication system. Meanwhile, it is at least 21.4% more area-efficient compared with previously reported fixed sampling rate architecture based on RS codes. [ABSTRACT FROM AUTHOR]

This paper presents a digital signal processing (DSP) architecture for real-time and distortion-free recovery of electrically-evoked compound action potentials (ECAPs) from stimulus artifacts and periodic noises in bidirectional neural response telemetry (NRT) system. In this DSP architecture, a low computation-cost bidirectional-filtered coherent averaging (BFCA) method is proposed for programmable linear-phase filtering of ECAPs, which can be easily combined with the alternating-polarity (AP) stimulation method to reject stimulus artifacts overlapped with ECAP responses. Design techniques including the configurable folded infinite-impulse response (IIR) filter and division-free averaging are also presented for efficient hardware implementation. Implemented in 180-nm CMOS process, the proposed DSP architecture consumes 10.03-mm2 area and 2.35-mW post-layout simulated power. The efficacy of the DSP architecture in recovering ECAPs from recorded neural data contaminated by overlapped stimulus artifacts and periodic noises is validated in in-vivo electrical nerve stimulations. Experiment results show that compared with the previous coherent averaging technique, the proposed DSP architecture improves the signal-to-noise ratio (SNR) of ECAP responses by 11 dB and achieves a 3.1% waveform distortion that is 17.1× lower. [ABSTRACT FROM AUTHOR]

With the increasing demand in electronic gadgets expecting better video quality for multimedia applications, various coding standards evolved for the past two decades and optimization on the architectures of the various modules used in the video codec is most popular. In this paper, an efficient architecture for deblocking filter used to smoothen the pixels of the decompressed video data is proposed, which utilizes both pipelining and parallelism. The filtering process follows a sequential order as filtering vertical edges of luma block and chroma block followed by the horizontal edges of the luma block and chroma block. Three pipeline stages are used and four edges, either vertical or horizontal are filtered in parallel. Internal buffers which hold the sub-blocks read from the external frame buffers are accessed in a ping pong fashion to filter the adjacent sub-edges and thus reducing the external memory access cycles. Due to parallelism with novel edge filtering order, self-transposing mechanism, and ping pong buffer access, the throughput is increased. The proposed quad parallel edge deblocking filter architecture is implemented using Synopsys 90 nm library. It achieves a target area of 19.8 K and can process a Macro Block in 58 clock cycles.

Transform model estimation (TME) is a geometric operation, widely utilized in real-time imaging systems. Considering the massive computational load of matrix algebra-based TME realizations, most of the imaging systems resort to highly paralleled software-platform-based TME execution, which is power-intensive and expensive. Due to low-speed and power intensiveness, existing hardware for TME is not capable enough to meet the requirements of real-time systems. In this article, a hardware-realizable method of three-degree-of-freedom TME is formulated encompassing both the conventional CORDIC and the proposed modified CORDIC. The novelties of the proposed TME method and the corresponding architecture are that its latency sublinearly varies with the precision and the total computation time (CT) is almost independent of the input image sizes. The performance of prototype 16-bit fixed-point TME architecture (realized using VHDL in Xilinx Vivado 18.2) is compared with the software-counterpart. The proposed TME hardware is utilized along with other standard hardware modules to realize image registration (IR) operation. The proposed IR architecture achieves, on average, 60% reduction in total CT, $1.61 \times $ increase in maximum operating frequency with a comparable accuracy, only at the cost of 23% increase in power consumption with respect to other existing IR hardware. [ABSTRACT FROM AUTHOR]

This article proposes an encoding method based on a two-step encoding algorithm for the 12 quasi-cyclic (QC)-low-density parity-check (LDPC) (QC-LDPC) codes specified in the IEEE 802.11n/ac/ax standards. The proposed approach jointly considers all codes of the particular set, instead of targeting each code separately. The proposed algorithm performs multiplication by inverse matrices. The complexity of the multiplications is significantly reduced by the introduced encoding method. It allows the implementation of full-parallel architectures that execute the encoding process within a single clock cycle, or more for pipelined implementations, for any of the supported codes. A corresponding VLSI encoding architecture based on XOR-gate trees is also proposed. The proposed solution exploits the structure and features of the involved matrices to extract common subexpressions (CSs) using common sub-expression sharing techniques (CSST). Such expressions result due to common features of the original matrices and the corresponding inverses, identified in this article. Innovative subexpression extraction procedures that target the specific codes as a set are introduced here. Furthermore, illustrative single-clock hardware encoders derived by the proposed technique are integrated into 90- and 45-nm technologies at 1 GHz occupying 125 and 107 KGates, respectively, achieving throughput rates up to 1.62 Tbps. [ABSTRACT FROM AUTHOR]

In this brief, a novel approximation method and its optimized hardware implementation are proposed for the sigmoid function used in Deep Neural Networks (DNNs). Based on piecewise approximation and truncated Taylor series expansion, the proposed method achieves very good approximation with low complexity while exploiting data representation with powers of two. In addition, by analyzing gradients of the sigmoid function, a small trick is introduced to improve the approximation precision. Furthermore, to reduce the hardware complexity and shorten the critical path, sampled values of the function are generated with simple logical-mapping. It is shown that the proposed approximation schemes can be implemented with purely combinational logic and the sigmoid function can be computed in one clock cycle. The experimental results demonstrate that the mean absolute errors are at the order of $1\times 10^{-3}$. Compared with prior arts, the new design can obtain significant improvement in critical path with comparable performance. [ABSTRACT FROM AUTHOR]

In this brief, we propose a low complexity VLSI architecture design Methodology for Wigner Ville Distribution (WVD) computation. The proposed methodology performs both auto and cross WVD computations using only the half number of Fast Fourier transform (FFT) computations as opposed to the state of the art methodologies. The FPGA implementation for proposed methodology was performed for 16 bit fixed point and 32 bit single precision floating point numbers on the Xilinx Virtex-7 FPGA (XC7vx485tffg). The proposed methodology saves 49% energy consumption when compared with the state of the art methodology. However it can be noted that the proposed methodology is independent of the VLSI implementation platform and technology node. [ABSTRACT FROM AUTHOR]

To enable the continued scaling of distributed storage, failure recovery schemes that have low latency and low redundancy are indispensable. Minimum storage regenerating (MSR) codes have been developed to achieve this goal. Compared to other MSR codes, the recent coupled-layered (Clay) codes have many advantages such as low sub-packetization level, small finite field for construction, and uniform repair bandwidth over data and parities. This brief proposes efficient VLSI architectures for Clay encoder and decoder. Through exploiting subfield elements of finite fields, the logic complexity is substantially lowered. Additionally, the buffer size is reduced by optimizing the coupling scheme. For an example Clay code with (n,k)=(6,4), the proposed designs achieve 12% and 24% logic complexity reduction on the encoder and decoder, respectively, under the same timing constraint. [ABSTRACT FROM AUTHOR]

This article presents a piecewise linear approximation computation (PLAC) method for all nonlinear unary functions, which is an enhanced universal and error-flattened piecewise linear (PWL) approximation approach. Compared with the previous methods, PLAC features two main parts, an optimized segmenter to seek the minimum number of segments under the predefined software maximum absolute error (MAE), raising the segmentation performance to the highest theoretical level for logarithm, and a novel quantizer to completely simulate the hardware behavior and determine the required bit width and ${\text {MAE}}_{c}$ (MAE in circuits) for hardware implementation. In addition, the hardware architecture is also improved by simplifying the indexing logic, leading to nonredundant hardware overhead. The ASIC implementation results reveal that the proposed PLAC can improve all metrics without any compromise. Compared with the state-of-the-art methods, when computing logarithmic function, PLAC reduces 2.80% area, 3.77% power consumption, and 1.83% ${\text {MAE}}_{c}$ with the same delay; when approximating hyperbolic tangent function, PLAC reduces 6.25% area, 4.31% power consumption, and 18.86% ${\text {MAE}}_{c}$ with the same delay; when evaluating sigmoid function, PLAC reduces 16.50% area, 4.78% power consumption with the same delay, and ${\text {MAE}}_{c}$ ; and when calculating softsign function, PLAC reduces 17.28% area, 11.34% power consumption, 12.50% delay, and 33.28% ${\text {MAE}}_{c}$. [ABSTRACT FROM AUTHOR]

The metric-first-based multiple-input–multiple-output (MIMO) detection algorithm can achieve optimal performance with large stack size, which leads to huge memory consumption and extremely high-sorting complexity. This article presents the algorithm and architecture of a soft-input–soft-output metric-first MIMO detection. The proposed algorithm divides the global stack into multiple local stacks for each nonleaf of the tree. Furthermore, each level of the search tree is performed in parallel to improve the throughput and hardware efficiency. In the proposed algorithm, the hybrid enumeration strategy significantly reduces the computational complexity by avoiding the full enumeration and sorting. The simulation results show the novel algorithm can achieve good performance with lower complexity than other metric-first methods. The proposed detector has been designed for a $4\times 4\,\,64$ -QAM MIMO system and implemented in SMIC 65-nm CMOS technology. The detector can operate at 333-MHz clock frequency and achieve a maximum throughput of 799.2 Mb/s at a 17.3-dB signal-to-noise ratio with area equivalent 242 kg and power consumption of 102.3 mW, and the hardware efficiency is 3.3 Mb/s/kg. Compared with other detectors based on the metric-first algorithm, this article has an obvious advantage in terms of throughput and hardware efficiency. [ABSTRACT FROM AUTHOR]

A novel high-efficient reconstruction architecture of compressed sensing and an area-efficient integrated source-channel decoder based on Reed-Solomon (RS) code are proposed in this letter. The proposed reconstruction architecture only includes a parameter calculation (PC) block and a target locator and evaluator solution (TLES) block, resulting in 30 times higher throughput rate achieved and 85% area saved compared with previously reported reconstruction architecture based on orthogonal marching pursuit (OMP) algorithm. Moreover, the proposed integrated source-channel decoder can reduce 15.3% and 28.5% area respectively for the sampling rate of 25% and 12.5%. [ABSTRACT FROM AUTHOR]

This paper proposes an area-efficient fixed-point architecture for the computation of the discrete cosine transform (DCT) of multiple sizes in high efficiency video coding (HEVC). This result is obtained by comparing different DCT factorizations in order to find the most suitable one for implementation in the HEVC encoder. The recursive structure of fast algorithms, which decompose the $N$ -point DCT by means of two $N/2$ -point DCTs, is exploited to execute computations of small-size DCTs in parallel, thus maximizing the hardware re-usability while maintaining a constant throughput. The simulation results prove that the proposed solution features reduced rate-distortion loss es, with relevant complexity saving compared with the state-of-the-art implementations. Finally, the proposed architecture is exploited to design two families of architectures for the 2D-DCT, namely, folded and full-parallel. [ABSTRACT FROM AUTHOR]

Large integer multiplication has been widely used in fully homomorphic encryption (FHE). Implementing feasible large integer multiplication hardware is thus critical for accelerating the FHE evaluation process. In this paper, a novel and efficient operand reduction scheme is proposed to reduce the area requirement of radix-r butterfly units. We also extend the single-port, merged-bank memory structure to the design of number theoretic transform (NTT) and inverse NTT (INTT) for further area minimization. In addition, an efficient memory addressing scheme is developed to support both NTT/INTT and resolving carries computations. Experimental results reveal that significant area reductions can be achieved for the targeted 786432- and 1179648-bit NTT-based multipliers designed using the proposed schemes in comparison with the related works. Moreover, the two multiplications can be accomplished in 0.196 and 2.21 ms, respectively, based on 90-nm CMOS technology. The low-complexity feature of the proposed large integer multiplier designs is thus obtained without sacrificing the time performance. [ABSTRACT FROM AUTHOR]

This brief proposes a new selective-sampling technique that enables spectrum sensing of orthogonal-frequency division multiplexing primary users with 64, 128, 256, 512, and 1024 subcarriers for contemporary cognitive-radio wireless networks. Reconfigurable and memory-efficient very-large scale-integration architecture of the time-domain cyclostationary detector, based on this new technique, has been designed for spectrum sensing. In addition, we present robust coordinate rotation digital-computer architecture for our detector that reduces the computational error to achieve adequate performance. Our detector is post-layout simulated in 90-nm CMOS process and field-programmable gate array implemented that processes the real-world signals captured using universal-software radio peripheral transceivers. In comparison with the state-of-the-art technique, this design alleviated memory requirement by 99% and other hardware resources by 33%. [ABSTRACT FROM AUTHOR]

Binary weight convolutional neural networks (BCNNs) can achieve near state-of-the-art classification accuracy and have far less computation complexity compared with traditional CNNs using high-precision weights. Due to their binary weights, BCNNs are well suited for vision-based Internet-of-Things systems being sensitive to power consumption. BCNNs make it possible to achieve very high throughput with moderate power dissipation. In this paper, an energy-efficient architecture for BCNNs is proposed. It fully exploits the binary weights and other hardware-friendly characteristics of BCNNs. A judicious processing schedule is proposed so that off-chip I/O access is minimized and activations are maximally reused. To significantly reduce the critical path delay, we introduce optimized compressor trees and approximate binary multipliers with two novel compensation schemes. The latter is able to save significant hardware resource, and almost no computation accuracy is compromised. Taking advantage of error resiliency of BCNNs, an innovative approximate adder is developed, which significantly reduces the silicon area and data path delay. Thorough error analysis and extensive experimental results on several data sets show that the approximate adders in the data path cause negligible accuracy loss. Moreover, algorithmic transformations for certain layers of BCNNs and a memory-efficient quantization scheme are incorporated to further reduce the energy cost and onchip storage requirement. Finally, the proposed BCNN hardware architecture is implemented with the SMIC 130-nm technology. The postlayout results demonstrate that our design can achieve an energy efficiency over 2.0TOp/s/W when scaled to 65 nm, which is more than two times better than the prior art. [ABSTRACT FROM AUTHOR]

Quasi-cyclic low-density parity-check (QC-LDPC) codes are adopted in many digital communication and storage systems. The encoding of these codes is traditionally done by multiplying the message vector with a generator matrix consisting of dense circulant submatrices. To reduce the encoder complexity, this paper introduces two schemes making use of finite Fourier transform. We focus on QC-LDPC codes whose circulant submatrices are of dimension (2^r-1)\times (2^r-1) and the entries are elements of GF (2^p) , where p divides r , and hence, GF (2^p) is a subfield of GF (2^r) . These cover a broad range of codes, and binary LDPC codes are a special case. Making use of conjugacy constraints, low-complexity architectures are developed for finite Fourier and inverse transforms over subfields in this paper. In addition, composite field arithmetic is exploited to eliminate the computations associated with message mapping and reduce the complexity of Fourier transform. For a (2016, 1074) nonbinary QC-LDPC code whose generator matrix consists of circulants of dimension 63 \times 63 with GF (2^2) entries, the proposed encoders achieve 22% area reduction compared with the conventional encoders without sacrificing the throughput. [ABSTRACT FROM PUBLISHER]

For large-scale distributed storage, besides redundancy, locality in terms of the number of data and parity symbols to access for failure recovery is a critical issue to address in order to ensure data availability, lower network traffic, and reduce recovery latency. A flexible yet low-complexity scheme for local erasure recovery is presented in this letter. Although the proposed scheme is not maximum distance separable, it does not have any constraint on the locality nor the parameters of the code, allows easy tradeoff on the locality and redundancy, and can achieve unequal protection over drives with different reliabilities. More importantly, it enables low-complexity implementation. An efficient hardware architecture for the proposed scheme is developed. It has very small overhead compared with traditional erasure codes when correction capability is not large, such as 2, 3, or 4. [ABSTRACT FROM PUBLISHER]

Improved video coding techniques introduced in the H.265/High Efficiency Video Coding (HEVC) standard allow video encoders to achieve better compression efficiencies. On the other hand, the increased complexity requires a new design methodology able to face challenges associated with ever higher spatiotemporal resolutions. This paper presents a computationally scalable algorithm and its hardware architecture able to support intra encoding up to 2160p@30 frames/s resolution. The scalability allows a tradeoff between the throughput and the compression efficiency. In particular, the encoder is able to check a variable number of candidate modes. The rate estimation based on bin counting and the distortion estimation in the transform domain simplify the rate–distortion analysis and enable the evaluation of a great number of candidate intra modes. The encoder preselects candidate modes by the processing of $8\times 8$ predictions computed from original samples. The preselection shares hardware resources used for the processing of predictions generated from reconstructed samples. To support intra $4\times 4$ modes for the 2160p@30 frames/s resolution, the encoder incorporates a separate reconstruction loop. The processing of blocks with different sizes is interleaved to compensate for the delay of reconstruction loops. Implementation results show that the encoder utilizes 1086k gates and 52-kB on-chip memories for TSMC 90 nm. The main reconstruction loop can operate at 400 MHz, whereas the remaining modules work at 200 MHz. For 2160p@30 frames/s videos, the average BD-rate is 5.46% compared with that of the HM software. [ABSTRACT FROM PUBLISHER]

Scaling is a key important arithmetic operation and is difficult to perform in Residue Number Systems (RNS). This paper proposes a comprehensive approach for designing efficient and accurate 2^n RNS scalers for important classes of moduli sets that have large dynamic ranges. These classes include the traditional 3-moduli set, but the exponent of the power of two modulo is augmented by a variable value x ( \lbrace 2^n-1, 2^n\underline+x, 2^n+1 \rbrace ), and any extended set with an additional modulo m_4 ( \lbrace 2^n-1, 2^n\underline+x, 2^n+1[,\underlinem_4]\rbrace ). The proposed approach embeds scaling into the formulation of the Chinese remainder theorem and the mixed radix system, and it exploits the properties of the target moduli sets to perform scaling explicitly in the RNS domain. This is accomplished by operating hierarchically on each channel without requiring reverse and forward conversions. Simple memoryless VLSI architectures are proposed based on the obtained formulations. The relative assessment indicates that not only are these architectures comprehensive and suitable for configurable systems, but they are also more efficient than the related state of the art in terms of both performance and energy. The experimental results obtained for a 90 nm CMOS ASIC technology show improvements in the area-delay product, normalized with respect to the dynamic range, of up to $57$ and $146$ percent with the proposed scalers for the augmented 3-moduli set (dynamic range of $4n-1$ bits) and an extended 4-moduli set (dynamic range of $6n$ bits), respectively. These improvements increase to $64.9$ and $263$ percent when the energy required per scaling is measured. The proposed scalers are not only flexible and cost-effective, but they are also suitable for designing and implementing energy-constrained devices, particularly mobile systems. [ABSTRACT FROM PUBLISHER]

Fractional motion estimation (FME) significantly enhances video compression efficiency, but its high computational complexity also limits the real-time processing capability. In this brief, we present a VLSI implementation of FME design in High Efficiency Video Coding for ultrahigh definition video applications. We first propose a bilinear quarter pixel approximation, together with a search pattern based on it to reduce the complexity of interpolation and fractional search process. Furthermore, a data reuse strategy is exploited to reduce the hardware cost of transform. In addition, using the considered pixel parallelism and dedicated access pattern for memory, we fully pipeline the computation and achieve high hardware utilization. This design has been implemented as a 65-nm CMOS chip and verified. The measured throughput reaches 995 Mpixels/s for $7680\,\times \,4320~30$ frames/s at 188 MHz, at least 4.7 times faster than prior arts. The corresponding power dissipation is 198.6 mW, with a power efficiency of 0.2 nJ/pixel. Due to the optimization, our work achieves more than 52% improvement on power efficiency, relative to previous works in H.264. [ABSTRACT FROM AUTHOR]

Motion estimation (ME) in the latest High Efficiency Video Coding standard adopts the quadtree coding structure and up to a $64\times 64$ prediction unit (PU) size to improve the coding gain. However, these techniques also have serious design problems regarding the complexity, data dependency, external memory bandwidth, and on-chip buffer size compared with previous standards, especially for real-time ultrahigh-definition video coding. To solve these problems, this paper proposes an efficient ME design with a joint algorithm and architecture optimization. To reduce complexity, we propose a predictive integer ME (IME) algorithm that selects the most probable search directions and steps through a statistical analysis to reduce the number of search points by 90.5%. We also employ a PU size-dependent fractional ME (FME) algorithm to reduce the interpolation filtering by 62.4% compared with the reference software. To resolve the corresponding dependency, we cascade the IME and FME computations via interlaced scheduling and propose an early motion vector prediction candidate approach. We use this scheduling with a 16\times 16$ processing unit to compute the partial matching cost of all PUs with the same 16\times 16$ current block in an interlaced order and share their common reference block to reduce the on-chip buffer size and off-chip memory bandwidth. The bandwidth is further reduced by a cache with double Z scan indexed addressing to simplify the cache controller. Implementation with a Taiwan Semiconductor Manufacturing Company 90-nm CMOS process supports the real-time encoding of at 60 frames/s operated at 270 MHz with 778.7k logic gates and 17.4 KB of on-chip memory. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a new hardware-efficient adaptive binary range coder (ABRC) and its very-large-scale integration (VLSI) architecture. To achieve this, we follow an approach that allows to reduce the bit capacity of the multiplication needed in the interval division part and shows how to avoid the need to use a loop in the renormalization part of ABRC. The probability estimation in the proposed ABRC is based on a lookup table free virtual sliding window. To obtain a higher compression performance, we propose a new adaptive window size selection algorithm. In comparison with an ABRC with a single window, the proposed system provides a faster probability adaptation at the initial encoding/decoding stage, and more accurate probability estimation for very low entropy binary sources. We show that the VLSI architecture of the proposed ABRC attains a throughput of 105.92 MSymbols/s on the FPGA platform, and consumes 18.15 mW for the dynamic part power. In comparison with the state-of-the-art MQ-coder (used in JPEG2000 standard) and the M-coder (used in H.264/Advanced Video Coding and H.265/High Efficiency Video Coding standards), the proposed ABRC architecture provides comparable throughput, reduced memory, and power consumption. Experimental results obtained for a wavelet video codec with JPEG2000-like bit-plane entropy coder show that the proposed ABRC allows to reduce the bit rate by 0.8%–8% in comparison with the MQ-coder and from 1.0%–24.2% in comparison with the M-coder. [ABSTRACT FROM PUBLISHER]

This paper presents the compute voltage regulator module (C-VRM), an architecture that embeds the information processing subsystem into the energy delivery subsystem for ultra-low power (ULP) platforms. The C-VRM employs multiple voltage domain stacking and core swapping to achieve high total system energy efficiency in near/sub-threshold region. Energy models for the C-VRM are derived, and employed in system simulations to compare the energy efficiency benefits of the C-VRM over a switched capacitor VRM (SC-VRM). A prototype IC incorporating a C-VRM and a SC-VRM supplying energy to an 8-tap fully folded FIR filter core is implemented in a 1.2 V, 130 nm CMOS process. Measured results indicate that the C-VRM has up to 44.8% savings in system-level energy per operation (Eop) compared to the SC-VRM system, and an efficiency \eta ranging from 79% to 83% over an output voltage range of 0.52 V to 0.6 V. Measured values of the Eop and \eta match those predicted by system simulations thereby validating the energy models. [ABSTRACT FROM AUTHOR]

In this brief, we propose a high-throughput layered decoder architecture to support a broader family of quasicyclic low-density parity-check (QC-LDPC) codes, whose parity-check matrices are constructed from arrays of circulant submatrices. Each nonzero circulant submatrix is a superposition of K cyclic-shifted identity matrices, where the circulant weight K\geq 1. We propose a novel layered decoder architecture to support QC-LDPC codes with any circulant weight. We present a block-serial decoding architecture which processes a layer of a parity check matrix block by block, where each block is a Z\times Z circulant matrix with a circulant weight of K. In the case study, we demonstrate an LDPC decoder design for the China Mobile Multimedia Broadcasting (CMMB) standard, which was synthesized for a TSMC 65-nm CMOS technology. With a core area of 3.9 mm^2, the CMMB LDPC decoder achieves a maximum throughput of 1.1 Gb/s with 15 iterations. [ABSTRACT FROM PUBLISHER]

Algebraic soft-decision (ASD) decoding algorithm of Reed-Solomon (RS) codes can achieve better performance-complexity tradeoff than other soft-decision decoding algorithms. The interpolation is a major step of ASD algorithms. In the case that multiple test vectors are involved, the interpolation needs to be carried out for each vector and leads to very high hardware complexity. To enable the sharing of computation results in the interpolation for different vectors, a backward interpolation scheme was developed previously to eliminate points from a given interpolation result, which is a Grobner basis. However, this scheme can only eliminate all points in the same code position when their multiplicities are all one and the number of points is one less than the number of polynomials in the Grobner basis. Larger multiplicities are required to achieve better error-correcting performance. Moreover, for general ASD algorithms, the points in the same code position may have different multiplicities. In this paper, a generalized backward interpolation algorithm is proposed through constructing equivalent Grobner basis. It is capable of reducing the multiplicity of each point in the same code position by one at a time until zero, and the multiplicity of each point can be different. As an example, the proposed scheme is applied to a Chase-type decoding that has multiplicity two in the flipping points, and efficient hardware architectures are developed. For a (255, 239) RS code with eight test vectors, employing the proposed backward interpolation leads to 18% area reduction and 23% speedup compared to repeating the interpolation over the flipping points for each test vector. [ABSTRACT FROM PUBLISHER]

This paper proposes a data bandwidth-oriented motion estimation design for resource-limited mobile video applications using an integrated bandwidth rate distortion optimization framework. This framework predicts and allocates the appropriate data bandwidth for motion estimation under a limited bandwidth supply to fit a dynamically changing bandwidth supply. The simulation results show that our proposed algorithm can achieve 66% and 41% memory bandwidth savings while maintaining an equivalent rate-distortion performance and meeting real-time targets, when compared with conventional approaches for low-motion and high-motion D1 (704\,\times\,576)-size video, respectively. The final implementation costs 122 K gate counts with TSMC 0.13-\mum CMOS technology and consumes 74 mW of power for D1 resolution at 30 frames/s which is 40% of that achieved in previous designs. [ABSTRACT FROM AUTHOR]

A new decoder architecture for nonbinary low-density parity-check (LDPC) codes is presented in this paper to reduce the hardware operational complexity in VLSI implementations. The low decoding complexity is achieved by employing adaptive message control (AMC) that dynamically trims the message length of belief information to reduce the amount of memory accesses and arithmetic operations. To implement the proposed AMC, we develop the architecture of a horizontal sequential nonbinary LDPC decoder. Key components in the architecture have been designed with the consideration of variable message lengths to leverage the benefit of the proposed AMC. Simulation results demonstrate that the proposed nonbinary LDPC decoder architecture can significantly reduce hardware operations and power consumption as compared with existing work with negligible performance degradation. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel path-preserving trellis-search (PPTS) algorithm and its high-speed VLSI architecture for soft-output multiple-input-multiple-output (MIMO) detection. We represent the search space of the MIMO signal with an unconstrained trellis, where each node in stage k of the trellis maps to a possible complex-valued symbol transmitted by antenna k. Based on the trellis model, we convert the soft-output MIMO detection problem into a multiple shortest paths problem subject to the constraint that every trellis node must be covered in this set of paths. The PPTS detector is guaranteed to have soft information for every possible symbol transmitted on every antenna so that the log-likelihood ratio (LLR) for each transmitted data bit can be more accurately formed. Simulation results show that the PPTS algorithm can achieve near-optimal error performance with a low search complexity. The PPTS algorithm is a hardware-friendly data-parallel algorithm because the search operations are evenly distributed among multiple trellis nodes for parallel processing. As a case study, we have designed and synthesized a fully-parallel systolic-array detector and two folded detectors for a 4 \times 4 16-QAM system using a 1.08 V TSMC 65-nm CMOS technology. With a 1.18 mm^2 core area, the folded detector can achieve a throughput of 2.1 Gbps. With a 3.19 mm^2 core area, the fully-parallel systolic-array detector can achieve a throughput of 6.4 Gbps. [ABSTRACT FROM AUTHOR]