87 results on '"Tuck, Barbara"'
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2. Be ready to make trade-offs when selecting a programmable architecture
3. Testing fully diffused blocks embedded in complex ASICs
4. What can users of programmable logic devices expect from PREP benchmarks?
5. OVI, IEEE meet on standardization of Verilog HDL
6. The VHDL/Verilog debate continues. How will they share the coveted crown?
7. FPGA vendors turn their attention to tools
8. Vendors vying for FPGA market try different strategies
9. Analog designers still trail behind their digital counterparts
10. ASIC testability tools force trade-offs in silicon, performance and coverage
11. Technologies move toward hardware/software codesign
12. FPGAs race for the gold in product development
13. Pinouts and performance drive PAL choices
14. What do digital designers need to master the art of analog design?
15. Automated compilers let users configure their own SRAMs
16. Designers must look beyond the obvious to discover the promise of synthesis
17. High-density ASICs force focus on testability; getting an ASIC of 20,000-plus gates to market on time means building testability into the design flow
18. Are mixed cells and arrays the solution ASIC vendors claim? Does embedding fully diffused blocks on gate arrays
19. Digitization broadens the scope of measurement and analysis
20. Network-distributed processing reduces run times for complex designs
21. Are designers' expectations for synthesis realistic?
22. European consumer products replete with mixed-signal, DSP technology
23. High-speed PALs keep pace with today's processors
24. High-density gate arrays: products too far ahead of technology?
25. Is synthesis the solution for testing complex ASICs?
26. FPGA, complex PLD vendors rush to support silicon with advanced tools
27. VLSI uses ViaLink antifuse to embed programmability into ASICs, ASSPs
28. EDA leaders getting serious about automatic test generation
29. ASIC choices increase for mixed 3-V/5-V designs
30. Choices expand to incorporate design for testability
31. VHDL poised to overtake Verilog as support grows
32. High-level synthesis unlocks potential of FPGAs
33. CrossCheck testability reaches commercial gate array family
34. Chase for process portability prompts advances in cell library tools
35. PLDs catch up to FPGAs in logic capacity and I/O
36. Denser, faster FPGAs encroach further on masked gate arrays
37. Vendor-independent floorplanner links synthesis with ASIC layout
38. Users turn to graphics for high-level system specification
39. Improved FPGAs deliver fast, predictable performance
40. Timing-driven partitioning tool splits design into multiple FPGAs after mapping
41. EDA vendors push to boost top-down design productivity
42. Split decision on HDLs forces VHDL/Verilog coexistence
43. Claims by FPGA tool vendors bury reality in noise
44. Fault simulator uses cycle-based algorithm
45. Emphasis shifts from density to I/O in low-density arrays
46. CrossCheck testability solution extended with interface to ATE
47. Mixed-signal ASIC toolset offers analog design for testability
48. 1.25-GHz ECL array has on-chip phased-lock loop
49. Hardware accelerator speeds mixed-level simulation
50. Interconnect key to speed of new programmable ASICs
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