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In this article, threshold-voltage VTH instabilities under positive gate voltage stress VGStress in GaN-on-Si devices are thoroughly investigated. Measurement-stress-measurement pBTI technique using ultrafast VG ramp was applied in this study. PBTI transients performed at different VGStress and several temperatures highlight the influence of two trap populations, one being related to Al2O3 gate oxide defects and the other one to CN acceptors in GaN lattice. Both trap populations are located close to the Al2O3/GaN interface and lead to VTH instabilities via two different underlying mechanisms simulated by TCAD. PBTI transients obtained under several dc and ac stress conditions have also been modeled using capture emission time (CET) maps and allowed the identification of the two trap populations. Analysis of the temperature-dependent CET maps gives an activation energy of 0.8–0.9 eV related to CN traps and an energy range between 0.7 and 1.5 eV ascribed to Al2O3 defects above the GaN conduction band energy. This study provides a better understanding of the underlying physical mechanisms, leading to BTI degradation in GaN-HEMT technologies.

We target the parameter extraction from ${I}$ – ${V}$ and ${C}$ – ${V}$ characteristics and modeling of organic thin-film transistors (OTFTs) from 150 K up to 350 K (in two different manufacturing technologies). We also analyze the temperature dependence of the extracted parameters. For that purpose, we used a unified model and parameter extraction method at different temperatures adapted to OTFTs. We validated our model by comparison with experimental ${I}$ – ${V}$ characteristics in both the linear and saturation regimes and ${C}$ – ${V}$ characteristics at different frequencies.

International audience; This work presents the performance and low-frequency noise (LFN) of 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The experimental measurements and the analysis are performed as a function of temperature for the first time, focusing on cryogenic applications, down to 4.2 K. The back bias impact on device performance is evaluated. The results reveal that the threshold voltage tuning is found to be temperature independent, allowing extra drain current improvement. This is particularly interesting for short channel devices, whose drain current gain with temperature lowering is expected to be smaller in comparison with long channel MOSFETs. LFN is characterized by means of time-domain current sampling measurements. Moderate and strong inversion regimes are investigated. The carrier number with correlated mobility fluctuations model can well describe the 1/f noise behavior down to 4.2 K. The physical origin behind the drain current noise-to-signal power augmentation with temperature lowering could be mainly attributed to the normalized transconductance improvement.

International audience; The wide range of cryogenic applications, such as spatial, high performance computing or high-energy physics, has boosted the investigation of CMOS technology performance down to cryogenic temperatures. In particular, the readout electronics of quantum computers operating at low temperature requires larger bandwidth than spatial applications, so that advanced CMOS node has to be considered. FDSOI technology appears as a valuable solution for co-integration between qubits and consistent engineering of control and read-out. However, there is still lack of reports on literature concerning advanced CMOS nodes behavior at deep cryogenic operation, from devices electrostatics to mismatch and self-heating, all requested for the development of robust design tools. For these reasons, this chapter presents a review of electrical characterization and modeling results recently obtained on ultra-thin film FDSOI MOSFETs down to 4.2 K.

In this paper, the flicker noise properties of bottom-gate ESL structured amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) from two different technologies have been studied and modeled. Model development is carried out by adapting the Unified Model parameter Extraction Method (UMEM), developed for parameter extraction and compact modeling of TFT devices, and the unified 1/f noise model. Furthermore, comparative study of device figures of merits is performed to point out the device performance enhancements that the different fabrication technologies have brought about. It is found out that both devices have low deep state density, whereas the second device demonstrated higher performance in terms of carrier mobility and subthreshold slope. Both the DC and noise models are validated by matching them against experimental data obtained in different regimes of device operation.

Junctionless transistors (JLTs) have promising advantages such as structural simplicity without p-n-junctions and bulk conduction-based operation for the realization of advanced complementary metal oxide semiconductor (CMOS) technologies. Here the channel-length dependence on the operation of JLTs with substrate biasing ( ${V}_{\text {gb}}$ ) was investigated in detail. Parasitic series resistance ( ${R}_{\text {sd}}$ ) noticeably decreased as ${V}_{\text {gb}}$ increased. In addition, transconductance ( ${g}_{\text {m}}$ ), its derivative ( dg m/ dV gf), and ON-drain current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) in a short-channel JLT were significantly affected by the ${V}_{\text {gb}}$ -modulated ${R}_{\text {sd}}$ with charge coupling effects. This work provides important information for better understanding and true estimation of intrinsic JLT performance, for practical applications based on polycrystalline Si, III–V semiconductors, and transition metal dichalcogenides (TMDs) nano-materials as well as advanced logic devices.

International audience; The applicability of the Lambert-W function-based parameter extraction methodology is demonstrated for 28nm FDSOI MOSFETs down to deep cryogenic temperatures (4.2K). The Lambert-W function enables to accurately model the inversion charge and drain current MOSFET characteristics from weak to strong inversion, while using the classical mobility law down to liquid helium temperature. The main MOSFET parameters were extracted versus temperature and gate length, showing the temperature independence of short channel effects and the strong mobility degradation at short channel length due to increased neutral defect scattering.

In this paper we present an analytical experimental study regarding the extraction and analysis of 28 nm FD-SOI MOSFET parameters, from room temperature down to 25 K, and from micro- to nanometer gate lengths. It is shown that the FD-SOI device behavior with temperature can reliably be described by the already established theory of physics for deep cryogenic conditions: Boltzmann statistics and phonon scattering mechanisms are the two main factors that define the device electrical behavior. Moreover, we also demonstrate the advantage of the Y-function as a parameter extraction method, across different channel lengths, and a wide temperature range. We demonstrate the dependence of threshold voltage, sub-threshold swing, low-field mobility and source-drain series resistance on temperature, and how this may be affected by the gate length decrease.

International audience; A new concept of differential effective mobility is proposed. It characterizes the effective mobility of an increment of drain current resulting from a small increase of inversion charge in MOSFET channel. It allows us to show that the effective mobility can be described by a local electric field approach and not entirely by an effective electric field model.

This work presents a new method, called “pinch to detect”, for the characterization of Random Telegraph Noise (RTN) in nanometer length Tri-Gate Nanowire MOSFETs, allowing for the maximum number of active RTN traps to be detected. We demonstrate that the channel pinch-off effect, which takes place in saturation region, can actually be exploited for the modulation of RTN amplitudes and kinetics, and therefore disable (or enable) the appearance of RTN signals which are present (or not) in linear region, where the channel is uniform. It is shown that by combining the measurements for three different channel configurations, i.e. uniform, pinched-off near the drain and pinched-off near the source, the total number of detectable RTN traps can be maximized. This conclusion is also supported by noise spectral analysis and TCAD simulations. Furthermore, it is demonstrated through how going to longer channels with no short-channel effects does not make this effect disappear, but just limit it to traps in the pinched-off region.

Under several circumstances, a nanowire transistor with a square cross-section behaves as a circular. Taking the Gate-All-Around junctionless transistor as a primary example, we investigate the transition of the conductive region from square to circle-like. In this case, the metamorphosis is accentuated by smaller size, lower doping, and higher gate voltage. After defining the geometrical criterion for square-to-circle shift, simulation results are used to document the main consequences. This transition occurs naturally in nanowires thinner than 50 nm. The results are rather universal, and supportive evidence is gathered from inversion-mode Gate-All-Around (GAA) MOSFETs as well as from thermal diffusion process.

International audience; This paper presents an electrical characterization and a compact modeling of FD-SOI fourgate qubit MOS devices, carried out at room temperature and in linear regime. The main figures ofmerit are extracted from average drain current curves using Y – function method. Poisson solver-based simulations are performed to interpret the experimental data, in particular the influence among gates and the effective channel length modulation. Furthermore, a drain current matching analysis between gates is conducted, and the main variability parameters are extracted. Our results, despite the unconventional device engineering, show a variability performance comparable to the state-of-the-art 28nm FD-SOI technology. Finally, a Lambert function based model is developed to validate both the electrical and statistical characterization. It is assumed, according to the experimental data, that the four gate device can be modeled as the series of four identical and independent transistors. Including the contribution of source and drain access resistance it has been possible to reproduce the device behavior at high external gates voltages.

We review recent compact modeling solutions for Organic and Amorphous Oxide TFTs (OTFTs and AOS TFTs, respectively), which were developed, under the framework of the EU-funded project DOMINO, to address issues specifically connected to the physics of these devices. In particular, using different approaches, analytical equations were formulated to model the Density of States (DOS), different transport mechanisms, trapping/de-trapping, drain current, stress, capacitances, frequency dispersion and noise. The final TFT models were, after implementation in Verilog-A, validated by means of the design and simulation of test circuits.

In this work, a continuous and symmetric trans-capacitance compact model for triple-gate junctionless MOSFETs is presented, valid in all regions of operation. Initially, the expressions of the gate, drain and source total charges are analytically derived based on a continuous and symmetric drain current compact model already developed. Then, the intrinsic capacitances are calculated via the differentiation of the terminal charges, verified against TCAD simulation data. The AC symmetry tests of the trans-capacitance compact model are thoroughly investigated.

This article presents a new methodology for the extraction of low-frequency noise (LFN) or random telegraph noise (RTN) parameters, such as the gate oxide interface trap density, ${N}_{\text {t}}$ , and the mobility fluctuations factor, $\Omega $ , without the influence of the source/drain series resistance, ${R}_{\text {sd}}$ . The method utilizes the ${Y}$ -function—which is immune to any first-order degradation, including the series resistance—as well as the intrinsic mobility degradation factors $\theta _{ {1,0}}$ and $\theta _{{2}}$ . The proposed extraction technique is first demonstrated through numerical calculations and then applied on experimental results of n-channel short length FinFETs. It is shown that if the ${R}_{\text {sd}}$ impact is not accounted for, the extracted LFN parameters through the classic carrier number fluctuations (CNF) with correlated mobility fluctuations (CMF) model can lead to significant extraction errors. This mainly concerns the correlated mobility factor $\Omega $ , which may be strongly underestimated, but also the extraction of the trap density ${N}_{\text {t}}$ .

In this article, we have studied the drain current and transconductance of nMOS fully depleted silicon-on-insulator (FDSOI) transistors operating at low temperature (typically < 20 K) when back gate is forward biased. Humps appear in the current, leading to oscillations of the transconductance with gate voltage, owing to mobility discontinuity due to intersubband scattering, in relation with the 2-D subband structure. The conditions for which these specific features appear in thin-film silicon-on-insulator (SOI) devices have been analyzed, by varying the temperature, drain voltage, silicon channel thickness, and gate length.

A comprehensive analysis of the MOSFET subthreshold swing for a 2D subband with exponential band tail of states is first proposed. Then, a compact analytical expression for the subthreshold swing as a function of temperature is derived, well accounting for both its cryogenic temperature saturation and classical higher temperature increase. Moreover, a generalized subthreshold swing calculation applicable to the situation where the MOSFET drain current should be evaluated from the conductivity function within the Kubo-Greenwood formalism is developed.

Variability of28nm FD-SOI transistors is evaluated for the first time down to ultra low temperatures (UL T), at T= 1 00mK. High performance is achieved at UL T for short channel transistors, with $\mathrm{I}_{\mathrm{ON}} > 1\mathrm{mA}\mu \mathrm{m}$ and $\mathrm{I}_{\mathrm{OFF}}$ below the equipment accuracy $(\mathrm{V}_{\mathrm{TH}})$ and current gain factor $(\beta)$ variabilities. Besides that, we demonstrated that the increase of $\mathrm{V}_{\mathrm{TH}}$ and $\beta$ variabilities at low temperature remains reasonably low in comparison to RT values and other CMOS technologies, so that it should not be detrimental to circuit operation in this range of temperatures.

We investigated the performances of GaN junctionless fin-shaped field-effect transistors (FinFETs) with two different types of gate structures; overlapped- and partially covered-gate. DC, low-frequency noise (LFN), and pulsed I-V characterization measurements were performed and analyzed together in order to identify the conduction mechanism and examine both the interface and buffer traps in the devices. The fabricated GaN junctionless device with overlapped-gate structure exhibits improved DC and noise performance compared to the device with partially covered-gate, even though its gate length is much larger. The LFN behavior was found to be dominated by carrier number fluctuations (CNF). At off-state, the device with partially covered-gate exhibits generation-recombination (g-r) noise on top of 1/ ${f}$ noise. This superposition is correlated with the severe current collapse revealed by pulsed I-V measurements. In contrast, the device with overlapped-gate shows clear 1/ ${f}$ behavior without g-r noise.

International audience; In this paper we demonstrate for the first time how the series resistance of an advanced CMOS device, such as the FinFET, can lead to an incorrect extraction of low-frequency noise parameters. In particular, the use of the carrier number fluctuations with correlated mobility fluctuations model is shown to be very sensitive to the transistor series resistance. We demonstrate how the classic fitting methods can lead to an underestimated value in the extraction of the mobility fluctuations factor Ω. Furthermore, we present an original method for suppressing this effect, by taking advantage of the series resistance immune Y-function.

The quality of interfaces between dielectrics and semiconductors has a tremendous impact on the performances of semiconductor devices. High-k dielectrics are omnipresent in the gate stack of advanced MOSFETs. They are also used as passivation layers for silicon in fields such as solar cells [1] or image sensors [2]. When referring to passivation, two mechanisms can be identified: chemical passivation (quantified by the interface state density, Dit) and electric-field passivation (quantified by fixed oxide charge density, Qox). An ideal characterization method for passivated silicon should give access to both chemical and field-effect relevant quantities (ideally being able to distinguish them) in a non-destructive way. Among the commonly used techniques, we can cite electrical methods based on current or capacitance monitoring of simple test devices [3], Corona characterization of semiconductors [4], carrier lifetime extraction [5] conducted through photoconductance or photoluminescence decay measurements, etc. The choice among these several options is based on criteria such as sensitivity, non-destructiveness, possibility of direct on-wafer probing without any additional device fabrication steps, ability to discriminate Dit and Qox, capability to provide a high spatial resolution. A recent technique which could meet all these criteria is the second harmonic generation (SHG) [6], provided that an appropriate calibration method is developed for Dit and Qox extraction. The SHG is a non-linear optics phenomenon: when a high intensity laser beam of wavelength λ reaches a sample, a second harmonic wave at λ/2 is generated by the sample. For centrosymmetric materials (such as silicon, SiO2, Al2O3, etc.) the SHG signal contains two parts: one related to the symmetry breaking inherently present at interfaces between two different materials, and another one produced by any “static” electric field in the sample [7]. Such field is present at the vicinity of dielectric-to-semiconductor interfaces due to charge trapping by various mechanisms. In other words, the magnitude of the generated SHG signal contains information on both Dit and Qox This technique has already been used for dielectric characterization with various modalities (SHG versus power, time, wavelength ...) [8], [9], [10]. The SHG proved very promising (sensitive, non-destructive, applied directly on-wafer, etc.); however its extensive use still needs a more general calibration methodology. Such a methodology requires not only SHG measurements, but also real Qox/Dit values extracted by classical electrical methods on the same samples and modeling to understand/anticipate the expected effect of these parameters on the SHG signal. In this paper, we’ll discuss all these issues based on a review of our recent advances on how to exploit SHG for dielectrics on semiconductor characterization. Acknowledgements This work was supported by Region Rhône Alpes (ARC6 program), the French National Research Agency within the framework of the OXYGENE project (ANR-17-CE05-0034) and French National Plan Nano2022, within the IPCEI Nanoelectronics for Europe program. [1] A. G. Aberle, "Surface passivation of crystalline silicon solar cells: a review," Progress in Photovoltaics: Research and Applications, vol. 8, pp. 473-487, 2000. [2] J. L. Regolini, D. Benoit, and P. Morin, "Passivation issues in active pixel CMOS image sensors," Microelectronics Reliability, vol. 47, pp. 739-742, 2007. [3] D. K. Schroder, Semiconductor Material and Device Chracterization, 3rd Edition ed. New Jersey: John Wiley & sons, 2006. [4] M. Wilson, J. Lagowski, L. Jastrzebski, A. Savtchouk, and V. Faifer, "COCOS (corona oxide characterization of semiconductor) non-contact metrology for gate dielectrics," AIP Conference Proceedings, vol. 550, pp. 220-225, 2001. [5] D. K. Schroder, "Carrier lifetimes in silicon," Electron Devices, IEEE Transactions on, vol. 44, pp. 160-170, 1997. [6] G. Lupke, "Characterization of semiconductor interfaces by second-harmonic generation," Surface Science Reports, vol. 35, pp. 75-161, 1999. [7] J. E. Sipe, D. J. Moss, and H. M. van Driel, "Phenomenological theory of optical second- and third-harmonic generation from cubic centrosymmetric crystals," Physical Review B, vol. 35, pp. 1129-1141, 1987. [8] J. Price, M. Lei, P. S. Lysaght, G. Bersuker, and M. C. Downer, "Charge trapping defects in Si/SiO2/Hf(1−x)SixO2 film stacks characterized by spectroscopic second-harmonic generation," Journal of Vacuum Science & Technology B, vol. 29, p. 04D101, 2011. [9] N. M. Terlinden, G. Dingemans, V. Vandalon, R. H. E. C. Bosch, and W. M. M. Kessels, "Influence of the SiO2 interlayer thickness on the density and polarity of charges in Si/SiO2/Al2O3 stacks as studied by optical second-harmonic generation," Journal of Applied Physics, vol. 115, p. 033708, 2014. [10] H. Park, J. Qi, Y. Xu, K. Varga, S. M. Weiss, B. R. Rogers, et al., "Boron induced charge traps near the interface of Si/SiO2 probed by second harmonic generation," Physica Status Solidi (b), vol. 247, pp. 1997-2001, 2010.

GaN-based materials are expected to show excellent immunity against short-channel effects because they have relatively lower permittivity and higher electron effective mass, compared to other materials such as Si, Ge, and In(Ga)As. To further reduce the short-channel effects, it is important to enhance the gate controllability of the device by utilizing a gate-all-around (GAA) structure. In this article, GaN vertical GAA nanowire MOSFETs with various diameters of 120, 75, and 45 nm have been fabricated. The device with a diameter of 120 nm shows a threshold voltage of 0.7 V, drain saturation voltage of 0.5 V, and subthreshold swing of 70 mV/decade, which would be suitable for low-voltage/power applications. However, the devices with smaller diameters of 75 and 45 nm show peculiar characteristics, such as a second rise of the drain current in output characteristics and a negative transconductance.

In this article, we investigate the impact of the hot carrier (HC) aging on the performance of nanoscale n-channel triple-gate junctionless MOSFETs with channel length varying from 95 down to 25 nm. The devices were electrically stressed in the ON-state region of operation at fixed gate voltage ${V}_{g} = {1.8}$ V and drain bias ${V}_{d} = {1.8}$ V, with the stress time being a variable parameter. The device degradation was monitored through the relative change with stress time of the threshold voltage, subthreshold swing, linear drain current, low-field mobility, series resistance, and gate current. For relatively long-channel transistors ( ${L} = {95}$ nm), the threshold voltage and the subthreshold swing remain almost unchanged, whereas the ON-state drain current is degraded showing a good correlation with the series resistance degradation, caused by HC-induced damage in the drain region. For short-channel transistor ( ${L} = {45}$ nm), the HC-induced damage is extended in the channel region: interface traps are generated, exhibiting good correlation with both threshold voltage and low-field mobility degradations. For the very short-channel device ( ${L} = {25}$ nm), after long stress time, the HC-induced interface degradation is severe, causing a continuous increase of the ideality factor with increasing the gate voltage.

Substrate-bias-affected unique electrical characteristics of junctionless transistors (JLTs) were investigated in detail. Bulk channel thickness of JLTs ( ${t}_{\mathrm {si\_{}eff}}$ ) was effectively modulated by back-gate bias ( ${V}_{\text {gb}}$ ). The variation in threshold voltage ( ${V}_{\text {th}}$ ) $\vphantom {^{\int }}$ and mobility degradation were observed in the reduced ${t}_{\mathrm {si\_{}eff}}$ , due to the negative ${V}_{\text {gb}}$ -induced depletion of free electrons. The ${V}_{\text {gb}}$ effect was also influenced significantly by the doping concentration in JLTs. In addition, numerical simulations verified those results and analytical equations explained well the experimental results.

In this chapter, we present the most important aspects of our recent research work concerning the low-frequency noise (LFN) characterization and modeling of Fully Depleted Silicon-on-Insulator (FDSOI) MOSFETs, as well as the development of circuit noise simulation methods. Before doing so, we make a brief introduction (Sect. 1) on the importance of LFN characterization and modeling, especially in sub-μm multi-interface devices such as the FDSOI MOSFETs.

A new differential method for accurate extraction of electrical parameters of high-electron mobility transistor (HEMT) devices for gallium nitride (GaN) technology is proposed. This method, presented here for the first time, is used to study the mobility degradation with gate length, allowing an analysis of the contribution of the gate edge region to the total metal–insulator semiconductor (MIS)-HEMT device conductance. First, an analytical model is proposed to account for the relative conduction of the edges and the main flat part of the channel HEMTs. Second, the differential method allows the split- CV mobility extraction of each part, allowing a precise analysis of the resistive contribution of each region of the HEMT devices. This study has been performed over a large range of channel lengths for two normally OFF HEMT GaN wafers having different recess depths.

Thorough investigations of the low-frequency noise (LFN) in a fully depleted silicon-on-insulator technology node have been accomplished, pointing out on the contribution of the buried oxide (BOX) and the Si-BOX interface to the total drain current noise level. A new analytical multilayer gate stack flat-band voltage fluctuation-based model has been established, and 2D numerical simulations have been carried out to identify the main noise sources and related parameters on which the LFN depends. The increase of the noise at strong inversion could be explained by the access resistance contribution to the 1/f noise. Therefore, considering uncorrelated noise sources in the channel and in the source/drain regions, the total low-frequency noise can simply be obtained by adding to the channel noise the contribution of the excess noise originating from the access region (Δr). Moreover, only two fit parameters are used in this work: the trap volumetric density in the BOX, and the 1/f access noise level originating from the access series resistance, which is assumed to be the same for the front and the back interfaces.

International audience; Unreliable mobility values, and particularly greatly overestimated values and severely distorted temperature dependences, have recently hampered the development of the organic transistor field. Given that organic field-effect transistors (OFETs) have been routinely used to evaluate the mobility, precise parameter extraction using the electrical properties of OFETs is thus of primary importance. This review examines the origins of the various mobilities that must be determined for OFET applications, the relevant extraction methods, and the data selection limitations, which help in avoiding conceptual errors during mobility extraction. For increased precision, the review also discusses device fabrication considerations, calibration of both the specific gate-dielectric capacitance and the threshold voltage, the contact effects, and the bias and temperature dependences, which must actually be handled with great care but have mostly been overlooked to date. This paper serves as a systematic overview of the OFET mobility extraction process to ensure high precision and will also aid in improving future research.

International audience; For the first time, an in-depth analysis of the intertier dynamic coupling and RF crosstalk of digital circuits in 3D sequential integration enables to conclude on the need of a Ground Plane (GP) for various applications. Experiments in conjunction with TCAD simulations reveal the parasitic capacitances responsible for the dynamic coupling effects and their impact is investigated for a 3D sequential 2-bitcell SRAM cell circuit configuration. Furthermore, we show a greater than 20dB suppression up to 100GHz of the inter-tier RF crosstalk, achieved by the addition of a strategically designed polysilicon Ground Plane between active device layers enabling the possibility of heterogeneous 3DSI integration without metallic Ground Plane. We propose a technological solution to create experimentally a 34nm-thick polysilicon GP of 1.8x10 20 at/cm 3 n-doping and 295Ω/sq sheet resistance.

In this paper, we compare the evolution with temperature of the experimental characteristics of Nanonet-based Field-Effect Transistors, with a modelling of carrier transport in the percolating regime. The main electrical parameters of Nanonet-based Field-Effect Transistors that featured different nanowire densities and source-drain distances were extracted from static measurements at different temperatures. The temperature dependence of low field mobility and threshold voltage was explained by the temperature activated behaviour of inter-nanowire junctions, and the activation energy dispersion of individual junctions. A Monte-Carlo simulation of Nanonet FET in the shape of a random percolating network of resistances and thermally activated junctions was used to confirm the influence of activation energy dispersion on low field mobility. The simplest model which was able to capture experimental trends consisted in a bimodal distribution of activation energies, with a subset of non-thermally activated junctions (resistive junctions) while other junctions were thermally activated (energy barriers at the junctions).

A new methodology for MOSFET characterization making use of the on-resistance characteristics Ron(Vg,Vd) = Vd/Id(Vg,Vd) and associated derivatives dRon/dVg and dRon/dVd is proposed. This approach enables to eliminate the influence of source-drain series resistance Rsd not only in linear region but also in non-linear region of MOSFET operation. Therefore, it allows for intrinsic MOSFET parameter extraction free from source and drain series resistance.

The impact of different interfacial layers (ILs) on the electrical performances of Au/Ti/HfO2/Ge0.9Sn0.1 metal oxide semiconductor (MOS) capacitors is studied. Parallel angle resolved x-ray photoelectron spectroscopy measurements show that germanium diffuses into the HfO2 layer when no IL is used. This results in an increase in the tin content at the interface and a high interface state density. We demonstrate that the use of an IL prevents germanium and HfO2 intermixing and improves the electrical performance of MOS capacitors. Several ILs are studied such as alumina (Al2O3) and plasma oxidized GeSn (GeSnOx) prior to HfO2 deposition. C–V measurements correlated with simulations made by a customized analytical model indicate an interface state density of 5 × 1011 eV−1 cm−2 for the HfO2/GeSnOx/Ge0.9Sn0.1 gate stack. This result is promising for the integration of high mobility GeSn channels in CMOS devices.The impact of different interfacial layers (ILs) on the electrical performances of Au/Ti/HfO2/Ge0.9Sn0.1 metal oxide semiconductor (MOS) capacitors is studied. Parallel angle resolved x-ray photoelectron spectroscopy measurements show that germanium diffuses into the HfO2 layer when no IL is used. This results in an increase in the tin content at the interface and a high interface state density. We demonstrate that the use of an IL prevents germanium and HfO2 intermixing and improves the electrical performance of MOS capacitors. Several ILs are studied such as alumina (Al2O3) and plasma oxidized GeSn (GeSnOx) prior to HfO2 deposition. C–V measurements correlated with simulations made by a customized analytical model indicate an interface state density of 5 × 1011 eV−1 cm−2 for the HfO2/GeSnOx/Ge0.9Sn0.1 gate stack. This result is promising for the integration of high mobility GeSn channels in CMOS devices.

In this brief, we upgrade our initial drain current compact model for triple-gate junctionless transistors (JLTs) to a continuous model satisfying the source/drain (S/D) symmetry. This is achieved by reformulating the key equations of our original model, using Lambert-function-based terminal charges. The upgraded model is compact, bulk-referenced valid in all regions of operation and it is validated through comparison with experimental data to verify its accuracy. The symmetry condition is investigated and validated performing the dc Gummel symmetry test (GST) for all derivatives up to the fifth order.

International audience; The negative bias temperature instability (NBTI) is investigated in ultrathin body ultrathin box (UTBB) fully depleted silicon-on-insulator (FD-SOI) p-MOSFETs with zero back gate bias and small drain bias voltage. The threshold voltage shifts during stress at different temperatures and gate bias voltage conditions show that the NBTI is dominated by the trapping of holes in preexisting traps of the gate dielectric, while the recovery transient follows a logarithmic-like time dependence. Considering the hole-trapping/detrapping mechanisms, NBTI modeling has been proposed capturing the temperature and gate voltage dependence.

We propose three innovative SOI Tunnel FET architectures to solve the recurrent issue of low ION and degraded subthreshold slope measured on TFETs. These are evaluated and compared with a standard TFET structure (with lateral tunneling) using the Sentaurus TCAD tool. Extending the source (anode) at the bottom of the body region generates vertical band-to-band tunneling. Moreover, reducing the vertical distance between the extension and the gate oxide (Lrt) yields a very steep slope and higher ION compared to a device with only lateral tunneling, but only for gate lengths longer than 100 nm. Using an ultrahigh boron dopant concentration (1021 cm−3) thin layer at the bottom for extremely small body thickness (TSi

We present a detailed study of the process influence on two-dimensional electron gas (2DEG) transport properties in Al0.25Ga0.75N/AlN/GaN heterostructure. Hall effect measurements are used to analyze the conduction in normally on devices demonstrating the formation of a second channel at the Al2O3/AlGaN interface for high biases. Electrical characterization is performed on a large set of devices for temperatures ranging from 25 °C to 250 °C, and 2DEG mobility is extracted using split C-V measurement technique. Various technological splits were experimentally tested and the corresponding mobility characteristics were modeled using the Kubo-Greenwood formula in order to determine the dominant scattering phenomenon limiting the 2DEG mobility.

Self-heating in fully depleted silicon-on-insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is experimentally studied using the gate resistance thermometry technique, in a wide temperature range from 300 down to 4.2 K. We demonstrate that below 160 K, the channel temperature increase ( $\Delta {T}$ ) due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance. This power dependence is interpreted in terms of temperature dependent thermal conductivity. The thermal resistance dependence on the active device temperature ( ${T}_{\text {Device}}$ ) indicates that the former one is mainly driven by the thermal conductivity of the oxide layer. Moreover, based on this dependence we reconstructed the channel temperature increase for each dissipated power and ambient temperature, and we found that the calculated values were in a good agreement with the experimental ones. Results indicate that even at low temperatures, thermal resistance does not depend significantly on the silicon channel thickness (ranging from 7 up to 24 nm), whereas the buried-oxide thinning (145 and 25 nm) strongly reduces the magnitude of the thermal resistance. Finally, this paper intends to fill the gap of experimental data concerning self-heating in advanced FDSOI transistors at low temperatures, revealing limitations and perspectives that should be taken into account for future work.

Endurance reliability at the array level of resistive random access memories (RRAMs) is addressed. Both oxide based RAM and conductive bridge RAM stacks are extensively characterized, presenting various measurements over resistive layers, memory stacks, and programming conditions. These measurement results allow to extract the maximum number of cycles before breakdown $\text {N}_{c\,\text {max}}$ . It is found that this quantity follows a log-normal law. According to this first significant result, the impact of SET and RESET conditions on $\text {N}_{c\,\text {max}}$ statistics is studied. Using tailored ramp voltage stress (RVS) measurements, the minimum RRAM switching voltage is extracted along the endurance cycles and then correlated with the memory degradation. To explain and better understand all these experimental results, a stochastic model based on defect generation in a constriction zone of the resistive layer during cycling is proposed. After exploration of the size, geometry, and shape of such constriction zone, as well as different probability laws governing breakdown, modeled $\text {N}_{c\,\text {max}}$ distributions fitting the experimental ones are successfully generated and deeper explanations about the origin of the maximum number of cycles variability are inferred.

International audience; Two different lateral GaN-based nanowire gate-all-around transistors with and without 2-D electron gas (2-DEG) channel were fabricated using top-down approach, and their noise characteristics were investigated. The nanowire transistor with 2-DEG channel had a relatively larger channel cross section, which consists of regrown AlGaN/GaN plateau on the trapezoidal GaN layer, and exhibited negative threshold voltages ( ${V} _{\textsf {th}}$ ). The transistor without 2-DEG channel consisted only GaN layer with triangular-shaped smaller channel cross section and exhibited a positive ${V} _{\textsf {th}}$ . Both nanowire transistors clearly demonstrated typical $1/{f}$ noise characteristics, but the AlGaN/GaN nanowire transistor with 2-DEG channel showed larger noise magnitude. The noise characteristics of both devices are well explained by the carrier number fluctuation with correlated mobility fluctuation model. Using this model, the interface trap densities and the remote Coulomb scattering parameters were extracted, revealing a worse interface quality for the AlGaN/GaN device on the one hand, but stronger scattering for the narrow GaN transistor on the other hand.

International audience; The reliability of mobility evaluation of organic field-effect transistors (OFETs) is a serious issue because numerous overestimated and underestimated mobilities have been reported recently. A reliable approach to accurately evaluate OFET mobility is therefore highly desirable. Here, two commonly employed methods and the Y function method (YFM) were used to extract the mobilities of indacenodithiophene-cobenzothiadiazole (IDT-BT) OFETs with four different contact metals. The mobilities extracted by the commonly used methods varied greatly with the contact metal and channel length, whereas those extracted by the YFM were very stable and approached the intrinsic mobility of IDT-BT. Our results show that the YFM is a precise approach that can be widely used to evaluate OFET mobility.

International audience; In this work, we present an experimental method that allows for a proper distinction between oxide (front or back) and semiconductor traps in FDSOI MOSFETs, using all four bias terminals. To this end, two cases of Random Telegraph Noise (RTN) measured signals are studied. It is shown that this method can also be used to localize the trap across the channel. Furthermore, the trap's electrostatic impact is proven to be misleading when it comes to trap localization in nanoscale devices.

International audience; FDSOI technologies are very promising candidates for future CMOS circuits as they feature low variability, improved short channel effect and good transport characteristics. In this paper, we review the main electrical techniques and methodologies used to characterize the important MOS device parameters. First, the capacitance-voltage measurements are considered for the vertical stack characterization of FDSOI structures with HK/MG gate, ultra thin film channel, thin box oxide and back plane substrate. Then, the MOSFET parameter extraction methods are illustrated, as well as the transport and mobility assessment using various techniques (I-V, magneto-transport). Finally, the methodology to study the local variability of the electrical characteristics is also discussed.

International audience; The low-frequency noise in triple-gate junctionless n-MOSFETs, with channel lengths varying from 95 to 25 nm and operating in the bulk and accumulation modes, is investigated by measurements in the frequency and time domains. The experimental drain current noise spectra present 1/f and Lorentzian-type behavior components. The noise spectra in the time domain reveal that the Lorentzian-type behavior components are due to the capture and emission processes of carriers at discrete gate insulator traps, resulting in random telegraph noise (RTN). The 1/f behavior can be described by the carrier number with the correlated mobility fluctuations model. In the below-threshold region, the conducting channel is isolated from the interface by depletion region. In the above-threshold region (bulk conduction mode), the histograms of the time-domain data show multilevel switching events, from which one or more individual traps can be distinguished. The extracted time constants of two-level RTN signals indicate the interaction of a single trap either with the channel or with both channel and gate. The relative RTN amplitude is described with the carrier number with the mobility correlated fluctuations physics-based model or with the “hole in the inversion layer” stochastic simulation-based model, enabling estimation of the flat-band voltage fluctuation caused by the RTN.

International audience; The device transport parameters (subthreshold slope, low-field mobility, series resistance, and threshold voltage) of n-channel triple-gate junctionless transistors are investigated in the temperature range 298-398 K. The temperature dependence of these parameters is analyzed to clarify the mechanisms responsible for the impact of temperature on the device performance. Based on analytical empirical expressions capturing their temperature dependence, our analytical compact model can predict the transfer and output characteristics at elevated temperatures with good accuracy.

session 1: Fabrication and Process characterization; International audience; We propose for the first time a method based on C-V measurement to extract the bridge doping profile which governs the A2RAM performances. Assessed with TCAD simulation and simple extraction model adapted from bulk devices, this technique is validated with experimental data.