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Superconductive Rapid Single Flux Quantum (RSFQ) is an emerging cryogenic technology promising a significant boost in performance and ultra-low power consumption. The operating frequency achieved by RSFQ digital integrated circuits is several orders of magnitude greater than traditional CMOS circuits. The fundamental difference of RSFQ circuits, however, renders traditional clocking techniques appropriate for CMOS unsuitable for RSFQ technology. Most RSFQ logic gates, such as AND and OR, are sequential in nature. The number of pipeline stages is therefore significantly greater in RSFQ as compared to CMOS, complicating the clock distribution network design process. This issue is further exacerbated with the need for splitters to achieve a fanout greater than one and the need for transmission lines rather than ordinary metallic wires as in CMOS. In this work, QuCTS — single flux Quantum Clock Tree Synthesis — is presented. QuCTS utilizes a two stage framework for synthesizing clock networks. In the clock skew scheduling stage, the clock signal arrival time of each gate is chosen to maximize the robustness of the circuit to timing variations. In the clock tree synthesis stage, the layout of the clock distribution network is generated based on a novel delay equilibration technique. QuCTS is the first clock tree synthesis tool for RSFQ circuits utilizing useful clock skew. The synthesized network satisfies the clock arrival time requirements while minimizing the associated overhead, such as the interconnect length and number of delay elements. The tool is validated on a set of benchmark circuits. In a prototypical case study, a clock tree is generated for the AMD2901 with 1,049 clock sinks in 53 minutes while satisfying the clock arrival time.

This paper proposes a method for generating RSFQ logic circuits utilizing special RSFQ gates in logic synthesis. It is suited for the standard technology mapping flow used in logic synthesis tools and enables generating RSFQ circuits utilizing confluence buffers (CBs) and resettable DFFs (RDFFs), to reduce the number of clocked gates by reduction of logic depth. A library of supergates, each consisting of several gates, is used to compose a resultant circuit in the technology mapping. In this paper, a library containing supergates including those special gates is generated and is utilized to design circuits with the gates. First, a generation of a supergate library is proposed to introduce CBs and RDFFs, which realize logic OR without clock pulses and a fused function of logic AND and NOT, respectively. The generated library contains supergates including the special gates and they are used to compose the resultant circuits with the special gates. A mapping approach is also proposed. It distinguishes non-clocked gates such as CBs and clocked gates. It takes the number of inserted DFFs for path balancing into account to reduce the number of clocked gates. The method was implemented into the state-of-the-art academic EDA tool, i.e., ABC, and was evaluated. Evaluation results show that the number of clocked gates is reduced by about 30% from the original ABC with path-balancing DFFs.

It is known that rapid single-flux-quantum (RSFQ) circuit technology and its energy-efficient derivatives are considered as one promising technology in superconducting digital applications. In this paper, given the placement result of a multiple-stage pipelined architecture with n gate columns and m gate components in an RSFQ circuit inside a rectangular layout, it is assumed that signals can be propagated from the primary inputs on the left boundary to the primary outputs on the right boundary. Firstly, a lower bound on the routed width of one PTL region can be defined as the estimated width of one PTL region. Furthermore, the sum of the estimated widths of all the PTL regions in an RSFQ circuit can be defined as the estimated region width in an RSFQ circuit and the estimated width can be used as the objective function for the design of the clock distribution in an RSFQ circuit. Based on the flexibility of using the clock splitters (SPLs) inside the gate components for the propagation of clock signals, an iterative assignment algorithm can be proposed to complete the assignment of the tree-based clock connections with minimizing the estimated width of an RSFQ circuit. From viewpoint of numerical experiments, the experimental results show that the reduction of the estimated region width can lead to the reduction of the final width of the PTL regions in an RSFQ circuit. Compared with the design of Kito’s tree-based clock distribution for 5 tested RSFQ circuits, the experimental results show that the design of our proposed tree-based clock distribution with two capability parameters, 2 and 3, on a clock SPL can use reasonable CPU time to reduce 47.03% and 54.33% of the estimated region width and 44.83% and 45.25% of the final width for 5 tested RSFQ circuits on the average, respectively.

Aided by the advancement of super-conductive materials, rapid single flux quantum (RSFQ) digital circuits are emerging as a promising complement or even replacement of the traditional CMOS digital integrated circuits. RSFQ digital circuits typically work at a low temperature of around 4.2 K, i.e., around −268.95 °C. Nevertheless, the operating frequency of RSFQ digital circuits reaches up to 770 GHz, which is orders of magnitudes faster than contemporary CMOS digital circuits. The high operating frequency causes critical design challenges especially for the clock networks and data path signals, where relative skew on wires need to be observed for achieving the correct functionality. Therefore, for designing a timing-variability-aware SFQ layout, it is necessary to match the PTL delays that are proportional to their respective lengths. And the matching of PTL delays should be carried out by extensions in PTL lengths. To meet the above-mentioned critical timing requirements, it is necessary to incorporate length-matching constraints into a routing problem, which is transformed from the timing requirements of matching the PTL delays during the logical synthesis stage. However, existing routing algorithms are inherently limited by preallocated splitters (SPLs), which complicates the subsequent routing stage under length-matching constraints. In this article, in order to effectively address the length-matching constraints, we reallocate SPLs to fully utilize routing resources. We propose the first multiterminal routing algorithm for RSFQ circuits, which integrates SPL reallocation into the routing stage and achieves 100% routing completion in the tested benchmarks. Compared with the state-of-the-art method, the proposed multiterminal routing algorithm reduces the required area by 17% and the runtime by 7%.

A 128-b rapid single-flux-quantum (RSFQ) Advanced Encryption Standard (AES) encryption accelerator based on bit-slice architecture is proposed for the first time. Unlike the traditional methods, the method of looking up only one 256-B table to complete the entire AES round function is proposed. The proposed method can reduce nearly 50% of the hardware cost compared to the traditional method. The simple lookup table, shift, and xor operations are used in the proposed accelerator where one 256-B table needs to be stored for lookup table operations. The RSFQ logic circuits of the proposed accelerator are designed and simulated at the logic level. It consists of 136 558 JJs based on the Open Dataset of CONNECT Cell Library for AIST ADP2. The simulation results show the proposed accelerator works correctly.

Fast time-to-digital converters (TDCs), used to convert a continuous time interval into discrete number for further processing, serve diverse applications ranging from photon/particle detectors to communication systems employing delay-encoded pulses. Being a multi-rate digital circuit, the TDC is also a good candidate to explore operation of Energy-Efficient Rapid Single Flux Quantum (ERSFQ) circuits at high (>10 GHz) clock frequency. We designed a TDC using ERSFQ cells, targeting the 10-kA/cm2 SFQ5ee fabrication process at MIT Lincoln Laboratory. The main elements of the circuit comprise a 9-bit binary ripple counter and a parallel-to-serial converter. A frequency divider and a pulse distribution network with a decision-making element are designed to control the operation. The ERSFQ TDC was operated up to 25 GHz clock frequency (40 ps time resolution) and with a power consumption of around 14 µW for all ERSFQ components. The design specifications such as number of junctions and area will be discussed together with the power delivery technique involving an over-pumped feeding Josephson transmission line (JTL).

RSFQ circuits require a DC bias current to operate properly. The bias current in conventional RSFQ circuits is supplied to each gate, resulting in large current requirements in VLSI complexity SFQ systems, on the order of tens to hundreds of amperes. These high currents are difficult to supply and distribute. Superconductive input/output pins and bias lines support this limited current. Large currents however require significant metal and input pin resources. In addition, large currents can inductively couple to sensitive superconductive inductors, degrading circuit operation and producing errors. Current recycling is a well known technique to reduce these bias currents. RSFQ circuits with similar bias current requirements can be placed on separate ground planes and serially biased. The inputs and outputs of these circuits are galvanically decoupled and require drivers and receivers between connections. In this paper, a methodology for automated partitioning of complex RSFQ circuits into blocks with similar bias currents is described, where the number of connections among the blocks is minimized. Blocks with a significant difference in bias current are balanced using dummy padding structures. These blocks are biased in series, reducing the total bias current by the number of partitions. The Fiduccia-Mattheyses algorithm is modified with RSFQ specific enhancements to partition the system. A geometric partitioning approach, optimized by simulated annealing, is also proposed. These algorithms are integrated into the circuit placement process, and the methodology is evaluated using several modified ISCAS’89 sequential benchmark circuits and the AMD2901. The proposed partitioning methodology is intended for use within an automated EDA flow to enable current recycling for arbitrary (non-uniform, irregular) VLSI complexity RSFQ circuits, drastically reducing overall bias current and input requirements

The hardware security of RSFQ circuits has become an issue of growing importance for prospective exascale computing systems. Hardware security in RSFQ circuits is particularly relevant to large scale data centers operating with sensitive information. The number of fabrication facilities for superconductive niobium-based technology is limited, and the supply chain for distributing fabricated circuits can be compromised. Logic locking is widely used in modern CMOS circuits to enhance security by masking the functionality of the circuit using a secret key. If an attacker possesses a physical circuit secured by logic locking, the attacker would be unable to determine the intended function. In this paper, a novel methodology for logic locking is proposed for SFQ circuits. Mutual inductances are used to apply additional currents to some or all of the logic gates. These currents behave as keys to access the functionality of the SFQ logic elements. In the proposed technique, only after an additional correct current is applied to all of the locked gates will the circuit produce the proper output. By using inductors with a positive and negative mutual inductance connected to the internal inductances of the gates, the range of current required to unlock a secured circuit is greatly narrowed. In this work, the operation of this proposed logic locking technique is demonstrated using modified SFQ OR gates to enable security while maintaining proper functionality. Less than 4% area overhead is achieved.

With the demand for data processing and storage increasing rapidly, the existing CMOS-based computing system is gradually unable to meet the amplification demand because of its high-power consumption. Due to high frequency and low power consumption, superconducting rapid single-flux-quantum (RSFQ) logic circuit technology is an attractive candidate. In this paper, we propose a novel placement method based on the layer layout. We layer the gates according to the logic level, which is the length of the longest path in terms of the number of clocked gates from any primary input (PI) of the circuit to the gate. Dummy gates are inserted so that any two adjacent layers can form a bipartite graph. Then the gates of each layer are reordered to minimize the half-perimeter wirelength (HPWL). Finally, the gates of each layer are assigned vertical positions to make the edges as straight as possible. The distance between adjacent layers is determined by the number of bending points of the edges between layers. We use several superconducting RSFQ logic circuits to evaluate the effectiveness of our proposed placement method, which uses HPWL and area as evaluation metrics. The experimental results show that compared with the Simulated Annealing (SA)-based placement method, the proposed approach can reduce the total HPWL and total area by an average of 77.77% and 57.56%, respectively.

Neuromorphic and bio-inspired circuits have reached considerable attention since Moore's Law is coming to its limitations. Information processing in mammalian brains takes place in a far more energy-efficient manner and significantly faster than in the best computing architecture nowadays. We propose an approach to bring those benefits to a superconducting information processing circuit. Since the computation in a neuronal network is considered as analogue and the computation as digital, the design is grown around a Josephson comparator with its inherent non-linearity in the transfer function as the central information processing unit. Furthermore, a modified version of the Josephson Transmission Line is used to realize an adaptable coupling between neuron cells. This circuit design benefits of the noise in a 4.2 K environment and is therefore more resilient to noise and switching errors than conventional digital circuits. The proposed circuit behavior in a 2-neuron configuration and the integration in a network topology will be investigated.

A high-throughput 4 $\boldsymbol{\times }$ 4-bit multiplier was demonstrated using an extremely careful timing design for low-voltage rapid single-flux-quantum (LV-RSFQ) logic. The design considers the lengths of all wires, bias dependency of the delays, and load dependency of the signal splitters. The key is to intentionally use both Josephson transmission lines and passive transmission lines for gate-to-gate wiring, even over short distances, to form the same structure wiring as the clock lines. The structure of the multiplier is based on a bit-parallel, gate-level pipeline to exploit throughput. The test chip was fabricated using the AIST 10-kA/cm $\boldsymbol{^2}$ , Nb/AlOx/Nb, 9-Nb-layer Advanced Process 2. The measured maximum operating frequency, throughput, and power consumption without cooling cost in the high-speed on-chip test were 52 GHz, 52 G-operations per second (GOPS), and 134 $\boldsymbol{\mu }$ W, respectively. Although the switching speed of the Josephson junctions was reduced by 40 $\boldsymbol{\%}$ owing to the low-voltage operation, the obtained clock frequency was as high as that demonstrated with the standard bias voltage. The energy efficiency was 381 tera-operations per second per watt (TOPS/W) at 4.2 K. Further improvement in energy efficiency is expected by using low-voltage half-flux-quantum (LV-HFQ) circuits and shrinking the size of Josephson junctions.

Accurate timing characterization of library cells is essential for adopting the standard digital design flow using EDA tools, such as static timing analysis (STA) with timing back-annotation. For RSFQ circuits, the propagation delay of a cell is influenced by the input and output load. We have developed an automated timing characterization methodology that facilitates extraction of timing constraints and propagation delays for each cell as a function of all the possible permutations of input and output load. While being highly accurate, such a comprehensive timing characterization requires a large number of simulation runs. To significantly reduce the total number of simulation runs, we propose to analyze independently, rather than jointly, the effect of succeeding cells with standard preceding load and preceding cells with standard succeeding load. In addition, for succeeding cells with a storage loop, the delay of a cell is dependent on the state of the succeeding cell. STA tools cannot account for state-dependent timing variations. To mitigate state-dependent timing constraint violations, a state-dependent timing correction is added to the hold/set-up time. We have generated Liberty files for multiple process corners using the load dependent as well as standard load timing tables. We compare the timing accuracy for each methodology. We have designed and simulated a 64-bit ALU with 90,256 junctions with Verilog HDL and timing back-annotation across multiple process corners using Synopsys VCS tool. To validate the three timing characterization methodologies, we have evaluated their timing accuracies by comparing with full circuit simulations on representative ALU sub-blocks.

Cell library is the keystone component that enables adoption of advanced electronic design automation (EDA) tools, such as logic synthesis and automatic place-and-route. The EDA tools are essential for scaling circuit complexity by orders of magnitude. We have designed a dual RSFQ/ERSFQ cell library for the MIT-LL SFQ5ee process, that can be used with the superconductor EDA tools suite that is being developed. In addition to satisfying the margins criterion, the performance of each cell has been optimized for Monte-Carlo statistical variations across multiple process corners including minimizing the spread of timing distributions. To enable a digital design flow using HDL simulations with timing back-annotation Liberty files have been developed for multiple process corners, using the load-dependent timing char-acterization. The cells have been designed for a standard height of 40 μm with a grid size of 20 μm. The library provides dedicated tracks for signal and power routing. Multiple independent biases are supported for RSFQ designs. The cells can be interconnected either by abutting or using passive transmission lines. Dedicated moat slots have been provided which are uniformly distributed across the cell. All cells are re-optimized post-layout. The library currently contains 22 unique types of cells. Initial validation of the cell library was performed by designing RSFQ and ERSFQ shift registers for the MIT-LL SFQ5ee fabrication process, which yielded wide operating margins. In addition, we present measurement results for a chip designed and fabricated to characterize several library cells using a multiplexing scheme.

Each superconductor logic family has distinct features and advantages. For instance, adiabatic quantum-flux-parametron (AQFP) circuits operate with very high energy efficiency, and rapid single-flux-quantum (RSFQ) circuits operate at very high clock frequencies. To build a hybrid system that combines the above advantages, we propose a compact interface between AQFP and RSFQ circuits that converts current signals in AQFP logic into flux signals in RSFQ logic using a non-adiabatic quantum-flux-parametron gate. Compared to a previously proposed AQFP/RSFQ interface, the proposed interface has far fewer Josephson junctions (4 vs. 11). We optimize the circuit parameters of the AQFP/RSFQ interface and demonstrate the interface at low speed as proof of concept. Furthermore, we demonstrate data propagation between AQFP circuits along a long passive transmission line via the AQFP/RSFQ interface at low speed to show that the AQFP/RSFQ interface can alleviate the interconnect length limit in AQFP circuits.

We demonstrated interface circuits between a half-flux-quantum (HFQ) circuit and a rapid single-flux-quantum (RSFQ) circuit to obtain SFQ/HFQ and HFQ/SFQ converters. These converters were created by simply inserting a resistor between an RSFQ circuit and the adjacent HFQ circuit, where both circuits are based on pulse logic. These converters enable us to create combinatory circuits that make the best use of the features of the two circuits. Using a DC/SFQ, SFQ/HFQ, HFQ/SFQ, and SFQ/DC converter, we measure an HFQ Josephson transmission line (JTL) composed of eight 0-0-π superconducting quantum interference devices (SQUIDs), which are the essential elements of an HFQ circuit. The 0-0-π SQUIDs are composed of two conventional Josephson junctions and a π-shifted ferromagnetic junction. The HFQ JTL demonstrated in this study is driven by a bias current 11-fold lower than that of a similar RSFQ JTL. These experimental results indicate that the HFQ circuit requires power that is two or more orders of magnitude lower than that of an RSFQ circuit.

Energy-efficient rapid single flux quantum (ERSFQ) circuits are often considered to have two working states including ERSFQ (zero static power dissipation) and RESFQ (resistive energy-efficient SFQ) state. In our previous research, a new working state called MIDSFQ state has been also found in which the biasing JJs cannot return to the non-voltage state after the dynamic process. Both the RESFQ and MIDSFQ states result in extra power dissipation and should be avoided if possible. In this paper, we investigate the characteristics of these three states and explain the working principle of the MIDSFQ state using the hysteresis effect. We obtain an optimization scenario to eliminate the MIDSFQ state and furthermore, a simple but effective method to improve power efficiency of ERSFQ circuits.

The increasing complexity of modern rapid single flux quantum (RSFQ) circuits has made the issue of multiple fanout of growing importance. Most RSFQ gates can only drive a single output. Splitter gates can however distribute an SFQ pulse to multiple fanout. To drive $N$ SFQ gates, $N-1$ splitters with a fanout of two are required. Large splitter trees are often used in high speed VLSI complexity SFQ systems. These splitters require significant area and increase the path delay. In this paper, three area and power efficient splitter topologies for large scale RSFQ circuits are introduced. These SFQ splitters are an active splitter tree with fewer JJs, a passive splitter, and a multi-output active splitter. A methodology is presented for determining when to use passive or active splitters. Tradeoffs among the number of JJs, bias current of each stage, and delay are reported along with a margin analysis. The proposed splitters greatly reduce the required bias currents and delay of large scale RSFQ circuits by enabling multiple fanout. The methodologies and techniques are applicable to automated layout and clock tree synthesis for large scale SFQ integrated circuits.

An architecture of rapid single-flux-quantum logic circuits using clockless gates is proposed. Compared with a circuit composed of only clocked gates, a circuit using clockless gates includes fewer clocked gates, and therefore, a smaller clock distribution network. A circuit in the proposed architecture is constructed from pipeline stages. Each pipeline stage consists of a column of clocked gates and a succeeding block of clockless gates. The function of a pipeline register of a stage is implemented by the latching function of the clocked gates in the column. The combinational logic of a stage is implemented by the logic function of the clocked gates in the column and that of the clockless gates in the block. We designed a two-stage-pipelined 4-bit carry-lookahead-adder using clockless gates as a design example of the proposed architecture. It had reductions of the count of clocked gates and the area by 33 and 13%, respectively, compared with that composed of only clocked gates. The 4-bit adder in the proposed architecture was fabricated and demonstrated with the maximum clock frequency of 21.4 GHz and the bias margin of $\pm$ 16%.

It is known that the pipelined architecture in a rapid single-flux-quantum (RSFQ) circuit can be constructed by inserting a set of path-balancing $D$ -type flip-flops (DFFs) into some gate columns. Based on the assignment of the gates involving the splitters (SPLs) inside each gate column in the placement stage, the passive transmission line (PTL) region between two adjacent gate columns can be formed for a set of 2-pin connections in the routing stage. In this article, given a set of 2-pin connections with length-matching constraints inside one PTL region, based on the efficient utilization of available space in two routing layers, a new grid-based Manhattan routing model can be defined to use available space inside two routing layers for the insertion of the extension lengths on the given connections. To minimize the routing width inside one PTL region, a two-way track-assignment-based routing algorithm using the defined routing model can be first proposed to assign two partitioned sets of vertical intervals onto the used tracks inside two routing layers and connect the corresponding horizontal segments for the given connections with no extension length. Based on the definition of the available areas in the initial two-layer routing result, an iterative flow-based insertion algorithm can be further proposed to insert the feasible detouring paths onto the available areas for the extension lengths on the given connections. If there is no available area for the extension lengths on the unsatisfied connections, an efficient insertion algorithm can be proposed to insert the detouring paths onto one extra area for the extension lengths on the unsatisfied connections. Compared with Kito’s routing algorithm and Cheng’s routing algorithm in length-matching-constrained region routing, the experimental results show that our proposed routing algorithm can use reasonable CPU time to decrease 22.2% and 16.3% of the region width for 12 tested examples on the average, respectively.

Rapid single-flux-quantum (RSFQ) circuits are developing rapidly, but there are still many layouts that need to be completed manually, greatly reducing the design efficiency. We report the shape constraints of Josephson transmission line (JTL), and then propose automatic placement and routing methods for RSFQ circuits. First, for the pipeline structure of concurrent-flow clocking, a detailed placement algorithm based on simulated annealing is proposed, which use D Flip-Flop (DFF) insertion, column placement, and intra-column perturbation strategies to ensure the synchronization of clock phase while completing the placement of logic cells. More importantly, for the shape constraints of JTL, a new two-step JTL routing method is proposed. The first step is dummy wire routing, and the shape violations and routing congestion caused by shape constraints are solved to search legal paths for JTL routing; in the second step, timing optimization is performed when replacing dummy wire with JTL cells. Experimental results show that the proposed automatic methods achieve a 5% area-reduction and a 20× speed-up compared to manual design.

Superconductive passive transmission lines (PTL) are widely used for signal routing in large-scale rapid single flux quantum (RSFQ) circuits. Due to the imperfect matching of the transmission lines between the driver and receiver, single flux quantum (SFQ) pulses are partially reflected. The round trip propagation time of these reflections can coincide with the following SFQ pulse, resulting in a decrease in bias margins or incorrect circuit behavior. This resonant effect depends upon the length of the PTL and the clock frequency of the signal. A methodology to reduce and manage this effect is the focus of this article. A closed-form expression describing the dependence of the resonance frequency on the length of the PTL is presented. This expression describes a set of forbidden lengths for PTL interconnect segments in RSFQ circuits. The proposed methodology and algorithm insert active PTL-based repeaters into long superconductive interconnect while ensuring the length of the line segment is outside the forbidden region and increasing bias margins.

The conversion method of netlists consisting of conventional logic gates to RSFQ circuits is proposed. It treats netlists for CMOS circuits as the design entry and converts them to the netlists of RSFQ circuits, considering the reduction of the number of clocked gates, including D flip-flops (DFFs) for path balancing. It utilizes two kinds of special RSFQ gates for the reduction. One is a confluence buffer that can be utilized for realizing logic- or . The other is a small resettable DFF which can be utilized as an NIMPLY gate with the tuning of the order of pulse arrivals. The detection methods of replaceable gates with those two kinds of gates are proposed. An automatic test pattern generation tool is utilized for detecting replaceable or gates to speed up the previously proposed detection method. To minimize the number of clocked gates considering the cost of replacements, the selection problem of gates for replacements with those special RSFQ gates and the assignment of a logic level for each gate are formulated as an instance of integer linear programming. The proposed conversion method has been evaluated with ISCAS85 circuits, a 32-bit ALU, and a 64-bit ALU. The evaluation results show that the number of clocked gates and the latency in the cycles of circuits is reduced by about 10%. The delay time of the converted circuits has been estimated and the reduction of delay overhead is discussed.

SFQ logic (such as RSFQ and ERSFQ) is one of the contenders for future low power, high-speed electronics. SFQ logic can also function as the interface to superconducting quantum qubits. It is therefore essential to have robust SFQ cell libraries that can be used in these designs. One significant challenge in SFQ circuit design is to find the best optimized design, starting from a nominal working circuit, that circuit designers should layout. Various optimization algorithms and tools are available (such as largest inscribed hypersphere, critical margin optimization, particle swarm, and various other algorithms), but all of them have different shortcomings that make them difficult to use with real-world cells. We present a new optimization algorithm, the distance-to-failure-maximization method, that uses some of the insight of the previous algorithms as well as a few new characteristics that make the optimization algorithm practical to use in real-world cases. We also provide an open-source implementation that was used to optimize real-world RSFQ cells for the ColdFlux project. We compare the optimization algorithm with other approaches and show the improvements above the current state of the art.

An automated layout design flow for rapid single-flux-quantum circuits is proposed in this article. In order to realize small circuit area and low latency, both Josephson transmission lines (JTLs) and passive transmission lines (PTLs) are used for interconnects. Placement and routing are performed considering effective use of JTLs and PTLs. Logic cells are grouped into clusters, and JTLs are used inside clusters. PTLs are used among clusters. The placement process is composed of three steps: first, cell clustering, second, cell placement and JTL routing in each cluster, and third, cluster placement. After the placement process, routing among clusters are performed using PTLs. We applied the proposed design flow to sample circuits with several hundreds of gates. Though the circuit area is not fully optimized, the latency of the circuits designed by the proposed design flow are lower than those of the circuits designed manually.

In recent years, rapid single flux quantum (RSFQ) circuits, which are promising for the development of high-speed digital electronics, have attracted widespread interest. Niobium nitride (NbN) films have also attracted significant attention for high-frequency applications in superconducting electronics because of their superior material parameters, including their high critical temperature T c and large gap voltage V g. To enable the development of all-NbN SFQ circuits, we have developed a fabrication process based on NbN junctions and inductors made of NbN strip lines. It is important to evaluate the inductance because it can affect the performance of an RSFQ circuit and is essential for the RSFQ design. We measured the inductance properties of both epitaxial and polycrystalline NbN strip lines using a superconducting quantum interference device modulation technique at 4.2 K and obtained the width dependence on the inductance of the NbN films. The penetration depth was then calculated from these measurements. The NbN inductance values were calculated numerically with respect to the penetration depth and were then compared with the measured values from the experiments. It was demonstrated that the differences between these values were within 5%. The results reported here will be useful for the design and fabrication of all-NbN RSFQ circuits.

With Moore's law approaching its physical limits, low-temperature computing technology is ushering in unprecedented development opportunities. Rapid single-flux-quantum (RSFQ) circuit technology is currently the most mature superconducting integrated circuit technology. Based on the current fabrication process, we propose an 8-bit bit-parallel RSFQ microprocessor. The proposed microprocessor processes 8-bit data each clock cycle. Ten different instructions are executed. The microprocessor mainly consists of an on-chip instruction memory, two data registers, an instruction decoder, an 8-bit bit-parallel arithmetic logic unit, and a program counter. The microprocessor contains 7702 JJs (based on the Open Dataset of CONNECT Cell Library for AIST ADP2) without considering splitters, Josephson transmission lines, and passive transmission lines. We perform a logic-level simulation of the proposed microprocessor. The simulation results show correct operation with a target frequency of 16.7 GHz.

Place and route tools for synthesized superconductor logic circuits, either for dc-biased rapid single flux quantum (RSFQ) or ac-biased adiabatic quantum flux parametron (AQFP), are required to automate the design of complex logic circuits. For hand-crafted circuit layout, logic cells, clock, and bias distribution, and signal interconnect can be optimized for tight fit and the adherence to design rules. For complex systems with thousands of logic gates, a hand-crafted approach is not efficient and automated place and route tools are a necessity. Such tools require logic cell layout for placement with a minimum set of rules, followed by an interconnect design that allows maximum routability and strict adherence to layer fill requirements. In this article, we present the design and characterization of a routing architecture that allows rule-based automated place and route for both RSFQ and AQFP logic families. We show that a layout tile size of 10 × 10 μm can be designed to accommodate all design rules for layout fill densities, passive transmission line routing, bias current distribution, and the vias needed to stitch multiple ground planes and provide shielded signal and bias tracks. We also characterize the performance of the layout architecture in terms of transmission line parameters and bias current coupling with powerful simulation tools developed for the SuperTools project. The result is a track layout that doubles as chip fill, is now used for integrated circuit layout under SuperTools and is also applicable to any similar fabrication process with at least eight superconductor metal layers.

Among the major issues in modern large-scale rapid single-flux quantum (RSFQ) circuits are the complexity of the clock network, tight timing tolerances, poor applicability of existing CMOS-based design algorithms, and extremely deep pipelines, which reduce the effective clock frequency. In this article, asynchronous dynamic single-flux quantum majority gates are proposed to solve some of these problems. The proposed logic gates exhibit high bias margins and do not require significant area or a large number of Josephson junctions as compared to existing RSFQ logic gates. These gates exhibit a tradeoff among the input skew tolerance, clock frequency, and bias margins. Asynchronous logic gates greatly reduce the complexity of the clock network in large-scale RSFQ circuits, thereby alleviating certain timing issues and reducing the required bias currents. Furthermore, asynchronous logic allows existing design algorithms to utilize CMOS approaches for synthesis, verification, and testability. The adoption of majority logic in complex RSFQ circuits also reduces the pipeline depth, enabling higher clock speeds in very large scale integration RSFQ circuits.

Rapid single flux quantum (RSFQ) logic, based on Josephson junctions (JJs), is seeing a resurgence as a way for providing high performance in the era beyond the end of physical scaling of complementary metal-oxide-semiconductor (CMOS). Due to its use of fabrication processes with large feature sizes, the defect density for RSFQ is lower than its CMOS counterpart. Hence, process variations and other RSFQ-specific nonidealities are major causes of chip failures. Because of the nature of its quantized pulse-based operation, even highly distorted pulses are interpreted logically correctly by cells, but the timings are affected. Therefore, timing verification and delay testing increase in importance in RSFQ. Our goal is to ensure that designs and fabricated chips provide desired performance. To achieve this goal, we propose new methods and tools for timing verification and delay testing of fully path balanced RSFQ logic circuits that use concurrent-flow clocking scheme. We address several radically new phenomena in the RSFQ technology, especially the existence of single-pattern delay tests and the need to propagate delayed values via multiple pipeline stages. We then characterize cells under process variations and identify delay excitation conditions, sensitization conditions, and conditions for propagation of the logic errors caused by timing violations due to process variations. We then propose a completely new paradigm for automatic test pattern generation (ATPG) which utilizes these new phenomena to select multicycle paths as targets and to generate test patterns that are guaranteed to excite the worst-case delay along each target multicycle path. Finally, we present theoretical proofs and Monte Carlo simulation results for benchmark circuits under process variations to demonstrate that the patterns generated by our new ATPG are effective (invoke maximum delays of target multicycle paths) and efficient (require small numbers of patterns).

Integrated circuit (IC) camouflaging is a defense to defeat image-based reverse engineering. The security of CMOS ICs has been extensively studied and camouflage techniques have been developed. A camouflaging method is introduced here to protect superconducting electronics, specifically, rapid single flux quantum (RSFQ) technology, from reverse engineering. RSFQ camouflaged units have been developed by applying the structural similarity of RSFQ standard cells. A defense using camouflaged RSFQ cells combined with obfuscating the temporal distribution of inputs to the IC increases the attacker's effort to decamouflage. The approach establishes the complexity class of RSFQ decamouflaging and a model checker is applied to evaluate the strength of the defenses. These techniques have been evaluated on ISCAS’85 combinational benchmarks and the controllers of the OpenSPARC T1 microprocessor. A dummy Josephson junction fabrication process adds two additional mask steps that increase the cost overhead. Camouflaging 100% of the benchmark circuits results in an area and power overhead of almost 40%. In the case of the OpenSPARC processor, the approach requires near-zero area, power, and performance overhead even when 100% of the sensitive parts of the processor are camouflaged.

Devices used for rapid single flux quantum (RSFQ) cell interconnects include passive transmission lines (PTLs) and Josephson transmission lines. In this article, we demonstrate software analysis methods with which reflections on PTLs can be improved through impedance matching without compromising the margins of the connected RSFQ logic cells. RSFQ cells are typically designed to connect to PTL transmitters and receivers before attaching the PTL interconnects. These transmitters and receivers are used as matching and buffer stages between the cell and the PTL; and can be adjusted to minimize impedance mismatching. We integrate PTL transmitters and receivers within the RSFQ cell to decrease the amount of Josephson junctions required to incorporate PTL interconnect functionality. Frequency domain analysis on each cell provides equivalent impedance characteristics used for impedance matching.

Recently, we demonstrated a rapid-single-flux-quantum NOT gate comprising a toggle storage loop. In this paper, we present our design and operation of a NOR gate that is a straightforward extension of the NOT gate by attaching a confluence buffer. Parameter margins wider than ±28% were confirmed in simulation. Functional tests using Nb integrated circuits demonstrated correct NOR operation with a bias margin of ±21%.

With the development of rapid single-flux-quantum (RSFQ) circuits, signal integrity issues of interconnects, such as signal distortion and crosstalk, become critical. Josephson junctions, as driver and receiver of interconnects, also affect signal integrity. Hence, it is significant to coanalyze time-domain responses of multicoupled passive transmission lines (PTLs) and Josephson junctions in RSFQ circuits. In this article, an accurate numerical method based on finite-difference time-domain (FDTD) is proposed to coanalyze multicoupled PTLs and Josephson junctions. The FDTD method is used to solve the telegraph equations of PTLs, and an iteration algorithm based on the contractive mapping theorem is proposed to solve the nonlinear equations generated by the Josephson junctions. In addition, the existence and uniqueness conditions of the nonlinear equations are also provided. The numerical and simulation results show that the proposed coanalysis method has the same accuracy as but higher efficiency than WRspice.

In this article, 8-bit bit-slice butterfly processing units (BPUs) are proposed for 64-point rapid single-flux-quantum (RSFQ) fast Fourier transform processors. The BPUs are based on radix-2, mixed-radix, and split-radix algorithms, respectively. Unlike the previously developed bit-serial RSFQ BPUs, the proposed bit-slice BPUs continuously process 64-point data divided into eight slices of eight points each in order to reduce the hardware cost. The BPUs use synchronous concurrent-flow clocking and they can be extended to any $n^2$ -point processing.

Energy-efficient rapid single flux quantum circuits having zero static power dissipation require a feeding Josephson junction transmission line (FJTL) to stabilize the power bus voltage. It is shown how a FJTL can be configured to obtain a desired current-bias window of constant delay, while preserving operability above and below that range as well, as a tradeoff against power and area. A test chip to validate circuit simulation results is designed with a gridded fabric for power delivery and cell placement, with consideration of passive transmission lines, magnetic flux exclusion, power bus isolation, and thermal noise. Measurements made on hardware fabricated in MIT Lincoln Lab's advanced 8-Nb-layer process correlate well with the model and indicate specific FJTL design challenges that need to be addressed.

Superconducting single flux quantum (SFQ) circuits have been shown to offer huge advantages that are ideal for high performance computing applications. These circuits can operate at very high frequencies (tens of GHz) but consume very low power (from nanowatts to microwatts per gate). Energy-efficient SFQ (ERSFQ) circuits, evolved from traditional rapid SFQ (RSFQ) circuits, were invented with the goal of elimination of static power dissipation. When compared with RSFQ circuits, ERSFQ circuits require a new biasing network that includes biasing Josephson junction(s), biasing inductor(s), and feeding Josephson transmission line(s). Some general suggestions on how to design the network have been offered, but a detailed analysis and optimization scenario for the network is still to be provided. In this paper, we first optimize the previously reported DC-biased two-Josephson junction per bit RSFQ shift register circuit, which can be used to provide a more robust, energy-efficient, and high memory capacity storage unit. The simulated power dissipation of 16-bit RSFQ shift register is 0.45 mu W per bit when operating at 21.7 GHz. We then convert the RSFQ-based shift register into an ERSFQ structure and investigate the effects of the ERSFQ bias network on the margins of the ERSFQ circuit. Finally, we propose a more comprehensive optimization method for the ERSFQ biasing network.

As superconducting circuits grow in complexity, full transient simulation and verification at the Josephson junction level using analog circuit simulators become increasingly computationally expensive. To enable faster functional and timing verification using timing back annotation and static timing analysis, logic models of rapid single flux quantum library cells are developed using hardware description languages like Verilog together with the required timing characteristics. These include propagation delays and minimum pin-to-pin pulse arrival time separation at various process and operating corners. These timing parameters must satisfy required margins and yield using Monte Carlo simulations with statistical variations. For each library cell, these timing parameters depend not only on the adjacent cells but also on their internal states. These delay variations are driven by bias current redistribution, load inductance, and load junction critical currents. We present our methodology for extracting these timing parameters to enable timing back annotation and static timing analysis. We demonstrate our methodology with a parallel counter as a reference circuit and show that timing back annotated simulation can closely match results from full circuit simulation.

The increasing complexity of modern rapid single flux quantum (RSFQ) circuits has made on-chip signal routing, an issue of growing importance. In this paper, several methods for routing large-scale RSFQ circuits are described, and a process is presented for determining when to use passive microstrip transmission lines (PTL) and active Josephson transmission lines (JTL). The effect of the size of the JTL inductor and Josephson junctions on the length of a JTL chain for a target delay is also discussed. The dependence of the JTL inductance on the physical layout is evaluated, and the effects of the primary PTL parameters on delay are characterized. A novel PTL driver and receiver configuration is also proposed. Tradeoffs among the number of JJs, inductance, and length of a PTL stripline in the receiver and driver circuits are reported. The energy dissipation is evaluated for two different interconnects. A tradeoff between the proposed PTL circuits and an optimized JTL in terms of energy dissipation and delay is discussed. Guidelines for choosing the optimal element values are determined, and a simulated bias margin of $\pm$ 29% for the bias current of the proposed receiver operating at 20 GHz in a 10 kA/cm $^2$ technology for a 1-mm transmission line is achieved. Summarizing, guidelines and design tradeoffs appropriate for automated layout and synthesis are provided for driving long interconnect in SFQ VLSI circuits.

Nb/Al-AlO x /Nb Josephson junctions are widely used in superconducting quantum interference devices and rapid single flux quantum (RSFQ) circuits. Very large-scale RSFQ integration often has a strict requirement on wafer-scale junction qualities. In particular, Nb film stress in Nb/Al-AlO x /Nb trilayer based Josephson junctions is a critical factor affecting their qualities. In this work, we develop a multi-step sputtering process to prepare Nb films with different combinations of stress and roughness to investigate the correlation between Nb film stress and junction quality. In particular, this method allows us to prepare Nb films with almost the same roughness but different stress, a key factor to study solely the influence of stress on junction qualities. Our measurements indicate that within a very tight range of film roughness (less than 2 nm), tensile film stress is found to decrease the quality of Nb/Al-AlO x /Nb Josephson junctions and larger film roughness has a positive effect on junction quality. By decreasing the total tensile stress and increasing the film roughness properly, we fabricated Nb/Al-AlO x /Nb Josephson junctions with a high quality factor characterized by $R_{sg}/ R_{N}$ (30 on average). The minimum size of junctions was 1 μm.

Long ago, current recycling or serial biasing technique was recognized as a promising solution for the reduction of bias current in VLSI dc biased digital superconductor circuits. Despite a significant number of declarations, not so many successful experiments have been reported so far. In the paper we discuss our recent experiments with serially biased 16-bit counter-flow RSFQ shift registers, connected by special interfaces that are able to transfer SFQ pulses between the galvanically isolated driver and receiver. The required functionality is achieved using a superconductor transformer with isolated input and output coils. The known drawback of such interfaces is their parasitic sensitivity to magnetic fields induced by remote currents. To depress this sensitivity we have implemented a special superconductor guard that uses six superconductor layers. We have achieved stable operations of such registers with 16 current recycling stacks. The circuits have been fabricated at MIT Lincoln Laboratory.

We designed and tested the digital readout circuitry for superconducting nanowire single-photon detectors (SNSPDs). The designed time-to-digital converter (TDC) comprises a decision-making block, a clock controller, and a counter with parallel-to-serial (P2S) interface. We also designed an on-chip pattern generator to imitate a digitized SNSPD response that allowed us to screen the circuitry without bonding actual SNSPDs. Both rapid single-flux quantum (RSFQ) and its energy-efficient rapid single-flux quantum (ERSFQ) versions were designed for comparison and debugging purposes. To optimize the design of the feeding Josephson transmission line (FJTL) required by the ERSFQ variant, we compared different power grid structures and types of FJTLs. Using an 8-bit counter with P2S interface as a device under test, we also investigated the effect of FJTL's size on the bias margins. FJTL with a 75% junction overhead is sufficient for the ERSFQ circuit to match the margins of its RSFQ counterpart. All chips have been fabricated at MIT-LL using the SFQ5ee process node. Experimental results and future research directions are presented.

Energy-efficient rapid single flux quantum (ERSFQ) circuits have become a viable alternative for the implementation of superconducting circuits due to a large amount of static power consumption in RSFQ circuits. ERSFQ circuits are built upon the popular RSFQ logic circuits by replacing the power-dissipating resistor bias network with a bias network consisting of active devices. In this paper, a simulation study of ERSFQ biasing scheme is carried out by building simulation test benches for both synchronous and asynchronous ERSFQ circuits. A study is carried out to present the optimum value of biasing inductance, influence of the feeding Josephson transmission line (FJTL) and the effect of its size, the effect of the feeding clock frequency, and the effect of the circuit operating frequency. An innovative clock-choking mechanism using magnetic Josephson junctions is also proposed for the FJTL in the case of no logic circuit activity for a current-recycling circuit block, which would help in eliminating the dynamic power consumed due to the switching of bias junctions in a logic circuit. Simulation results for current recycling ERSFQ circuits are presented along with a strategy for implementing large superconducting circuits.

This paper presents a path balancing technology mapping algorithm, which is a new algorithm for generating a mapping solution for a given Boolean network such that the average logic level difference among fanin gates of each gate in the network is minimized. Path balancing technology mapping is required in dc-biased Single Flux Quantum (SFQ) circuits for guaranteeing the correct operation, and it is beneficial in CMOS circuits to reduce the hazard issues. We present a dynamic programming based algorithm for path balancing technology mapping which generates optimal solutions for dc-biased SFQ (e.g. Rapid SFQ or RSFQ) circuits with tree structure and acts as an effective heuristic for circuits with general Directed Acyclic Graph (DAG) structure. Experimental results show that our path balancing technology mapper reduces the balancing overhead by up to 2.7 times and with an average of 21% compared to the state-of-the-art academic technology mappers.

Equivalence checking is a key component of the verification methodology for digital circuit designs. In this paper, we propose an equivalence checking framework for superconducting rapid single-flux-quantum (RSFQ) logic circuits which include acyclic circuits and bit-slice-based cyclic circuits. It consists of a structure checker and a logic checker. The structure checker is used to check whether the circuit meets the design rules of superconducting RSFQ logic circuits. The logic checker can be used to check whether two RSFQ gate-level circuits have the same logic function. For the logic checker, we propose a logic equivalence checking method based on logic cone partition. The circuit network is simplified layer by layer and iteratively partitioned into logic cones, each of which is verified by the SMT solver. The experimental results show the feasibility of our approach on superconducting RSFQ logic circuits.

Single flux quantum (SFQ) digital circuits have shown the potential for high speed/low power computation applications. Unfortunately, because of the low integration density and low driving capability of SFQ circuits, realizing large-scale memories by using only SFQ circuits is still a challenge. Josephson-CMOS hybrid memory, hybridizing high-speed, low power SFQ circuits, and high-density CMOS memories is already proposed as a solution to the large-scale memory problem in RSFQ digital systems. In this article, an SFQ-based memory controller which works up to 10 GHz clock frequencies is designed for Josephson-CMOS hybrid memory systems. The memory controller acts as a SFQ/CMOS interface between the SFQ circuit and SRAM module and generates the required waveforms for SRAM read and write operations. The circuit which has 4-b data and 2-b address lines is fabricated with AIST 2.5 kA/cm2 STP2 process and operations of the circuits are verified. To demonstrate the scalability of the circuit, memory controller was scaled to 8-b data and 13-b address to control of the 64kb SRAM. Operations of the scaled memory controller are verified with analog simulations. Scaled circuit consumes 0.76 mW power in an area of 1.64 mm × 1.60 mm.

We propose a scalable readout interface for superconducting nanowire single-photon detector (SSPD) arrays, which we call the AQFP/RSFQ interface. This interface is composed of adiabatic quantum-flux-parametron (AQFP) and rapid single-flux-quantum (RSFQ) logic families. The AQFP part reads out the spatial information of an SSPD array via a single cable, and the RSFQ part reads out the temporal information via a single cable. The hybrid interface has high temporal resolution owing to low timing jitter in the operation of the RSFQ part. In addition, the hybrid interface achieves high circuit scalability because of low supply current in the operation of the AQFP part. Therefore, the hybrid interface is suitable for handling many-pixel SSPD arrays. We demonstrate a four-pixel SSPD array using the hybrid interface as proof of concept. The measurement results show that the hybrid interface can read out all of the pixels with a low error rate and low timing jitter., 10 pages, 6 figures

A 32-bit 4 × 4 bit-slice rapid single-flux-quantum (RSFQ) matrix multiplier is proposed. The multiplier mainly consists of bit-slice multipliers and bit-slice adders. The multiplication of unsigned integer matrices is implemented by control signals. The matrix multiplier used synchronous concurrent-flow clocking. The results show that a 16-bit bit-slice processing has the least latency at 10 GHz.

Static timing analysis in the rapid-single-flux-quantum and energy-efficient RSFQ superconducting digital circuit domain is yet to be achieved in a generic sense. A static timing analysis tool is proposed here for preplacement designs as well as postplaced and routed designs. Preplaced static timing analysis attempts to find a general gauge for the performance of a JSIM/SPICE netlist in the absence of information on wiring delays. The postplaced and routed static timing analysis provides a more accurate analysis of a design in the cadence design exchange format. This design file should include all the wire lengths as well as a complete clocking scheme. Results of this postplaced and routed static timing analysis are then used to determine the maximum clock speed that the design can be run at to prevent timing violations. Results for both methods of analysis are presented and then incorporated in an hardware description language representation of the design to show that there are no timing violations at the presented clock speed. We show the implementation of a static timing analysis method developed as a precursor to the IARPA SuperTools project, and how it applies to circuits with H-tree and HL-tree clocking schemes.

A fast wire-routing method considering wire-length matching of passive transmission lines (PTLs) is proposed. The method deals with channel routing between adjacent columns of active devices, and generates paths of PTLs with specified additional length packed in compact area based on simulated annealing. It uses a generation method of paths from a sequence of symbols for searching solutions efficiently. An automatic layout tool is also shown. It consists of a placer and a router based on the proposed method. The placer uses total extension length of PTLs for length matching as one of the evaluation metrics for detailed placement using simulated annealing. By introducing this metric, total extension length in routing phase is reduced and compact layouts are obtained. Using the tool, design flow from HDL descriptions to layout generation can be established. As an experimental result, a layout of an adder designed by the tool is shown.